AT32F413
Series Reference Manual
2022.06.27
Page 125
Rev 2.00
and then writing to CTRL1 register clears the event.
6. End of communication.
11.4.2 I
2
C master communication flow
Initialization
1.
Porgram input clock to generate correct timing through the CLKFREQ bit in the I2C_CTRL2
register;
2.
Program I
2
C communication speed through the I2C_CLKCTRL bit in the clock control register;
3.
Program the maximum rising time of bus through the I2C_TMRISE register;
4.
Program the control register1
I2C_CTRL1;
5.
Enable peripherals, if the GENSTART bit is set, a Start condition is generated on the bus, and
the device enters master mode.
Slave address transmission
Slave address is divided into 7-bit and 10-bit modes. Whether it is transmitter mode or receiver mode
depends on the lowest address bit.
7-bit address mode:
Transmitter: When the lowest bit of the address sent is 0, the master enters transmitter mode.
Receiver: When the lowest bit of the address sent is 1, the master enters receiver mode.
10-bit address mode:
Transmitter: First send address head 0b11110xx0 (where xx refers to address [9: 8]), and then slave
address [7: 0], the master enters transmitter mode.
Receiver: First send slave address head 0b11110xx0 (where xx refers to address [9:8]) and then
address [7: 0], followed by the address head 0b11110xx1 (where xx refers to address [9: 8]), the
master enters receiver mode.
Master transmitter
Figure 11-5 Transfer sequence of master transmitter
Address
S
0
A
Data1
A
SCL
Stretch
Data2
A
DataN
A
P
Master to Slave
Slave to Master
S = Start
A = Acknowledge
P = Stop
Example : I2C Master transfer N bytes to I2C Slave .
EV1. I2C_STS1_STARTF=1, reading STS1 and write the address to I2C_DT will
clear the event.
EV2. I2C_STS1_ADDR7F= 1, reading STS1 and then STS2 will clear the event.
EV3. Both the internal shift register and the data register I2C_DT are empty,
I2C_STS1_TDBE = 1, the data is directly moved to the internal shift register
after Data1 is written.
EV4. I2C_DT writes Data, I2C_STS1_TDBE = 0
。
EV5. I2C_STS1 register TDBE and TDC bit = 1, software sets the stop condition to
clear the event
EV6. I2C_STS1_ADDRHF= 1,reading STS1 and write I2C_DT register will clear
the event.
EV2
EV3
EV4
EV5
...
TDBE
EV4
Address Head
S
A
Address
SCL
Stretch
A
Data1
A
Data2
A
DataN
A
P
EV4
EV5
...
EV4
SCL Stretch
EV2
EV4
EV4
EV6
7-bit address
10-bit address
R/W
0
R/W
SCL
Stretch
SCL
Stretch
EV1
EV1
EV3