ARM Prospector P1100, User Manual, Page: 31 / 154

Getting started
ARM DUI 0122A Copyright © ARM Limited 2000. All rights reserved. 2-7
2.5 System startup
When The P1100 powers up, the SA-1100 executes its first instruction from address
0x000000
(the reset vector). This is typically a jump instruction, because the first eight
words are reserved for exception vectors (known as hard vectors in the ARM
Architecture Reference Manual). The SA-1100 maps these addresses to static memory,
but these are remapped by the ARM Firmware Suite (AFS). The AFS carries out this
remapping as part of the initialization sequence, remapping the hard vectors to DRAM
for application use. For example, to implement a system- or application-specific
interrupt handler.
2.5.1 Boot switcher
The startup code for the P1100 includes a boot switcher routine. This reads SW5 in the
DIL switch pack and then, depending on the setting either runs the boot monitor or an
alternative image from flash. By using this mechanism, the boot switcher can relocate
the boot monitor to DRAM before it is invoked (which is necessary if you want to
reprogram the flash).
The boot switcher functions as follows:
• If the BOOTSEL switch (see Figure 2-2 on page 2-3) is LOW the boot monitor
code is executed. The boot monitor is a reserved image in flash, with the image
number 4280910 (
0x41524E
).
• If the BOOTSEL is (HIGH), the boot switcher:
— Searches for a System Information Block (SIB) stored in the flash.
— If a SIB is found, the image number is read and flash is examined for a
matching image.
— If an image match is detected, and the image has a valid CRC, the image is
either executed from flash, or downloaded to DRAM and then executed.
— If the boot switcher fails to find a valid image, or if the CRC fails, it
executes the boot monitor.
2.5.2 Memory initialization
The boot monitor and boot switcher both use the standard µHAL memory initialization
mechanism for The P1100. This tests the DRAM and remaps the memory spaces as
follows:
• Checks for a second bank, then concatenates the two banks of DRAM to a single
virtual address space starting at VA
0x00000000
.
• Remaps the flash to VA
0x04000000
.
• Maintains 1-to-1 mapped DRAM spaces for the fitted DRAM.