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Preface 

xiv

Copyright © 2007, 2008 ARM Limited. All rights reserved.

ARM DDI 0402B

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Summary of Contents for PL310

Page 1: ...Copyright 2007 2008 ARM Limited All rights reserved ARM DDI 0402B PrimeCell Level 2 MBIST Controller PL310 Revision r1p0 Technical Reference Manual ...

Page 2: ...nt are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in s...

Page 3: ...uction 1 1 About the MBIST controller 1 2 1 2 MBIST controller interface 1 3 1 3 Product revisions 1 7 Chapter 2 Functional Description 2 1 Functional overview 2 2 2 2 Functional operation 2 13 Chapter 3 MBIST Instruction Register 3 1 About the MBIST Instruction Register 3 2 3 2 Field descriptions 3 4 Appendix A Signal Descriptions A 1 MBIST controller interface signals A 2 A 2 Miscellaneous signa...

Page 4: ...Contents iv Copyright 2007 2008 ARM Limited All rights reserved ARM DDI 0402B ...

Page 5: ...d MBISTDIN mapping for tag RAM 8 way 2 8 Table 2 6 MBISTADDR and MBISTDIN mapping for tag RAM 16 way 2 8 Table 2 7 MBISTTX signals 2 10 Table 2 8 MBISTRX signals 2 11 Table 2 9 MBIST controller top level I O 2 11 Table 2 10 Data log format 2 15 Table 3 1 Pattern field encoding 3 4 Table 3 2 Go No Go test pattern 3 6 Table 3 3 Control field encoding 3 7 Table 3 4 Read latency field encoding 3 8 Tab...

Page 6: ...ved ARM DDI 0402B Table 3 10 Enables field encoding 3 15 Table 3 11 Column width field encoding 3 16 Table 3 12 Cache size field encoding 3 16 Table 3 13 Way size field encoding 3 17 Table A 1 MBIST controller interface signals A 2 Table A 2 Miscellaneous signals A 4 ...

Page 7: ...Cache controller compiled RAM latency 2 5 Figure 2 3 Cache controller MBIST paths for data RAM testing 2 7 Figure 2 4 Cache controller MBIST paths for tag RAM testing 2 9 Figure 2 5 MBIST controller block 2 10 Figure 2 6 Loading the MBIST controller instruction 2 13 Figure 2 7 Starting the MBIST test 2 14 Figure 2 8 Detecting an MBIST failure 2 14 Figure 2 9 Start of data log retrieval 2 15 Figure...

Page 8: ...List of Figures viii Copyright 2007 2008 ARM Limited All rights reserved ARM DDI 0402B ...

Page 9: ...ARM Limited All rights reserved ix Preface This preface introduces the PrimeCell Level 2 MBIST Controller PL310 Revision r1p0 Technical Reference Manual It contains the following sections About this manual on page x Feedback on page xiv ...

Page 10: ...troller to test the RAM blocks used by the cache controller The AXI protocol is not specified but some familiarity with AXI is assumed Using this manual This manual is organized into the following chapters Chapter 1 Introduction Read this chapter for an introduction to MBIST technology Chapter 2 Functional Description Read this chapter for a description of the cache controller interface to the MBI...

Page 11: ...e code monospace Denotes a permitted abbreviation for a command or option You can enter the underlined text instead of the full command or option name monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code and Angle brackets enclose replaceable terms for assembler syntax w...

Page 12: ...nals LOW for active LOW signals Lower case n At the start or end of a signal name denotes an active LOW signal Prefix A Denotes global Advanced eXtensible Interface AXI signals Prefix AR Denotes AXI read address channel signals Prefix AW Denotes AXI write address channel signals Prefix B Denotes AXI write response channel signals Prefix C Denotes AXI low power interface signals Prefix H Denotes Ad...

Page 13: ... b1111 is an eight bit wide binary value of b00001111 Additional reading This section lists publications by ARM and by third parties See http infocenter arm com help index jsp for access to ARM documentation ARM publications This manual contains information that is specific to the MBIST controller See the following documents for other relevant information AMBA AXI Protocol Specification ARM IHI 00...

Page 14: ...s or suggestions about this product contact your supplier giving the product name a concise explanation of your comments Feedback on this manual If you have any comments on this manual send email to errata arm com giving the title the number the relevant page number s to which your comments apply a concise explanation of your comments ARM also welcomes general suggestions for additions and improve...

Page 15: ...imited All rights reserved 1 1 Chapter 1 Introduction This chapter introduces the MBIST controller It contains the following sections About the MBIST controller on page 1 2 MBIST controller interface on page 1 3 Product revisions on page 1 7 ...

Page 16: ...perform memory testing of the Level 2 L2 cache RAM Note The example integration files provided with the MBIST controller only support a 16 way cache design MBIST mode takes priority over all other modes for example SCAN in that the L2 RAMs are only accessible to the MBIST controller when MBIST mode is activated with the MTESTON pin You must keep the MTESTON signal LOW during functional mode and th...

Page 17: ... cache controller Figure 1 2 MBIST controller wiring diagram Figure 1 3 on page 1 4 shows the traditional method of accessing a cache RAM for MBIST 0 67 7 1 0 675 6 71 07 6721 0 67 6 7 0 67581 0 676 7 0 675 68 7 Q5 6 7 0 67 287 0 67 7 0 675 6 71 07 6721 0 67 6 7 0 67581 0 676 7 0 67 7 1 0 675 68 7 0 67 0 67 0 67 5 0 67 1 0 67 0 67 0 67 5 0 67 1 07 6721 0 67 7 0 67 287 Q5 6 7 XWRPDWHG WHVW HTXLSPHQ...

Page 18: ...he maximum operating frequency it is not suitable for high performance designs Instead the MBIST controller uses an additional input to the existing functional multiplexors without reducing maximum operating frequency Figure 1 4 on page 1 5 shows the five pipeline stages used to access the cache RAM arrays DWD Q LVW DWD Q GGUHVV LVW GGUHVV LVW LVW LVW0RGH 5 0 DWD2XW LVW DWD2XW ...

Page 19: ...nterface signals 0 67 5 0 67 1 0 67 0 67 07 6721 0 67 7 URP GDWD SDWKV URP DGGUHVV SDWKV URP FKLS HQDEOHV URP ZULWH HQDEOHV 4 4 4 4 4 4 4 4 4 4 4 URP RWKHU 5 0 EORFNV 0 67 287 XQFWLRQDO RXWSXW 4 5 0 EORFN Table 1 1 Cache controller MBIST interface signals Name Type Description nRESET Input Global active LOW reset signal CLK Input Active HIGH clock signal This clock drives the cache controller logi...

Page 20: ...ed MBISTCE 17 0 MBISTADDR 1 0 MTESTON Input Select signal for cache RAM array This signal is the select input to the multiplexors that access the cache RAM arrays for test When asserted MTESTON takes priority over all other select inputs to the multiplexors MBISTCE 17 0 Input One hot chip enables to select cache RAM arrays for test MBISTWE 31 0 Input Global write enable signal for all RAM arrays M...

Page 21: ...d All rights reserved 1 7 1 3 Product revisions This section summarizes the differences in functionality between the releases of the MBIST controller r0p0 r1p0 The differences between these versions are Additional latency cycles in MBIST Instruction Register ...

Page 22: ...Introduction 1 8 Copyright 2007 2008 ARM Limited All rights reserved ARM DDI 0402B ...

Page 23: ... contains a functional overview and MBIST controller implementation The functional operation provides timing sequences for loading instructions starting the MBIST engine detecting failures and retrieving the data log It contains the following sections Functional overview on page 2 2 Functional operation on page 2 13 ...

Page 24: ... controller RAMS You can configure the following RAMs for up to eight cycles of latency data read data write tag read tag write See also Compiled RAM latencies on page 2 3 You can use the MBIST controller for testing the cache controller compiled RAMs You can also choose to design your own MBIST controller You can only access one RAM by the MBIST port at a time Note For the MBIST to run correctly ...

Page 25: ...ng the slowest compiled RAMs are being used This means sixteen cache controller clock cycles are used for each access In terms of reads this means that the read data is sampled eight clock edges after the edge on which the read request is sampled by the RAM Using this nomenclature the shortest latency is one During functional mode the latencies for each RAM are programmed in the cache 0 67 FRQWURO...

Page 26: ... compiled RAM latency Figure 2 2 on page 2 5 shows the cache controller compiled RAM latency Table 2 1 Cache controller compiled RAM latency Latency bits 3 0 Cycles of latency 4 b0000 1 cycle of latency No additional latency This is the default 4 b0001 2 cycles of latency 4 b0010 3 cycles of latency 4 b0011 4 cycles of latency 4 b0100 5 cycles of latency 4 b0101 6 cycles of latency 4 b0110 7 cycle...

Page 27: ...unt the data RAM latency and issues the correct control signals Table 2 2 shows the address range of the MBISTADDR bus used to test the data RAM based on the L2 cache size and configured to be 8 way GDWD GDWD GDWD KLS VHOHFW DFKH FRQWUROOHU FRPSLOHG 5 0 ODWHQF DFKH FRQWUROOHU FRPSLOHG 5 0 ODWHQF DFKH FRQWUROOHU FRPSLOHG 5 0 ODWHQF Table 2 2 MBISTADDR and MBISTDIN mapping for data RAM 8 way L2 cach...

Page 28: ...he latency can be from one to eight clock cycles See Compiled RAM latencies on page 2 3 The signal MBISTCE 0 is for the chip enable to the data RAM The signal MBISTDCTL 2 0 is for reads from previous MBIST transactions Figure 2 3 on page 2 7 shows the cache controller MBIST paths for data RAM testing Table 2 3 MBISTADDR and MBISTDIN mapping for data RAM 16 way L2 cache size Number of data RAM inde...

Page 29: ...AMs the MBIST controller has to test is 16 Only one tag RAM is tested at a time Table 2 5 on page 2 8 shows the address range of the MBISTADDR bus used to test a tag RAM based on the L2 cache size and configured to be 8 way The parity for each 0ELVWDGGU 0ELVWFH 0ELVWGLQ 0ELVWZH 7 5 7 6 7 1 7 7 5 0ELVWGFWO 0WHVWRQ DWD 5 0 5 0 67 287 0 67 5 0 67 K 0 67 1 0 67 7 0 67 07 6721 0WHVWRQ Table 2 4 Writes ...

Page 30: ... 1 024 TAGADDR 9 0 MBISTADDR 11 2 TAGWD 20 1 MBISTDIN 20 1 512KB 64KB 2 048 TAGADDR 10 0 MBISTADDR 12 2 TAGWD 20 2 MBISTDIN 20 2 1MB 128KB 4 096 TAGADDR 11 0 MBISTADDR 13 2 TAGWD 20 3 MBISTDIN 20 3 2MB 256KB 8 192 TAGADDR 12 0 MBISTADDR 14 2 TAGWD 20 4 MBISTDIN 20 4 4MB 512KB 16 384 TAGADDR 13 0 MBISTADDR 15 2 TAGWD 20 5 MBISTDIN 20 5 Table 2 6 MBISTADDR and MBISTDIN mapping for tag RAM 16 way L2 ...

Page 31: ... is for reads from previous MBIST transactions The latency of the tag RAMs can be from one to eight clock cycles See Compiled RAM latencies on page 2 3 Figure 2 4 shows the cache controller MBIST paths for tag RAM testing Figure 2 4 Cache controller MBIST paths for tag RAM testing Note MBISTCE 16 1 corresponds to TAGCS 15 0 MDBISTDCL 18 3 corresponds to TAG 15 0 Only 22 0 of MBISTDIN and MBISTDOUT...

Page 32: ...ate using the following signals MBISTTX 11 0 This signal is an output of the MBIST controller that goes to the dispatch unit Table 2 7 shows the signals 0 67 FRQWUROOHU LVSDWFK XQLW 0 677 0 675 0 67 FRQWUROOHU EORFN Table 2 7 MBISTTX signals MBISTTX bit Description 0 Reset address 1 Increment address 2 Access sacrificial row used during bang patterns 3 Invert data instruction data in 4 Checkerboar...

Page 33: ...e Table 2 8 shows the signals MBIST controller block top level I O The top level I O of the MBIST controller consists of the cache controller interface See Appendix A Signal Descriptions and the inputs and outputs shown in Table 2 9 Table 2 8 MBISTRX signals MBISTRX bit Description 0 Address instruction data out fail data out 1 Shadow pipeline empty 2 Nonsticky fail flag Table 2 9 MBIST controller...

Page 34: ... Any clocking during IDDQ capture cycles must have array chip select signals constrained MBISTRESULT 2 0 During tests the MBISTRESULT 1 signal indicates failures You can operate using two modes by configuring bit 5 of the engine control section of the instruction register If bit 5 is set the MBISTRESULT 1 signal is asserted for a single cycle for each failed compare If bit 5 is not set the MBISTRE...

Page 35: ...our ATE the faster clock relates to the clock driven by an on chip Phase Locked Loop PLL If you do not have an on chip PLL both clocks relate to the clock driven by your ATE Timing diagrams in the following sections show the procedures for operating the MBIST controller Instruction load Starting MBIST on page 2 14 Failure detection on page 2 14 Data log retrieval on page 2 14 Instruction load To l...

Page 36: ... MBISTRESULT 2 flag goes HIGH two cycles later Figure 2 8 Detecting an MBIST failure Note To ensure that the ATE can observe a failure at test speed specify a sticky fail in the MBIST instruction See Control field MBIR 54 49 on page 3 7 Data log retrieval During a test the MBIST controller automatically logs the first detected failure If required you can retrieve the data log at the end of the tes...

Page 37: ...ULT 0 two cycles after MBISTDSHIFT goes HIGH Figure 2 9 Start of data log retrieval When the last data log bit shifts out drive MBISTDSHIFT LOW as Figure 2 10 shows Figure 2 10 End of data log retrieval Table 2 10 shows the format of the data log 0 675 68 7 FRPSOHWH IODJ 0 67 6 7 0 675 68 7 GDWD ORJ VKLIW RXW 0 67581 0 675 68 7 0 67 6 7 0 675 68 7 0 67581 Table 2 10 Data log format Bits Descriptio...

Page 38: ...a RAM Each time a failure occurs the controller stops executing the current test and waits for you to begin shifting out the data log as Figure 2 11 shows Figure 2 11 Start of bitmap data log retrieval After you finish shifting and drive MBISTDSHIFT LOW the controller then resumes testing where it stopped as Figure 2 12 shows This process continues until the test algorithm completes A fault can ca...

Page 39: ...ter 3 MBIST Instruction Register This chapter describes how to use the MBIST Instruction Register MBIR to configure the mode of operation of the MBIST controller It contains the following sections About the MBIST Instruction Register on page 3 2 Field descriptions on page 3 4 ...

Page 40: ...ycles to enable a RAM read X addr Specifies the number of bits in the X address counter Y addr Specifies the number of bits in the Y address counter Data seed Specifies the four bit data background Enables Specifies the RAM under test Column width Specifies 4 8 16 or 32 columns per block of RAM Cache size Specifies a cache size of 128KB 256KB 512KB 1MB 2MB 4MB or 8MB Way size Specifies a way size ...

Page 41: ...ion Register ARM DDI 0402B Copyright 2007 2008 ARM Limited All rights reserved 3 3 Way configuration Specifies an 8 way or 16 way configuration Field descriptions on page 3 4 describes the MBIR fields in more detail ...

Page 42: ...ed with industry standard pattern algorithms and a bit line stress algorithm You can group algorithms together to create a specific memory test methodology for your product Table 3 1 describes the supported algorithms and Pattern specification on page 3 5 describes their use The N values in the table indicate the number of RAM accesses per address location and give an indication of the test time w...

Page 43: ... inverse Read Checkerboard This reads back the physical checkerboard pattern created by alternating the supplied data seed and its inverse For the next set of patterns the following notation describes the algorithm 0 represents the data seed 1 represents the inverse data seed w indicates a write operation r indicates a read operation indicates that the address is incremented indicates that the add...

Page 44: ...f the memory In the following algorithm description row 0 indicates a read or write of the data seed to the sacrificial row this is always the first row of the column being addressed w0 r0 w0 w0 row 0 6 r0 5 w0 row 0 r0 r0 Go No Go If you do not want to implement your own memory test strategy use the Go No Go test pattern that performs the algorithms that Table 3 2 shows This test suite provides a...

Page 45: ...atency and write latency fields of the MBIR are used to specify the read and write latency of the RAM under test Read and write latencies are the numbers of cycles that the RAM requires to complete read and write operations For example in a write to a RAM with a write latency of two cycles the RAM inputs are valid for a single cycle The next cycle is a NOP cycle with the chip enable negated Simila...

Page 46: ...ttings for write operations Table 3 4 Read latency field encoding Read latency MBIR 44 41 Number of cycles per read operation b0000 1 b0001 2 b0010 3 b0011 4 b0100 5 b0101 6 b0110 7 b0111 8 b1000 9 b1001 10 b1010 11 b1011 12 b1100 13 b1101 14 b1110 15 b1111 16 Table 3 5 Write latency field encoding Write latency MBIR 48 45 Number of cycles per write operation b0000 1 b0001 2 b0010 3 ...

Page 47: ... topology of the physical implementation of the RAM more accurately These two dimensions are controlled by two separate address counters the X address counter and the y address counter One counter can be incremented or decremented only when the other counter has expired The chosen test algorithm determines the counter that moves faster b0011 4 b0100 5 b0101 6 b0110 7 b0111 8 b1000 9 b1001 10 b1010...

Page 48: ...sult is eight or fewer bits they are all assigned to the X address for the row select Otherwise eight bits are used for the X address and any unassigned bits are added to the bits already assigned to the Y address and used for the block select Figure 3 2 shows an example topology for the Data RAM in a 256K level 2 cache Figure 3 2 Example data RAM topology The cache RAM in Figure 3 2 has a column ...

Page 49: ...r or lower than these produce incorrect results Note If the columns have fewer than 256 rows you must still assign address bits to the row address until all eight bits are used before assigning any to the block address If the cache RAM has more than 256 rows per column then the additional bits must be assigned to the block address This does not have any detrimental effects on the test coverage of ...

Page 50: ...ddress The X address field specifies the number of X address counter bits to use during test Table 3 7 shows the X address settings Table 3 6 Y address field encoding Y address MBIR 36 33 Number of counter bits b0010 Unsupported b0010 2 b0011 3 b0100 4 b0101 5 b0110 6 b0111 7 b1000 8 b1001 9 b1010 10 b1010 Reserved Table 3 7 X address field encoding X address MBIR 40 37 Number of counter bits b001...

Page 51: ... the X address and Y address fields for testing of data RAM b0101 5 b0110 6 b0111 7 b1000 8 b1001 9 b1010 10 b1010 Reserved Table 3 8 Required sums of X address and Y address fields for data RAM Cache size Data RAM 128KB 14 256KB 15 512KB 16 1MB 17 2MB 18 4MB 19 8MB 20 Table 3 7 X address field encoding continued X address MBIR 40 37 Number of counter bits ...

Page 52: ...ast and Bang algorithms do not use the data seed value Table 3 2 on page 3 6 shows the data that the Go No Go algorithm uses The data seed enables you to select values stored into arrays for IDDQ ATPG or to select data words to search for unexpected sensitivities during march or bit line stress tests The MBIST engine replicates the four bits of data 16 times to give the full 64 bits of data requir...

Page 53: ...nables field encoding Enables MBIR 28 11 RAM name b000000000000000001 Data b000000000000000010 Tag 0 b000000000000000100 Tag 1 b000000000000001000 Tag 2 b000000000000010000 Tag 3 b000000000000100000 Tag 4 b000000000001000000 Tag 5 b000000000010000000 Tag 6 b000000000100000000 Tag 7 b000000001000000000 Tag 8 b000000010000000000 Tag 9 b000000100000000000 Tag 10 b000001000000000000 Tag 11 b0000100000...

Page 54: ...ne stress testing and writing a true physical checkerboard pattern to the array Table 3 11 shows the supported column widths along with the number of LSB address bits used for each and the MBIR encodings required to select them 3 2 8 Cache size field MBIR 8 6 The cache size field specifies the size of the cache in your implementation of the module Table 3 12 shows the supported cache sizes Table 3...

Page 55: ...o 1 if parity is enabled 3 2 11 Lockdown by line support field MBIR 1 The lockdown by line support field specifies if lockdown by line is supported in your implementation Set to 1 if lockdown by line is enabled 3 2 12 Way configuration field MBIR 0 The way configuration field specifies an 8 way or 16 way configuration in your implementation Set to 0 for an 8 way configuration or 1 for a 16 way con...

Page 56: ...MBIST Instruction Register 3 18 Copyright 2007 2008 ARM Limited All rights reserved ARM DDI 0402B ...

Page 57: ...ARM Limited All rights reserved A 1 Appendix A Signal Descriptions This appendix describes the MBIST controller signals It contains the following sections MBIST controller interface signals on page A 2 Miscellaneous signals on page A 4 ...

Page 58: ...word select MBISTADDR 14 2 used for Tag RAM MBISTCE 17 0 Output MBIST RAM chip enables for writes MBISTCE 0 Data RAM chip enable MBISTCE 1 Tag RAM 0 chip enable MBISTCE 2 Tag RAM 1 chip enable MBISTCE 3 Tag RAM 2 chip enable MBISTCE 4 Tag RAM 3 chip enable MBISTCE 5 Tag RAM 4 chip enable MBISTCE 6 Tag RAM 5 chip enable MBISTCE 7 Tag RAM 6 chip enable MBISTCE 8 Tag RAM 7 chip enable MBISTCE 9 Tag R...

Page 59: ... select for Tag RAM 10 MBISTDCTL 14 MBIST RAM select for Tag RAM 11 MBISTDCTL 15 MBIST RAM select for Tag RAM 12 MBISTDCTL 16 MBIST RAM select for Tag RAM 13 MBISTDCTL 17 MBIST RAM select for Tag RAM 14 MBISTDCTL 18 MBIST RAM select for Tag RAM 15 MBISTDCTL 19 MBIST RAM select for data parity MBISTDIN 63 0 Output MBIST Data In to cache controller MBISTDIN 63 0 MBIST data in for Data RAM MBISTDIN 2...

Page 60: ...nals Table A 2 Miscellaneous signals Signal Type Description nRESET Input Global active LOW reset signal CLK Input Clock MBISTDATAIN Input Serial data in MBISTDSHIFT Input Data log shift MBISTRESETN Input MBIST reset MBISTRESULT 2 0 Output Output status bus MBISTRUN Input Run MBIST test MBISTSHIFT Input Instruction shift MTESTON Input MBIST Mode Enable ...

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