Cortex-M4 Peripherals
ARM DUI 0553A
Copyright © 2010 ARM. All rights reserved.
4-30
ID121610
Non-Confidential
4.3.11
HardFault Status Register
The HFSR gives information about events that activate the HardFault handler. See the register
summary in
for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing
1 to any bit clears that bit to 0. The bit assignments are:
Note
The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to
1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
4.3.12
MemManage Fault Address Register
The MMFAR contains the address of the location that generated a MemManage fault. See the
register summary in
for its attributes. The bit assignments are:
31 30
2 1 0
Reserved
29
DEBUGEVT
FORCED
VECTTBL
Reserved
Table 4-28 HFSR bit assignments
Bits
Name
Function
[31]
DEBUGEVT
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise
behavior is Unpredictable.
[30]
FORCED
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that
cannot be handles, either because of priority or because it is disabled:
0 = no forced HardFault
1 = forced HardFault.
When this bit is set to 1, the HardFault handler must read the other fault status registers to find
the cause of the fault.
[29:2]
-
Reserved.
[1]
VECTTBL
Indicates a BusFault on a vector table read during exception processing:
0 = no BusFault on vector table read
1 = BusFault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that was preempted by the exception.
[0]
-
Reserved.
Table 4-29 MMFAR bit assignments
Bits Name
Function
[31:0]
ADDRESS
When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location
that generated the MemManage fault