Cortex-M4 Peripherals
ARM DUI 0553A
Copyright © 2010 ARM. All rights reserved.
4-16
ID121610
Non-Confidential
4.3.4
Vector Table Offset Register
The VTOR indicates the offset of the vector table base address from memory address
0x00000000
for its attributes. The bit
assignments are:
When setting TBLOFF, you must align the offset to the number of exception entries in the vector
table. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts,
adjust the alignment by rounding up to the next power of two. For example, if you require 21
interrupts, the alignment must be on a 64-word boundary because the required table size is 37
words, and the next power of two is 64. See your vendor documentation for the alignment details
of your device.
Note
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
4.3.5
Application Interrupt and Reset Control Register
The AIRCR provides priority grouping control for the exception model, endian status for data
accesses, and reset control of the system. See the register summary in
for its attributes.
To write to this register, you must write
0x5FA
to the VECTKEY field, otherwise the processor
ignores the write.
31
7 6
0
TBLOFF
Reserved
Table 4-16 VTOR bit assignments
Bits
Name
Function
[31:7]
TBLOFF
Vector table base offset field. It contains bits[29:7] of the offset of the table base from the bottom
of the memory map.
Note
Bit[29] determines whether the vector table is in the code or SRAM memory region:
•
0 = code
•
1 = SRAM.
In implementations bit[29] is sometimes called the TBLBASE bit.
[6:0]
-
Reserved.
