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Introduction

ARM DUI 0553A

Copyright © 2010 ARM. All rights reserved.

1-2

ID121610

Non-Confidential

1.1

About the Cortex-M4 processor and core peripherals

The Cortex-M4 processor is a high performance 32-bit processor designed for the
microcontroller market. It offers significant benefits to developers, including:
•

outstanding processing performance combined with fast interrupt handling

•

enhanced system debug with extensive breakpoint and trace capabilities

•

efficient processor core, system and memories

•

ultra-low power consumption with integrated sleep mode and an optional deep sleep
mode

•

platform security robustness, with optional integrated

Memory Protection Unit

(MPU).

Figure 1-1 Cortex-M4 implementation

The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively
optimized design, providing high-end processing hardware including optional
IEEE754-compliant single-precision floating-point computation, a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and
dedicated hardware division.

To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements
tightly-coupled system components that reduce processor area while significantly improving
interrupt handling and system debug capabilities. The Cortex-M4 processor implements a
version of the Thumb

®

instruction set based on Thumb-2 technology, ensuring high code density

and reduced program memory requirements. The Cortex-M4 instruction set provides the
exceptional performance expected of a modern 32-bit architecture, with the high code density
of 8-bit and 16-bit microcontrollers.

The Cortex-M4 processor closely integrates a configurable

Nested Vectored Interrupt

Controller

(NVIC), to deliver industry-leading interrupt performance. The NVIC includes a

Non Maskable Interrupt

(NMI) that can provide up to 256 interrupt priority levels. The tight

integration of the processor core and NVIC provides fast execution of

Interrupt Service

Optional

Embedded

Trace Macrocell

NVIC

Optional

Debug

Access Port

Optional Memory

protection unit

Optional

WIC

Optional

Serial Wire

viewer

Bus matrix

Code

interface

SRAM and

peripheral interface

Optional

Data

watchpoints

Optional

Flash
patch

Cortex-M4

processor

Optional FPU

Processor

core

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Summary of Contents for Cortex-M4

Page 1: ...Copyright 2010 ARM All rights reserved ARM DUI 0553A ID121610 Cortex M4 Devices Generic User Guide ...

Page 2: ...oduct and its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM shall not be liable for any loss or damage arising from the use of any information in this docu...

Page 3: ...el 2 21 2 4 Fault handling 2 29 2 5 Power management 2 32 Chapter 3 The Cortex M4 Instruction Set 3 1 Instruction set summary 3 2 3 2 CMSIS functions 3 9 3 3 About the instruction descriptions 3 11 3 4 Memory access instructions 3 22 3 5 General data processing instructions 3 39 3 6 Multiply and divide instructions 3 74 3 7 Saturating instructions 3 95 3 8 Packing and unpacking instructions 3 107 ...

Page 4: ...ipherals 4 1 About the Cortex M4 peripherals 4 2 4 2 Nested Vectored Interrupt Controller 4 3 4 3 System control block 4 11 4 4 System timer SysTick 4 33 4 5 Optional Memory Protection Unit 4 37 4 6 Floating Point Unit FPU 4 48 Appendix A Cortex M4 Options A 1 Cortex M4 implementation options A 2 Glossary ...

Page 5: ...yright 2010 ARM All rights reserved v ID121610 Non Confidential Preface This preface introduces the Cortex M4 Devices Generic User Guide It contains the following sections About this book on page vi Feedback on page ix ...

Page 6: ... The rnpn identifier indicates the revision status of the product described in this book where rn Identifies the major revision of the product pn Identifies the minor revision or modification status of the product Intended audience This book is written for application and system level software developers familiar with programming who want to program a device that includes the Cortex M4 processor U...

Page 7: ...s internal cross references and citations bold Used for terms in descriptive lists where appropriate monospace Denotes text that you can enter at the keyboard such as commands file and program names and source code monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value and Enclose replaceable terms for assembler syntax where they appear in cod...

Page 8: ...ding the Cortex Microcontroller Software Interface Standard CMSIS ARM publications This book contains information that is specific to this product See the following documents for other relevant information Cortex M4 Technical Reference Manual ARM DDI 0439 ARMv7 M Architecture Reference Manual ARM DDI 0403 Other publications This guide only provides generic information for devices that implement th...

Page 9: ... on this product and its documentation Feedback on content If you have comments on content then send an e mail to errata arm com Give the title the number ARM DUI 0553A the page numbers to which your comments apply a concise explanation of your comments ARM also welcomes general suggestions for additions and improvements ...

Page 10: ...All rights reserved 1 1 ID121610 Non Confidential Chapter 1 Introduction This chapter introduces the Cortex M4 processor and its features It contains the following section About the Cortex M4 processor and core peripherals on page 1 2 ...

Page 11: ...cycle and SIMD multiplication and multiply with accumulate capabilities saturating arithmetic and dedicated hardware division To facilitate the design of cost sensitive devices the Cortex M4 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities The Cortex M4 processor implements a version of ...

Page 12: ...port that is ideal for microcontrollers and other small package devices For system trace the processor integrates an Instrumentation Trace Macrocell ITM alongside data watchpoints and a profiling unit To enable simple and cost effective profiling of the system events these generate a Serial Wire Viewer SWV can export a stream of software generated messages data trace and profiling information thro...

Page 13: ...Nested Vectored Interrupt Controller The NVIC is an embedded interrupt controller that supports low latency interrupt processing System Control Block The System Control Block SCB is the programmers model interface to the processor It provides system implementation information and system control including configuration control and reporting of system exceptions System timer The system timer SysTick...

Page 14: ...Confidential Chapter 2 The Cortex M4 Processor This chapter describes the Cortex M4 processor It contains the following sections Programmers model on page 2 2 Memory model on page 2 12 Exception model on page 2 21 Fault handling on page 2 29 Power management on page 2 32 ...

Page 15: ...r software execution is privileged or unprivileged see CONTROL register on page 2 9 In Handler mode software execution is always privileged Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software 2 1 2 Stacks T...

Page 16: ...ither Unknown Stack Pointer on page 2 4 LR RW Either 0xFFFFFFFF Link Register on page 2 4 PC RW Either See description Program Counter on page 2 4 PSR RW Privileged 0x01000000 Program Status Register on page 2 4 ASPR RW Either Unknown Application Program Status Register on page 2 5 IPSR RO Privileged 0x00000000 Interrupt Program Status Register on page 2 6 EPSR RO Privileged 0x01000000 Execution P...

Page 17: ...ins the current program address On reset the processor loads the PC with the value of the reset vector which is at address 0x00000004 Bit 0 of the value is loaded into the EPSR T bit at reset and must be 1 Program Status Register The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status Register EPSR These regi...

Page 18: ...y in Table 2 2 on page 2 3 for its attributes The bit assignments are Table 2 3 PSR register combinations Register Type Combination PSR RWa b a The processor ignores writes to the IPSR bits b Reads of the EPSR bits return zero and the processor ignores writes to the these bits APSR EPSR and IPSR IEPSR RO EPSR and IPSR IAPSR RWa APSR and IPSR EAPSR RWb APSR and EPSR Table 2 4 APSR bit assignments B...

Page 19: ...ter summary in Table 2 2 on page 2 3 for the EPSR attributes The bit assignments are Table 2 5 IPSR bit assignments Bits Name Function 31 9 Reserved 8 0 ISR_NUMBER This is the number of the current exception 0 Thread mode 1 Reserved 2 NMI 3 HardFault 4 MemManage 5 BusFault 6 UsageFault 7 10 Reserved 11 SVCall 12 Reserved for Debug 13 Reserved 14 PendSV 15 SysTick 16 IRQ0 n 15 IRQ n 1 a see Excepti...

Page 20: ...ions following an IT instruction Each instruction in the block is conditional The conditions for the instructions are either all the same or some can be the inverse of others See IT on page 3 122 for more information Thumb state The Cortex M4 processor only supports execution of instructions in Thumb state The following can clear the T bit to 0 instructions BLX BX and POP PC restoration from the s...

Page 21: ... Non Maskable Interrupt NMI See the register summary in Table 2 2 on page 2 3 for its attributes The bit assignments are The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler Table 2 7 PRIMASK register bit assignments Bits Name Function 31 1 Reserved 0 PRIMASK 0 no effect 1 prevents the activation of all exceptions with configurable priority Table 2 ...

Page 22: ... bit assignments Bits Name Function 31 8 Reserved 7 0 BASEPRIa Priority mask bits 0x00 no effect Nonzero defines the base priority for exception processing The processor does not process any exception with a priority value greater than or equal to BASEPRI a This field is similar to the priority fields in the interrupt priority registers Register priority value fields are eight bits wide and non im...

Page 23: ...ges the normal flow of software control The processor uses Handler mode to handle all exceptions except for reset See Exception entry on page 2 26 and Exception return on page 2 28 for more information The NVIC registers control interrupt handling See Nested Vectored Interrupt Controller on page 4 3 for more information 2 1 5 Data types The processor supports the following data types 32 bit words ...

Page 24: ...eripherals This document includes the register names defined by the CMSIS and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals Note This document uses the register short names defined by the CMSIS In a few cases these differ from the architectural short names that might be used in other documents The following sections give more information a...

Page 25: ... 2 2 2 1 Memory regions types and attributes The memory map and programming the optional MPU splits the memory map into regions Each region has a defined memory type and some regions have additional memory attributes The memory type and attributes determine the behavior of accesses to the region The memory types are Normal The processor can re order transactions for efficiency or perform speculati...

Page 26: ...e processor prevents instruction accesses A fault exception is generated only on execution of an instruction executed from an XN region 2 2 2 Memory system ordering of memory accesses For most memory accesses caused by explicit memory access instructions the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions providing this d...

Page 27: ...n 0x00000000 0x1FFFFFFF Code Normal Executable region for program code You can also put data here 0x20000000 0x3FFFFFFF SRAM Normal Executable region for data You can also put code here This region includes bit band and bit band alias areas see Table 2 13 on page 2 16 0x40000000 0x5FFFFFFF Peripheral Device XN This region includes bit band and bit band alias areas see Table 2 14 on page 2 16 0x600...

Page 28: ...sor provides the following memory barrier instructions DMB The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions See DMB on page 3 160 DSB The Data Synchronization Barrier DSB instruction ensures that outstanding memory transactions complete before subsequent instructions execute See DSB on page 3 161 ISB The Instruction...

Page 29: ..._offset is the position of the target bit in the bit band memory region Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit Bit_band_base is the starting address of the alias region Byte_offset is the number of the byte in the bit band region that contains the targeted bit Table 2 13 SRAM memory bit banding regions Address range Memory region Instructi...

Page 30: ...ue written to the targeted bit in the bit band region Writing a value with bit 0 set to 1 writes a 1 to the bit band bit and writing a value with bit 0 set to 0 writes a 0 to the bit band bit Bits 31 1 of the alias word have no effect on the bit band bit Writing 0x01 has the same effect as writing 0xFF Writing 0x00 has the same effect as writing 0x0E Reading a word in the alias region 0x00000000 i...

Page 31: ...he processor stores the most significant byte of a word at the lowest numbered byte and the least significant byte at the highest numbered byte For example Little endian format In little endian format the processor stores the least significant byte of a word at the lowest numbered byte and the most significant byte at the highest numbered byte For example 2 2 7 Synchronization primitives The Corte...

Page 32: ...truction to attempt to write the new value back to the memory location 4 Test the returned status bit If this bit is 0 The read modify write completed successfully 1 No write was performed This indicates that the value returned at step 1 might be out of date The software must retry the entire read modify write sequence Software can use the synchronization primitives to implement a semaphores as fo...

Page 33: ...e information about the synchronization primitive instructions see LDREX and STREX on page 3 36 and CLREX on page 3 38 2 2 8 Programming hints for the synchronization primitives ISO IEC C cannot directly generate the exclusive access instructions CMSIS provides functions for generation of these instructions Table 2 15 CMSIS functions for exclusive access instructions Instruction CMSIS function LDR...

Page 34: ...exception is being serviced by the processor and there is a pending exception from the same source 2 3 2 Exception types The exception types are Reset Reset is invoked on power up or a warm reset The exception model treats reset as a special form of exception When reset is asserted the operation of the processor stops potentially at any point in an instruction When reset is deasserted execution re...

Page 35: ...n exception that is triggered by the SVC instruction In an OS environment applications can use SVC instructions to access OS kernel functions and device drivers PendSV PendSV is an interrupt driven request for system level service In an OS environment use PendSV for context switching when no other exception is active SysTick A SysTick exception is an exception the system timer generates when it re...

Page 36: ...hat are handled by system handlers 2 3 4 Vector table The vector table contains the reset value of the stack pointer and the start addresses also called exception vectors for all exception handlers Figure 2 2 on page 2 24 shows the order of the exception vectors in the vector table The least significant bit of each vector must be 1 indicating that the exception handler is Thumb code see Thumb stat...

Page 37: ...e does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For information about configuring exception priorities see System Handler Priority Registers on page 4 21 Interrupt Priority Registers on page 4 7 Note Configurable priority values are in the range 0 This means that the Reset HardFault and NMI exceptions with fixed negative priority values alw...

Page 38: ...ndled does not preempt the handler If multiple pending interrupts have the same group priority the subpriority field determines the order in which they are processed If multiple pending interrupts have the same group priority and subpriority the interrupt with the lowest IRQ number is processed first For information about splitting the interrupt priority fields into group priority and subpriority ...

Page 39: ...ority than the exception being handled in which case the new exception preempts the original exception When one exception preempts another the exceptions are nested Sufficient priority means the exception has more priority than any limits set by the mask registers see Exception mask registers on page 2 7 An exception with less priority than this is pending but is not handled by the processor When ...

Page 40: ...handler At the same time the processor writes an EXC_RETURN value to the LR This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred If no higher priority exception occurs during exception entry the processor starts executing the exception handler and automatically changes the status of the corresponding pending interr...

Page 41: ...5 set to one When this value is loaded into the PC it indicates to the processor that the exception is complete and the processor initiates the appropriate exception return sequence Table 2 17 Exception return behavior EXC_RETURN 31 0 Description 0xFFFFFFF1 Return to Handler mode exception return uses non floating point state from the MSP and execution uses MSP after return 0xFFFFFFF9 Return to Th...

Page 42: ...er bit that indicates that the fault has occurred See Configurable Fault Status Register on page 4 24 for more information about the fault status registers Table 2 18 Faults Fault Handler Bit name Fault status register Bus error on a vector read HardFault VECTTBL HardFault Status Register on page 4 30 Fault escalated to a hard fault FORCED MPU or default memory map mismatch MemManage on instructio...

Page 43: ... is servicing This is because the handler for the new fault cannot preempt the currently executing fault handler An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception A fault occurs and the handler for that fault is not enabled If a BusFault occurs during a stack push when entering a BusFault handler the BusFault does not escalate...

Page 44: ... lockup state it does not execute any instructions The processor remains in lockup state until either it is reset an NMI occurs it is halted by a debugger Note If lockup state occurs from the NMI handler a subsequent NMI does not cause the processor to leave lockup state Table 2 19 Fault status and fault address registers Handler Status register name Address register name Register description Hard...

Page 45: ...e processor back to sleep mode Wait for interrupt The Wait For Interrupt instruction WFI causes immediate entry to sleep mode unless the wake up condition is true see Wakeup from WFI or sleep on exit on page 2 33 When the processor executes a WFI instruction it stops executing instructions and enters sleep mode See WFI on page 3 169 for more information Wait for event The Wait For Event instructio...

Page 46: ...iggers an event and wakes up the processor even if the interrupt is disabled or has insufficient priority to cause exception entry For more information about the SCR see System Control Register on page 4 19 2 5 3 The optional Wakeup Interrupt Controller Your device might include a Wakeup Interrupt Controller WIC an optional peripheral that can detect an interrupt and wake the processor from deep s...

Page 47: ...e 2 32 and the documentation supplied by your device vendor for more information about this signal 2 5 5 Power management programming hints ISO IEC C cannot directly generate the WFI and WFE instructions The CMSIS provides the following functions for these instructions void __WFE void Wait for Event void __WFI void Wait for Interrupt ...

Page 48: ...ns on page 3 11 Each of the following sections describes a functional group of Cortex M4 instructions Together they describe all the instructions supported by the Cortex M4 processor Memory access instructions on page 3 22 General data processing instructions on page 3 39 Multiply and divide instructions on page 3 74 Saturating instructions on page 3 95 Packing and unpacking instructions on page 3...

Page 49: ... C V page 3 41 ADD ADDS Rd Rn Op2 Add N Z C V page 3 41 ADD ADDW Rd Rn imm12 Add page 3 41 ADR Rd label Load PC relative Address page 3 23 AND ANDS Rd Rn Op2 Logical AND N Z C page 3 44 ASR ASRS Rd Rm Rs n Arithmetic Shift Right N Z C page 3 46 B label Branch page 3 119 BFC Rd lsb width Bit Field Clear page 3 115 BFI Rd Rn lsb width Bit Field Insert page 3 115 BIC BICS Rd Rn Op2 Bit Clear N Z C pa...

Page 50: ... Load Register with Halfword page 3 22 LDRSB LDRSBT Rt Rn offset Load Register with Signed Byte page 3 22 LDRSH LDRSHT Rt Rn offset Load Register with Signed Halfword page 3 22 LDRT Rt Rn offset Load Register with word page 3 22 LSL LSLS Rd Rm Rs n Logical Shift Left N Z C page 3 46 LSR LSRS Rd Rm Rs n Logical Shift Right N Z C page 3 46 MLA Rd Rn Rm Ra Multiply with Accumulate 32 bit result page ...

Page 51: ... halfword page 3 53 REVSH Rd Rn Reverse byte order in bottom halfword and sign extend page 3 53 ROR RORS Rd Rm Rs n Rotate Right N Z C page 3 46 RRX RRXS Rd Rm Rotate Right with Extend N Z C page 3 46 RSB RSBS Rd Rn Op2 Reverse Subtract N Z C V page 3 41 SADD16 Rd Rn Rm Signed Add 16 GE page 3 54 SADD8 Rd Rn Rm Signed Add 8 GE page 3 54 SASX Rd Rn Rm Signed Add and Subtract with Exchange GE page 3...

Page 52: ...Rm Signed dual Multiply Add Q page 3 89 SMULBB SMULBT SMULTB SMULTT Rd Rn Rm Signed Multiply halfwords page 3 91 SMULL RdLo RdHi Rn Rm Signed Multiply 32 x 32 64 bit result page 3 93 SMULWB SMULWT Rd Rn Rm Signed Multiply word by halfword page 3 91 SMUSD SMUSDX Rd Rn Rm Signed dual Multiply Subtract page 3 89 SSAT Rd n Rm shift s Signed Saturate Q page 3 96 SSAT16 Rd n Rm Signed Saturate 16 Q page...

Page 53: ...igned Add 16 GE page 3 63 UADD8 Rd Rn Rm Unsigned Add 8 GE page 3 63 USAX Rd Rn Rm Unsigned Subtract and Add with Exchange GE page 3 64 UHADD16 Rd Rn Rm Unsigned Halving Add 16 page 3 66 UHADD8 Rd Rn Rm Unsigned Halving Add 8 page 3 66 UHASX Rd Rn Rm Unsigned Halving Add and Subtract with Exchange page 3 67 UHSAX Rd Rn Rm Unsigned Halving Subtract and Add with Exchange page 3 67 UHSUB16 Rd Rn Rm U...

Page 54: ...e 3 117 UXTB16 Rd Rm ROR n Unsigned Extend Byte 16 page 3 117 UXTH Rd Rm ROR n Zero extend a Halfword page 3 117 VABS F32 Sd Sm Floating point Absolute page 3 128 VADD F32 Sd Sn Sm Floating point Add page 3 129 VCMP F32 Sd Sm 0 0 Compare two floating point registers or one floating point register and zero FPSCR page 3 130 VCMPE F32 Sd Sm 0 0 Compare two floating point registers or one floating poi...

Page 55: ... Dn x Copy scalar to ARM core register page 3 142 VMRS Rt FPSCR Move FPSCR to ARM core register or APSR N Z C V page 3 146 VMSR FPSCR Rt Move to FPSCR from ARM Core register FPSCR page 3 147 VMUL F32 Sd Sn Sm Floating point Multiply page 3 148 VNEG F32 Sd Sm Floating point Negate page 3 149 VNMLA F32 Sd Sn Sm Floating point Multiply and Add page 3 150 VNMLS F32 Sd Sn Sm Floating point Multiply and...

Page 56: ...IS functions to generate some Cortex M4 instructions Instruction CMSIS function CPSIE I void __enable_irq void CPSID I void __disable_irq void CPSIE F void __enable_fault_irq void CPSID F void __disable_fault_irq void ISB void __ISB void DSB void __DSB void DMB void __DMB void REV uint32_t __REV uint32_t int value REV16 uint32_t __REV16 uint32_t int value REVSH uint32_t __REVSH uint32_t int value ...

Page 57: ... ID121610 Non Confidential MSP Read uint32_t __get_MSP void Write void __set_MSP uint32_t TopOfMainStack PSP Read uint32_t __get_PSP void Write void __set_PSP uint32_t TopOfProcStack Table 3 3 CMSIS functions to access the special registers continued Special register Access CMSIS function ...

Page 58: ... The following sections give more information about using the instructions Operands on page 3 12 Restrictions when using PC or SP on page 3 12 Flexible second operand on page 3 12 Shift Operations on page 3 13 Address alignment on page 3 17 PC relative expressions on page 3 17 Conditional execution on page 3 18 Instruction width selection on page 3 21 ...

Page 59: ...d the Cortex M4 processor only supports Thumb instructions 3 3 3 Flexible second operand Many general data processing instructions have a flexible second operand This is shown as Operand2 in the descriptions of the syntax of each instruction Operand2 can be a Constant Register with optional shift on page 3 13 Constant You specify an Operand2 constant in the form constant where constant can be any ...

Page 60: ... with certain instructions For information on the shift operations and how they affect the carry flag see Shift Operations 3 3 4 Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits the shift length Register shift can be performed directly by the instructions ASR LSR LSL ROR and RRX and the result is written to a destination register du...

Page 61: ... register Rm to the right by n places into the right hand 32 n bits of the result And it sets the left hand n bits of the result to 0 See Figure 3 2 You can use the LSR n operation to divide the value in the register Rm by 2n if the value is regarded as an unsigned integer When the instruction is LSRS or when LSR n is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or...

Page 62: ...gister Rm to the right by n places into the right hand 32 n bits of the result And it moves the right hand n bits of the register into the left hand n bits of the result See Figure 3 4 When the instruction is RORS or when ROR n is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to the last bit rotation bit n 1 of the register Rm Note I...

Page 63: ...The Cortex M4 Instruction Set ARM DUI 0553A Copyright 2010 ARM All rights reserved 3 16 ID121610 Non Confidential Figure 3 5 RRX 30 Carry Flag 0 31 1 ...

Page 64: ... ARM recommends that programmers ensure that accesses are aligned To trap accidental generation of unaligned accesses use the UNALIGN_TRP bit in the Configuration and Control Register see Configuration and Control Register on page 4 19 3 3 6 PC relative expressions A PC relative expression or label is a symbol that represents the address of an instruction or literal data It is represented in the i...

Page 65: ... using conditional branches or by adding condition code suffixes to instructions See Table 3 4 on page 3 19 for a list of the suffixes to add to instructions to make them conditional instructions The condition code suffix enables the processor to test a condition based on the flags If the condition test of a conditional instruction fails the instruction does not execute does not write any value to...

Page 66: ...gative value if subtracting a positive value from a negative value generates a positive value if subtracting a negative value from a positive value generates a negative value The Compare operations are identical to subtracting for CMP or adding for CMN except that the result is discarded See the instruction descriptions for more information Note Most instructions update the status flags only if th...

Page 67: ... is greater than R1 and R2 is greater than R3 Example 3 2 Compare and update value CMP R0 R1 Compare R0 and R1 setting flags ITT GT Skip next two instructions unless GT condition holds CMPGT R2 R3 If greater than compare R2 and R3 setting flags MOVGT R4 R5 If still greater than do R4 R5 VS V 1 Overflow VC V 0 No overflow HI C 1 and Z 0 Higher unsigned LS C 0 or Z 1 Lower or same unsigned GE N V Gr...

Page 68: ... the assembler cannot generate an instruction encoding of the requested width it generates an error Note In some cases it might be necessary to specify the W suffix for example if the operand is the label of an instruction or literal data as in the case of branch instructions This is because the assembler might not automatically generate the right size encoding To use an instruction width suffix p...

Page 69: ... register offset on page 3 27 LDR type T Load Register with unprivileged access LDR and STR unprivileged on page 3 29 LDR Load Register using PC relative address LDR PC relative on page 3 30 LDREX type Load Register Exclusive LDREX and STREX on page 3 36 POP Pop registers from stack PUSH and POP on page 3 34 PUSH Push registers onto stack PUSH and POP on page 3 34 STM mode Store Multiple registers...

Page 70: ...the means by which position independent code can be generated because the address is PC relative If you use ADR to generate a target address for a BX or BLX instruction you must ensure that bit 0 of the address you generate is set to 1 for correct execution Values of label must be within the range of 4095 to 4095 from the address in the PC Note You might have to use the W suffix to get the maximum...

Page 71: ...pD cond Rt Rt2 Rn offset post indexed two words where op Is one of LDR Load Register STR Store Register type Is one of B unsigned byte zero extend to 32 bits on loads SB signed byte sign extend to 32 bits LDR only H unsigned halfword zero extend to 32 bits on loads SH signed halfword sign extend to 32 bits LDR only omit for word cond Is an optional condition code see Conditional execution on page ...

Page 72: ...he address for the memory access and written back into the register Rn The assembly language syntax for this mode is Rn offset Post indexed addressing The address obtained from the register Rn is used as the address for the memory access The offset value is added to or subtracted from the address and written back into the register Rn The assembly language syntax for this mode is Rn offset The valu...

Page 73: ... Rt can be SP for word stores only Rt must not be PC Rn must not be PC Rn must be different from Rt and Rt2 in the pre indexed or post indexed forms Condition flags These instructions do not change the flags Examples LDR R8 R10 Loads R8 from the address in R10 LDRNE R2 R5 960 Loads conditionally R2 from a word 960 bytes above the address in R5 and increments R5 by 960 STR R2 R9 const struc const s...

Page 74: ...d as the offset LSL n Is an optional shift with n in the range 0 to 3 Operation LDR instructions load a register with a value from memory STR instructions store a register value into memory The memory address to load from or store to is at an offset from the register Rn The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL The value to load or store can be a ...

Page 75: ...instructions do not change the flags Examples STR R0 R5 R1 Store value of R0 into an address equal to sum of R5 and R1 LDRSB R0 R5 R1 LSL 1 Read byte value from an address equal to sum of R5 and two times R1 sign extended it to a word value and put it in R0 STR R0 R1 R2 LSL 2 Stores R0 to an address equal to sum of R1 and four times R2 ...

Page 76: ...fset Specifies an offset from Rn and can be 0 to 255 If offset is omitted the address is the value in Rn Operation These load and store instructions perform the same function as the memory access instructions with immediate offset see LDR and STR immediate offset on page 3 24 The difference is that these instructions have only unprivileged access even when used in privileged software When used in ...

Page 77: ...ons on page 3 17 Operation LDR loads a register with a value from a PC relative memory address The memory address is specified by a label or by an offset from the PC The value to load or store can be a byte halfword or word For load instructions bytes and halfwords can either be signed or unsigned See Address alignment on page 3 17 label must be within a limited range of the current instruction Ta...

Page 78: ... and a branch occurs to this halfword aligned address if the instruction is conditional it must be the last instruction in the IT block Condition flags These instructions do not change the flags Examples LDR R0 LookUpTable Load R0 with a word of data from an address labelled as LookUpTable LDRSB R7 localdata Load a byte value from an address labelled as localdata sign extend it to a word value and...

Page 79: ...TM and STMEA are synonyms for STMIA STMEA refers to its use for pushing data onto Empty Ascending stacks STMFD is s synonym for STMDB and refers to its use for pushing data onto Full Descending stacks Operation LDM instructions load the registers in reglist with word values from memory addresses based on Rn STM instructions store the word values in the registers in reglist to memory addresses base...

Page 80: ...in PC if it contains LR reglist must not contain Rn if you specify the writeback suffix When PC is in reglist in an LDM instruction bit 0 of the value loaded to the PC must be 1 for correct execution and a branch occurs to this halfword aligned address if the instruction is conditional it must be the last instruction in the IT block Condition flags These instructions do not change the flags Exampl...

Page 81: ...he highest numbered register using the highest memory address PUSH uses the value in the SP register minus four as the highest memory address POP uses the value in the SP register as the lowest memory address implementing a full descending stack On completion PUSH updates the SP register to point to the location of the lowest store value POP updates the SP register to point to the location above t...

Page 82: ...right 2010 ARM All rights reserved 3 35 ID121610 Non Confidential Examples PUSH R0 R4 R7 Push R0 R4 R5 R6 R7 onto the stack PUSH R2 LR Push R2 and the link register onto the stack POP R0 R6 PC Pop r0 r6 and PC from the stack then branch to the new PC ...

Page 83: ... be the same as the address in the most recently executed Load exclusive instruction The value stored by the Store Exclusive instruction must also have the same data size as the value loaded by the preceding Load exclusive instruction This means software must always use a Load exclusive instruction and a matching Store Exclusive instruction to perform a synchronization operation see Synchronizatio...

Page 84: ...rom both Rt and Rn the value of offset must be a multiple of four in the range 0 1020 Condition flags These instructions do not change the flags Examples MOV R1 0x1 Initialize the lock taken value try LDREX R0 LockAddr Load the lock value CMP R0 0 Is the lock free ITT EQ IT instruction for STREXEQ and CMPEQ STREXEQ R0 R1 LockAddr Try and claim the lock CMPEQ R0 0 Did this succeed BNE try No try ag...

Page 85: ... the next STREX STREXB or STREXH instruction write 1 to its destination register and fail to perform the store It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation See Synchronization primitives on page 2 18 for more information Cond...

Page 86: ... and RRX on page 3 46 MOV Move MOV and MVN on page 3 50 MOVT Move Top MOVT on page 3 52 MOVW Move 16 bit constant MOV and MVN on page 3 50 MVN Move NOT MOV and MVN on page 3 50 ORN Logical OR NOT AND ORR EOR BIC and ORN on page 3 44 ORR Logical OR AND ORR EOR BIC and ORN on page 3 44 RBIT Reverse Bits REV REV16 REVSH and RBIT on page 3 53 REV Reverse byte order in a word REV REV16 REVSH and RBIT o...

Page 87: ... 3 62 UADD16 Unsigned Add 16 UADD16 and UADD8 on page 3 63 UADD8 Unsigned Add 8 UADD16 and UADD8 on page 3 63 UASX Unsigned Add and Subtract with Exchange UASX and USAX on page 3 64 USAX Unsigned Subtract and Add with Exchange UASX and USAX on page 3 64 UHADD16 Unsigned Halving Add 16 UHADD16 and UHADD8 on page 3 66 UHADD8 Unsigned Halving Add 8 UHADD16 and UHADD8 on page 3 66 UHASX Unsigned Halvi...

Page 88: ...first operand Operand2 Is a flexible second operand See Flexible second operand on page 3 12 for details of the options imm12 Is any value in the range 0 4095 Operation The ADD instruction adds the value of Operand2 or imm12 to the value in Rn The ADC instruction adds the values in Rn and Operand2 together with the carry flag The SUB instruction subtracts the value of Operand2 or imm12 from the va...

Page 89: ...1 0 of the PC are rounded to 0b00 before performing the calculation making the base address for the calculation word aligned If you want to generate the address of an instruction you have to adjust the constant based on the value of the PC ARM recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC because your assembler automatically calculates the correct consta...

Page 90: ...ith carry Multiword values do not have to use consecutive registers Example 3 5 shows instructions that subtract a 96 bit integer contained in R9 R1 and R11 from another contained in R6 R2 and R8 The example stores the result in R6 R9 and R2 Example 3 5 96 bit subtraction SUBS R6 R6 R9 subtract the least significant words SBCS R9 R2 R1 subtract the middle words with carry SBC R2 R8 R11 subtract th...

Page 91: ...Rn Specifies the register holding the first operand Operand2 Is a flexible second operand See Flexible second operand on page 3 12 for details of the options Operation The AND EOR and ORR instructions perform bitwise AND Exclusive OR and OR operations on the values in Rn and Operand2 The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in t...

Page 92: ... Set ARM DUI 0553A Copyright 2010 ARM All rights reserved 3 45 ID121610 Non Confidential Examples AND R9 R2 0xFF00 ORREQ R2 R0 R5 ANDS R9 R8 0x19 EORS R7 R11 0x18181818 BIC R0 R1 0xab ORN R7 R11 R14 ROR 4 ORNS R7 R11 R14 ASR 32 ...

Page 93: ...suffix If S is specified the condition code flags are updated on the result of the operation see Conditional execution on page 3 18 Rd Specifies the destination register Rm Specifies the register holding the value to be shifted Rs Specifies the register holding the shift length to apply to the value in Rm Only the least significant byte is used and can be in the range 0 to 255 n Specifies the shif...

Page 94: ... details on what result is generated by the different instructions see Shift Operations on page 3 13 Restrictions Do not use SP and do not use PC Condition flags If S is specified these instructions update the N and Z flags according to the result the C flag is updated to the last bit shifted out except when the shift length is 0 see Shift Operations on page 3 13 Examples ASR R7 R8 9 Arithmetic sh...

Page 95: ...tional execution on page 3 18 Rd Specifies the destination register Rm Specifies the operand register Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd The result value is 32 if no bits are set and zero if bit 31 is set Restrictions Do not use SP and do not use PC Condition flags This instruction does not change the flags Examples CLZ ...

Page 96: ...ion These instructions compare the value in a register with Operand2 They update the condition flags on the result but do not write the result to a register The CMP instruction subtracts the value of Operand2 from the value in Rn This is the same as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Operand2 to the value in Rn This is the same as an ADDS i...

Page 97: ...he corresponding shift instruction ASR S cond Rd Rm n is the preferred syntax for MOV S cond Rd Rm ASR n LSL S cond Rd Rm n is the preferred syntax for MOV S cond Rd Rm LSL n if n 0 LSR S cond Rd Rm n is the preferred syntax for MOV S cond Rd Rm LSR n ROR S cond Rd Rm n is the preferred syntax for MOV S cond Rd Rm ROR n RRX S cond Rd Rm is the preferred syntax for MOV S cond Rd Rm RRX Also the MOV...

Page 98: ...ction ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set Condition flags If S is specified these instructions update the N and Z flags according to the result can update the C flag during the calculation of Operand2 see Flexible second operand on page 3 12 do not affect the V flag Example MOVS R11 0x000B Write value of 0x000B to...

Page 99: ...register imm16 Is a 16 bit immediate constant Operation MOVT writes a 16 bit immediate value imm16 to the top halfword Rd 31 16 of its destination register The write does not affect Rd 15 0 The MOV MOVT instruction pair enables you to generate any 32 bit constant Restrictions Rd must not be SP and must not be PC Condition flags This instruction does not change the flags Examples MOVT R3 0xF123 Wri...

Page 100: ...ns to change endianness of data REV Converts either 32 bit big endian data into little endian data 32 bit little endian data into big endian data REV16 Converts either 16 bit big endian data into little endian data 16 bit little endian data into big endian data REVSH Converts either 16 bit signed big endian data into 32 bit signed little endian data 16 bit signed little endian data into 32 bit sig...

Page 101: ... to perform a halfword or byte add in parallel The SADD16 instruction 1 Adds each halfword from the first operand to the corresponding halfword of the second operand 2 Writes the result in the corresponding halfwords of the destination register The SADD8 instruction 1 Adds each byte of the first operand to the corresponding byte of the second operand 2 Writes the result in the corresponding bytes ...

Page 102: ...ster The SHADD16 instruction 1 Adds each halfword from the first operand to the corresponding halfword of the second operand 2 Shuffles the result by one bit to the right halving the data 3 Writes the halfword results in the destination register The SHADDB8 instruction 1 Adds each byte of the first operand to the corresponding byte of the second operand 2 Shuffles the result by one bit to the righ...

Page 103: ...by one bit to the right causing a divide by two or halving 3 Subtracts the top halfword of the second operand from the bottom highword of the first operand 4 Writes the halfword result of the division in the bottom halfword of the destination register shifted by one bit to the right causing a divide by two or halving The SHSAX instruction 1 Subtracts the bottom halfword of the second operand from ...

Page 104: ...ord of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4 and writes halved result to bottom halfword of R7 SHSAX R0 R3 R5 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0 ...

Page 105: ... The SHSUB16 instruction 1 Subtracts each halfword of the second operand from the corresponding halfwords of the first operand 2 Shuffles the result by one bit to the right halving the data 3 Writes the halved halfword results in the destination register The SHSUBB8 instruction 1 Subtracts each byte of the second operand from the corresponding byte of the first operand 2 Shuffles the result by one...

Page 106: ... SSUB16 instruction 1 Subtracts each halfword from the second operand from the corresponding halfword of the first operand 2 Writes the difference result of two signed halfwords in the corresponding halfword of the destination register The SSUB8 instruction 1 Subtracts each byte of the second operand from the corresponding byte of the first operand 2 Writes the difference result of four signed byt...

Page 107: ...rand 2 Writes the signed result of the addition to the top halfword of the destination register 3 Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand 4 Writes the signed result of the subtraction to the bottom halfword of the destination register The SSAX instruction 1 Subtracts the signed bottom halfword of the second operand from the top s...

Page 108: ...fword of R4 to bottom halfword of R5 and writes to top halfword of R0 Subtracts bottom halfword of R5 from top halfword of R4 and writes to bottom halfword of R0 SSAX R7 R3 R2 Subtracts top halfword of R2 from bottom halfword of R3 and writes to bottom halfword of R7 Adds top halfword of R3 with bottom halfword of R2 and writes to top halfword of R7 ...

Page 109: ...t of Rn is 0 or 1 use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0 The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2 This is the same as the EORS instruction except that it discards the result Use the TEQ instruction to test if two values are equal without affecting the V or C flags...

Page 110: ...instructions to add 16 and 8 bit unsigned data The UADD16 instruction 1 Adds each halfword from the first operand to the corresponding halfword of the second operand 2 Writes the unsigned result in the corresponding halfwords of the destination register The UADD16 instruction 1 Adds each byte of the first operand to the corresponding byte of the second operand 2 Writes the unsigned result in the c...

Page 111: ...and 2 Writes the unsigned result from the subtraction to the bottom halfword of the destination register 3 Adds the top halfword of the first operand with the bottom halfword of the second operand 4 Writes the unsigned result of the addition to the top halfword of the destination register The USAX instruction 1 Adds the bottom halfword of the first operand with the top halfword of the second opera...

Page 112: ...lfword of R4 to bottom halfword of R5 and writes to top halfword of R0 Subtracts bottom halfword of R5 from top halfword of R0 and writes to bottom halfword of R0 USAX R7 R3 R2 Subtracts top halfword of R2 from bottom halfword of R3 and writes to bottom halfword of R7 Adds top halfword of R3 to bottom halfword of R2 and writes to top halfword of R7 ...

Page 113: ...ction 1 Adds each halfword from the first operand to the corresponding halfword of the second operand 2 Shuffles the halfword result by one bit to the right halving the data 3 Writes the unsigned results to the corresponding halfword in the destination register The UHADD8 instruction 1 Adds each byte of the first operand to the corresponding byte of the second operand 2 Shuffles the byte result by...

Page 114: ...o the top halfword of the destination register 4 Subtracts the top halfword of the second operand from the bottom highword of the first operand 5 Shifts the result by one bit to the right causing a divide by two or halving 6 Writes the halfword result of the division in the bottom halfword of the destination register The UHSAX instruction 1 Subtracts the bottom halfword of the second operand from ...

Page 115: ...word of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R7 and writes halved result to bottom halfword of R7 UHSAX R0 R3 R5 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0 ...

Page 116: ...e result before writing the result to the destination register The UHSUB16 instruction 1 Subtracts each halfword of the second operand from the corresponding halfword of the first operand 2 Shuffles each halfword result to the right by one bit halving the data 3 Writes each unsigned halfword result to the corresponding halfwords in the destination register The UHSUB8 instruction 1 Subtracts each b...

Page 117: ...bler syntax fields Rd Specifies the destination register Rn Specifies the first operand register Rm Specifies the second operand register Operation The SEL instruction 1 Reads the value of each bit of APSR GE 2 Depending on the value of APSR GE assigns the destination register the value of either the first or second operand register Restrictions None Condition flags These instructions do not chang...

Page 118: ...d register Operation The USAD8 instruction 1 Subtracts each byte of the second operand register from the corresponding byte of the first operand register 2 Adds the absolute values of the differences together 3 Writes the result to the destination register Restrictions Do not use SP and do not use PC Condition flags These instructions do not change the flags Examples USAD8 R1 R4 R0 Subtracts each ...

Page 119: ... value Operation The USADA8 instruction 1 Subtracts each byte of the second operand register from the corresponding byte of the first operand register 2 Adds the unsigned absolute differences together 3 Adds the accumulation value to the sum of the absolute differences 4 Writes the result to the destination register Restrictions Do not use SP and do not use PC Condition flags These instructions do...

Page 120: ...er The USUB16 instruction 1 Subtracts each halfword from the second operand register from the corresponding halfword of the first operand register 2 Writes the unsigned result in the corresponding halfwords of the destination register The USUB8 instruction 1 Subtracts each byte of the second operand register from the corresponding byte of the first operand register 2 Writes the unsigned byte resul...

Page 121: ...y Accumulate word by halfword SMLA and SMLAW on page 3 79 SMLSD Signed Multiply Subtract Dual SMLSD and SMLSLD on page 3 84 SMLSLD Signed Multiply Subtract Long Dual SMLSD and SMLSLD on page 3 84 SMMLA Signed Most Significant Word Multiply Accumulate SMMLA and SMMLS on page 3 86 SMMLS SMMLSR Signed Most Significant Word Multiply Subtract SMMLA and SMMLS on page 3 86 SMUAD SMUADX Signed Dual Multip...

Page 122: ... Conditional execution on page 3 18 Rd Specifies the destination register If Rd is omitted the destination register is Rn Rn Rm Are registers holding the values to be multiplied Ra Is a register holding the value to be added or subtracted from Operation The MUL instruction multiplies the values from Rn and Rm and places the least significant 32 bits of the result in Rd The MLA instruction multipli...

Page 123: ...ange R0 to R7 Rd must be the same as Rm you must not use the cond suffix Condition flags If S is specified the MUL instruction updates the N and Z flags according to the result does not affect the C and V flags Examples MUL R10 R2 R5 Multiply R10 R2 x R5 MLA R10 R2 R1 R5 Multiply with accumulate R10 R2 x R1 R5 MULS R0 R2 R2 Multiply with flag update R0 R2 x R2 MULLT R2 R3 R2 Conditionally multiply...

Page 124: ...UMULL instruction Multiplies the two unsigned integers in the first and second operands Writes the least significant 32 bits of the result in RdLo Writes the most significant 32 bits of the result in RdHi The UMAAL instruction Multiplies the two unsigned 32 bit integers in the first and second operands Adds the unsigned 32 bit integer in RdHi to the 64 bit result of the multiplication Adds the uns...

Page 125: ...on Confidential Examples UMULL R0 R4 R5 R6 Multiplies R5 and R6 writes the top 32 bits to R4 and the bottom 32 bits to R0 UMAAL R3 R6 R2 R7 Multiplies R2 and R7 adds R6 adds R3 writes the top 32 bits to R6 and the bottom 32 bits to R3 UMLAL R2 R1 R3 R5 Multiplies R5 and R3 adds R1 R2 writes to R1 R2 ...

Page 126: ...ional condition code see Conditional execution on page 3 18 Rd Specifies the destination register If Rd is omitted the destination register is Rn Rn Rm Are registers holding the values to be multiplied Ra Is a register holding the value to be added or subtracted from Operation The SMALBB SMLABT SMLATB SMLATT instructions Multiplies the specified signed halfword top or bottom values from Rn and Rm ...

Page 127: ...top halfword of R6 with bottom halfword of R4 adds R1 and writes to R5 SMLATT R5 R6 R4 R1 Multiplies top halfwords of R6 and R4 adds R1 and writes the sum to R5 SMLABT R5 R6 R4 R1 Multiplies bottom halfword of R6 with top halfword of R4 adds R1 and writes to R5 SMLABT R4 R3 R2 Multiplies bottom halfword of R4 with top halfword of R3 adds R2 and writes to R4 SMLAWB R10 R2 R5 R3 Multiplies R2 with b...

Page 128: ...d SMLADX instructions regard the two operands as four halfword 16 bit values The SMLAD and SMLADX instructions If X is not present multiply the top signed halfword value in Rn with the top signed halfword of Rm and the bottom signed halfword values in Rn with the bottom signed halfword of Rm Or if X is present multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and t...

Page 129: ...rsed If the X is omitted the multiplications are bottom bottom and top top If X is present the multiplications are bottom top and top bottom cond Is an optional condition code see Conditional execution on page 3 18 RdHi RdLo Are the destination registers RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64 bit integer For SMLAL SMLALBB SMLALBT SMLALTB SMLALTT SMLALD and SMLALDX they a...

Page 130: ...o and RdHi to create the resulting 64 bit product Write the 64 bit product in RdLo and RdHi Restrictions In these instructions do not use SP and do not use PC RdHi and RdLo must be different registers Condition flags These instructions do not affect the condition code flags Examples SMLAL R4 R5 R3 R8 Multiplies R3 and R8 adds R5 R4 and writes to R5 R4 SMLALBT R2 R1 R6 R7 Multiplies bottom halfword...

Page 131: ...tion The SMLSD instruction interprets the values from the first and second operands as four signed halfwords This instruction Optionally rotates the halfwords of the second operand Performs two signed 16 16 bit halfword multiplications Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication Adds the signed accumulate value to the result of the...

Page 132: ... top halfword of R4 with top halfword of R5 subtracts second from first adds R6 writes to R0 SMLSDX R1 R3 R2 R0 Multiplies bottom halfword of R3 with top halfword of R2 multiplies top halfword of R3 with bottom halfword of R2 subtracts second from first adds R0 writes to R1 SMLSLD R3 R6 R2 R7 Multiplies bottom halfword of R6 with bottom halfword of R2 multiplies top halfword of R6 with top halfwor...

Page 133: ...he first and second multiply operands Ra Specifies the register holding the accumulate value Operation The SMMLA instruction interprets the values from Rn and Rm as signed 32 bit words The SMMLA instruction Multiplies the values in Rn and Rm Optionally rounds the result by adding 0x80000000 Extracts the most significant 32 bits of the result Adds the value of Ra to the signed extracted value Write...

Page 134: ...4 and R5 extracts top 32 bits adds R6 truncates and writes to R0 SMMLAR R6 R2 R1 R4 Multiplies R2 and R1 extracts top 32 bits adds R4 rounds and writes to R6 SMMLSR R3 R6 R2 R7 Multiplies R6 and R2 extracts top 32 bits subtracts R7 rounds and writes to R3 SMMLS R4 R5 R3 R8 Multiplies R5 and R3 extracts top 32 bits subtracts R8 truncates and writes to R4 ...

Page 135: ...on on page 3 18 Rd Specifies the destination register Rn Rm Are registers holding the first and second operands Operation The SMMUL instruction interprets the values from Rn and Rm as two s complement 32 bit signed integers The SMMUL instruction Multiplies the values from Rn and Rm Optionally rounds the result otherwise truncates the result Writes the most significant signed 32 bits of the result ...

Page 136: ...two signed halfwords in each operand This instruction Optionally rotates the halfwords of the second operand Performs two signed 16 16 bit multiplications Adds the two multiplication results together Writes the result of the addition to the destination register The SMUSD instruction interprets the values from the first and second operands as two s complement signed integers This instruction Option...

Page 137: ...ultiplication of top halfword of R7 with bottom halfword of R4 writes to R3 SMUSD R3 R6 R2 Multiplies bottom halfword of R4 with bottom halfword of R6 subtracts multiplication of top halfword of R6 with top halfword of R3 writes to R3 SMUSDX R4 R5 R3 Multiplies bottom halfword of R5 with top halfword of R3 subtracts multiplication of top halfword of R5 with bottom halfword of R3 writes to R4 ...

Page 138: ...e bottom halfword bits 15 0 of Rm is used If Y is T then the top halfword bits 31 16 of Rm is used cond Is an optional condition code see Conditional execution on page 3 18 Rd Specifies the destination register Rn Rm Are registers holding the first and second operands Operation The SMULBB SMULTB SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed 16 bit integers Thes...

Page 139: ...ith the bottom halfword of R5 multiplies results and writes to R0 SMULTT R0 R4 R5 Multiplies the top halfword of R4 with the top halfword of R5 multiplies results and writes to R0 SMULTB R0 R4 R5 Multiplies the top halfword of R4 with the bottom halfword of R5 multiplies results and and writes to R0 SMULWT R4 R5 R3 Multiplies R5 with the top halfword of R3 extracts top 32 bits and writes to R4 SMU...

Page 140: ...d the most significant 32 bits of the result in RdHi The UMLAL instruction interprets the values from Rn and Rm as unsigned integers It multiplies these integers adds the 64 bit result to the 64 bit unsigned integer contained in RdHi and RdLo and writes the result back to RdHi and RdLo The SMULL instruction interprets the values from Rn and Rm as two s complement signed integers It multiplies thes...

Page 141: ...er is Rn Rn Specifies the register holding the value to be divided Rm Is a register holding the divisor Operation SDIV performs a signed integer division of the value in Rn by the value in Rm UDIV performs an unsigned integer division of the value in Rn by the value in Rm For both instructions if the value in Rn is not divisible by the value in Rm the result is rounded towards zero Restrictions Do...

Page 142: ...f the Q flag use the MRS instruction see MRS on page 3 163 Table 3 10 Saturating instructions Mnemonic Brief description See SSAT Signed Saturate SSAT and USAT on page 3 96 SSAT16 Signed Saturate Halfword SSAT16 and USAT16 on page 3 97 USAT Unsigned Saturate SSAT and USAT on page 3 96 USAT16 Unsigned Saturate Halfword SSAT16 and USAT16 on page 3 97 QADD Saturating Add QADD and QSUB on page 3 98 QS...

Page 143: ...aturate shift s Is an optional shift applied to Rm before saturating It must be one of the following ASR s where s is in the range 1 to 31 LSL s where s is in the range 0 to 31 Operation These instructions saturate to a signed or unsigned n bit value The SSAT instruction applies the specified shift then saturates to the signed range 2n 1 x 2n 1 1 The USAT instruction applies the specified shift th...

Page 144: ...truction 1 Saturates two signed 16 bit halfword values of the register with the value to saturate from selected by the bit position in n 2 Writes the results as two signed 16 bit halfwords to the destination register The USAT16 instruction 1 Saturates two unsigned 16 bit halfword values of the register with the value to saturate from selected by the bit position in n 2 Writes the results as two un...

Page 145: ...he first and second operands and then writes a signed saturated value in the destination register The QADD and QSUB instructions apply the specified add or subtract and then saturate the result to the signed range 2n 1 x 2n 1 1 where x is given by the number of bits applied in the instruction 32 16 or 8 If the returned result is different from the value to be saturated it is called saturation If s...

Page 146: ...ites to corresponding halfword of R7 QADD8 R3 R1 R6 Adds bytes of R1 to the corresponding bytes of R6 saturates to 8 bits and writes to corresponding byte of R3 QSUB16 R4 R2 R3 Subtracts halfwords of R3 from corresponding halfword of R2 saturates to 16 bits writes to corresponding halfword of R4 QSUB8 R4 R2 R5 Subtracts bytes of R5 from the corresponding byte in R2 saturates to 8 bits writes to co...

Page 147: ... result of the subtraction and writes a 16 bit signed integer in the range 215 x 215 1 where x equals 16 to the bottom halfword of the destination register 4 Saturates the results of the sum and writes a 16 bit signed integer in the range 215 x 215 1 where x equals 16 to the top halfword of the destination register The QSAX instruction 1 Subtracts the bottom halfword of the second operand from the...

Page 148: ...2 saturates to 16 bits writes to top halfword of R7 Subtracts top highword of R2 from bottom halfword of R4 saturates to 16 bits and writes to bottom halfword of R7 QSAX R0 R3 R5 Subtracts bottom halfword of R5 from top halfword of R3 saturates to 16 bits writes to top halfword of R0 Adds bottom halfword of R3 to top halfword of R5 saturates to 16 bits writes to bottom halfword of R0 ...

Page 149: ...igned saturated value in the first operand Writes the result to the destination register The QDSUB instruction Doubles the second operand value Subtracts the doubled value from the signed saturated value in the first operand Writes the result to the destination register Both the doubling and the addition or subtraction have their results saturated to the 32 bit signed integer range 231 x 231 1 If ...

Page 150: ...he results of the sum and writes a 16 bit unsigned integer in the range 0 x 216 1 where x equals 16 to the top halfword of the destination register 4 Saturates the result of the subtraction and writes a 16 bit unsigned integer in the range 0 x 216 1 where x equals 16 to the bottom halfword of the destination register The UQSAX instruction 1 Subtracts the bottom halfword of the second operand from ...

Page 151: ...f R2 saturates to 16 bits writes to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4 saturates to 16 bits writes to bottom halfword of R7 UQSAX R0 R3 R5 Subtracts bottom halfword of R5 from top halfword of R3 saturates to 16 bits writes to top halfword of R0 Adds bottom halfword of R4 to top halfword of R5 saturates to 16 bits writes to bottom halfword of R0 ...

Page 152: ...egister The UQADD16 instruction Adds the respective top and bottom halfwords of the first and second operands Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 x 216 1 where x is 16 The UQADD8 instruction Adds each respective byte of the first and second operands Saturates the result of the addition for each byte in the destination register...

Page 153: ...g halfword in R2 saturates to 16 bits writes to corresponding halfword of R7 UQADD8 R4 R2 R5 Adds bytes of R2 to corresponding byte of R5 saturates to 8 bits writes to corresponding bytes of R4 UQSUB16 R6 R3 R0 Subtracts halfwords in R0 from corresponding halfword in R3 saturates to 16 bits writes to corresponding halfword in R6 UQSUB8 R1 R5 R6 Subtracts bytes in R6 from corresponding byte of R5 s...

Page 154: ... to 16 and add SXTA and UXTA on page 3 112 SXTAH Extend 16 bits to 32 and add SXTA and UXTA on page 3 112 SXTB Sign extend a byte SXT and UXT on page 3 117 SXTB16 Dual extend 8 bits to 16 and add SXT and UXT on page 3 117 SXTH Sign extend a halfword SXT and UXT on page 3 117 UXTAB Extend 8 bits to 32 and add SXTA and UXTA on page 3 112 UXTAB16 Dual extend 8 bits to 16 and add SXTA and UXTA on page...

Page 155: ...on the instruction For PKHBT LSL A left shift with a shift length from 1 to 31 0 means no shift For PKHTB ASR An arithmetic shift right with a shift length from 1 to 32 a shift of 32 bits is encoded as 0b00000 Operation The PKHBT instruction 1 Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register 2 If shifted the shifted value of the second...

Page 156: ...1610 Non Confidential Examples PKHBT R3 R4 R5 LSL 0 Writes bottom halfword of R4 to bottom halfword of R3 writes top halfword of R5 unshifted to top halfword of R3 PKHTB R4 R0 R2 ASR 1 Writes R2 shifted right by 1 bit to bottom halfword of R4 and writes top halfword of R0 to top halfword of R4 ...

Page 157: ... holding the value to extend ROR n Is one of ROR 8 Value from Rm is rotated right 8 bits ROR 16 Value from Rm is rotated right 16 bits ROR 24 Value from Rm is rotated right 24 bits If ROR n is omitted no rotation is performed Operation These instructions do the following 1 Rotate the value from Rm right by 0 8 16 or 24 bits 2 Extract bits from the resulting value SXTB extracts bits 7 0 and sign ex...

Page 158: ... All rights reserved 3 111 ID121610 Non Confidential Examples SXTH R4 R6 ROR 16 Rotates R6 right by 16 bits obtains bottom halfword of of result sign extends to 32 bits and writes to R4 UXTB R3 R10 Extracts lowest byte of value in R10 zero extends and writes to R3 ...

Page 159: ...value to rotate and extend ROR n Is one of ROR 8 Value from Rm is rotated right 8 bits ROR 16 Value from Rm is rotated right 16 bits ROR 24 Value from Rm is rotated right 24 bits If ROR n is omitted no rotation is performed Operation These instructions do the following 1 Rotate the value from Rm right by 0 8 16 or 24 bits 2 Extract bits from the resulting value SXTAB extracts bits 7 0 from Rm and ...

Page 160: ...n Confidential Condition flags These instructions do not affect the flags Examples SXTAH R4 R8 R6 ROR 16 Rotates R6 right by 16 bits obtains bottom halfword sign extends to 32 bits adds R8 and writes to R4 UXTAB R3 R4 R10 Extracts bottom byte of R10 and zero extends to 32 bits adds R4 and writes to R3 ...

Page 161: ...cking instructions Mnemonic Brief description See BFC Bit Field Clear BFC and BFI on page 3 115 BFI Bit Field Insert BFC and BFI on page 3 115 SBFX Signed Bit Field Extract SBFX and UBFX on page 3 116 SXTB Sign extend a byte SXT and UXT on page 3 117 SXTH Sign extend a halfword SXT and UXT on page 3 117 UBFX Unsigned Bit Field Extract SBFX and UBFX on page 3 116 UXTB Zero extend a byte SXT and UXT...

Page 162: ... to 31 width Specifies the width of the bitfield and must be in the range 1 to 32 lsb Operation BFC clears a bitfield in a register It clears width bits in Rd starting at the low bit position lsb Other bits in Rd are unchanged BFI copies a bitfield into one register from another register It replaces width bits in Rd starting at the low bit position lsb with width bits from Rn starting at bit 0 Oth...

Page 163: ...he range 0 to 31 width Specifies the width of the bitfield and must be in the range 1 to 32 lsb Operation SBFX extracts a bitfield from one register sign extends it to 32 bits and writes the result to the destination register UBFX extracts a bitfield from one register zero extends it to 32 bits and writes the result to the destination register Restrictions Do not use SP and do not use PC Condition...

Page 164: ...its ROR 24 Value from Rm is rotated right 24 bits If ROR n is omitted no rotation is performed Operation These instructions do the following 1 Rotate the value from Rm right by 0 8 16 or 24 bits 2 Extract bits from the resulting value SXTB extracts bits 7 0 and sign extends to 32 bits UXTB extracts bits 7 0 and zero extends to 32 bits SXTH extracts bits 15 0 and sign extends to 32 bits UXTH extrac...

Page 165: ... description See B Branch B BL BX and BLX on page 3 119 BL Branch with Link B BL BX and BLX on page 3 119 BLX Branch indirect with Link B BL BX and BLX on page 3 119 BX Branch indirect B BL BX and BLX on page 3 119 CBNZ Compare and Branch if Non Zero CBZ and CBNZ on page 3 121 CBZ Compare and Branch if Zero CBZ and CBNZ on page 3 121 IT If Then IT on page 3 122 TBB Table Branch Byte TBB and TBH on...

Page 166: ...it 0 to 0 Operation All these instructions cause a branch to label or to the address indicated in Rm In addition The BL and BLX instructions write the address of the next instruction to LR the link register R14 The BX and BLX instructions result in a UsageFault exception if bit 0 of Rm is 0 Bcond label is the only conditional instruction that can be either inside or outside an IT block All other b...

Page 167: ... the last instruction of the IT block Note Bcond is the only conditional instruction that is not required to be inside an IT block However it has a longer branch range when it is inside an IT block Condition flags These instructions do not change the flags Examples B loopA Branch to loopA BLE ng Conditionally branch to label ng B W target Branch to target within 16MB range BEQ target Conditionally...

Page 168: ...e flags and to reduce the number of instructions CBZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BEQ label CBNZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BNE label Restrictions The restrictions are Rn must be in the range of R0 to R7 the branch destination must be within 4 to 130 bytes after the instruction these instructi...

Page 169: ...ditional The conditions can be all the same or some of them can be the logical inverse of the others The conditional instructions following the IT instruction form the IT block The instructions in the IT block including any branches must specify the condition in the cond part of their syntax Note Your assembler might be able to generate the required IT instructions for conditional instructions aut...

Page 170: ... as for the other instructions in the block Note Your assembler might place extra restrictions on the use of IT blocks such as prohibiting the use of assembler directives within them Condition flags This instruction does not change the flags Example ITTE NE Next 3 instructions are conditional ANDNE R0 R0 R1 ANDNE does not update condition flags ADDSNE R2 R2 1 ADDSNE updates condition flags MOVEQ R...

Page 171: ... Operation These instructions cause a PC relative forward branch using a table of single byte offsets for TBB or halfword offsets for TBH Rn provides a pointer to the table and Rm supplies an index into the table For TBB the branch offset is twice the unsigned value of the byte returned from the table and for TBH the branch offset is twice the unsigned value of the halfword returned from the table...

Page 172: ...ruction sequence follows BranchTable_Byte DCB 0 Case1 offset calculation DCB Case2 Case1 2 Case2 offset calculation DCB Case3 Case1 2 Case3 offset calculation TBH PC R1 LSL 1 R1 is the index PC is used as base of the branch table BranchTable_H DCI CaseA BranchTable_H 2 CaseA offset calculation DCI CaseB BranchTable_H 2 CaseB offset calculation DCI CaseC BranchTable_H 2 CaseC offset calculation Cas...

Page 173: ... between floating point and integer with rounding VCVT VCVTR between floating point and integer on page 3 131 VCVTB Converts half precision value to single precision VCVTB VCVTT on page 3 133 VCVTT Converts single precision register to half precision VCVTB VCVTT on page 3 133 VDIV Floating point Divide VDIV on page 3 134 VFMA Floating point Fused Multiply Accumulate VFMA VFMS on page 3 135 VFNMA F...

Page 174: ...y floating point VMUL on page 3 148 VNEG Floating point negate VNEG on page 3 149 VNMLA Floating point multiply and add VNMLA VNMLS VNMUL on page 3 150 VNMLS Floating point multiply and subtract VNMLA VNMLS VNMUL on page 3 150 VNMUL Floating point multiply VNMLA VNMLS VNMUL on page 3 150 VPOP Pop extension registers VPOP on page 3 151 VPUSH Push extension registers VPUSH on page 3 152 VSQRT Floati...

Page 175: ... code see Conditional execution on page 3 18 Sd Sm Are the destination floating point value and the operand floating point value Operation This instruction 1 Takes the absolute value of the operand floating point register 2 Places the results in the destination floating point register Restrictions There are no restrictions Condition flags The floating point instruction clears the sign bit Examples...

Page 176: ...ode see Conditional execution on page 3 18 Sd Specifies the destination floating point value Sn Sm Are the operand floating point values Operation This instruction 1 Adds the values in the two floating point operand registers 2 Places the results in the destination floating point register Restrictions There are no restrictions Condition flags This instruction does not change the flags Examples VAD...

Page 177: ...ies the floating point operand to compare Sm Specifies the floating point operand that is compared with Operation This instruction 1 Compares Two floating point registers One floating point register and zero 2 Writes the result to the FPSCR flags Restrictions This instruction can optionally raise an Invalid Operation exception if either operand is any type of NaN It always raises an Invalid Operat...

Page 178: ... 18 Tm Specifies the data type for the operand It must be one of S32 signed 32 bit value U32 unsigned 32 bit value Sd Sm Are the destination register and the operand register Operation These instructions 1 Either Converts a value in a register from floating point value to a 32 bit integer Converts from a 32 bit integer to floating point value 2 Places the result in a second register The floating p...

Page 179: ...32 or U32 fbits must be in the range 1 32 Operation These instructions 1 Either converts a value in a register from floating point to fixed point converts a value in a register from fixed point to floating point 2 Places the result in a second register The floating point values are single precision The fixed point value can be 16 bit or 32 bit Conversions from fixed point values take their operand...

Page 180: ...used cond Is an optional condition code see Conditional execution on page 3 18 Sd Specifies the destination register Sm Specifies the operand register Operation This instruction with the F16 32 suffix 1 Converts the half precision value in the top or bottom half of a single precision register to single precision 2 Writes the result to a single precision register This instruction with the F32 F16 s...

Page 181: ...nd Is an optional condition code see Conditional execution on page 3 18 Sd Specifies the destination register Sn Sm Are the operand registers Operation This instruction 1 Divides one floating point value by another floating point value 2 Writes the result to the floating point destination register Restrictions There are no restrictions Condition flags These instructions do not change the flags ...

Page 182: ...he VFMA instruction 1 Multiplies the floating point values in the operand registers 2 Accumulates the results into the destination register The result of the multiply is not rounded before the accumulation The VFMS instruction 1 Negates the first operand register 2 Multiplies the floating point values of the first and second operand registers 3 Adds the products to the destination register 4 Place...

Page 183: ...gister 2 Multiplies the first floating point operand with second floating point operand 3 Adds the negation of the floating point destination register to the product 4 Places the result into the destination register The result of the multiply is not rounded before the addition The VFNMS instruction 1 Multiplies the first floating point operand with second floating point operand 2 Adds the negation...

Page 184: ...ional if mode IA list Specifies the list of extension registers to be loaded as a list of consecutively numbered doubleword or singleword registers separated by commas and surrounded by brackets Operation This instruction loads Multiple extension registers from consecutive memory locations using an address from an ARM core register as the base address Restrictions The restrictions are If size is p...

Page 185: ... data size specifiers Dd Specifies the destination register for a doubleword load Sd Specifies the destination register for a singleword load Rn Specifies the base register The SP can be used imm Is the or immediate offset used to form the address Permitted address values are multiples of 4 in the range 0 to 1020 label Specifies the label of the literal data item to be loaded Operation This instru...

Page 186: ...pecifies the destination floating point value Sn Sm Are the operand floating point values Operation The floating point Multiply Accumulate instruction 1 Multiplies two floating point values 2 Adds the results to the destination floating point value The floating point Multiply Subtract instruction 1 Multiplies two floating point values 2 Subtracts the products from the destination floating point va...

Page 187: ...mediate Syntax VMOV cond F32 Sd imm where cond Is an optional condition code see Conditional execution on page 3 18 Sd Specifies the branch destination imm Is a floating point constant Operation This instruction copies a constant value to a floating point register Restrictions There are no restrictions Condition flags These instructions do not change the flags ...

Page 188: ...ee Conditional execution on page 3 18 Dd Specifies the destination register for a doubleword operation Dm Specifies the source register for a doubleword operation Sd Specifies the destination register for a singleword operation Sm Specifies the source register for a singleword operation Operation This instruction copies the contents of one floating point register to another Restrictions There are ...

Page 189: ...Conditional execution on page 3 18 Rt Specifies the destination ARM core register Dn Specifies the 64 bit doubleword register x Specifies which half of the doubleword register to use If x is 0 use lower half of doubleword register If x is 1 use upper half of doubleword register Operation This instruction transfers one word from the upper or lower half of a doubleword floating point register to an ...

Page 190: ...Rt VMOV cond Rt Sn where cond Is an optional condition code see Conditional execution on page 3 18 Sn Specifies the single precision floating point register Rt Specifies the ARM core register Operation This instruction transfers The contents of a single precision register to an ARM core register The contents of an ARM core register to a single precision register Restrictions Rt cannot be PC or SP ...

Page 191: ... second single precision register This is the next single precision register after Sm Rt Specifies the ARM core register that Sm is transferred to or from Rt2 Specifies the The ARM core register that Sm1 is transferred to or from Operation This instruction transfers The contents of two consecutively numbered single precision registers to two ARM core registers The contents of two ARM core register...

Page 192: ...l execution on page 3 18 32 Is an optional data size specifier Dd x Specifies the destination where x defines which half of the doubleword is transferred as follows If x is 0 the lower half is extracted If x is 1 the upper half is extracted Rt Specifies the source ARM core register Operation This instruction transfers one word to the upper or lower half of a doubleword floating point register from...

Page 193: ... code see Conditional execution on page 3 18 Rt Specifies the destination ARM core register This register can be R0 R14 APSR_nzcv Transfer floating point flags to the APSR flags Operation This instruction performs one of the following actions Copies the value of the FPSCR to a general purpose register Copies the value of the FPSCR flag bits to the APSR N Z C and V flags Restrictions Rt cannot be P...

Page 194: ...ere cond Is an optional condition code see Conditional execution on page 3 18 Rt Specifies the general purpose register to be transferred to the FPSCR Operation This instruction moves the value of a general purpose register to the FPSCR See Floating point Status Control Register on page 4 50 for more information Restrictions The restrictions are Rt cannot be PC or SP Condition flags This instructi...

Page 195: ...here cond Is an optional condition code see Conditional execution on page 3 18 Sd Specifies the destination floating point value Sn Sm Are the operand floating point values Operation This instruction 1 Multiplies two floating point values 2 Places the results in the destination register Restrictions There are no restrictions Condition flags These instructions do not change the flags ...

Page 196: ...ion code see Conditional execution on page 3 18 Sd Specifies the destination floating point value Sm Specifies the operand floating point value Operation This instruction 1 Negates a floating point value 2 Places the results in a second floating point register The floating point instruction inverts the sign bit Restrictions There are no restrictions Condition flags These instructions do not change...

Page 197: ... VNMLA instruction 1 Multiplies two floating point register values 2 Adds the negation of the floating point value in the destination register to the negation of the product 3 Writes the result back to the destination register The VNMLS instruction 1 Multiplies two floating point register values 2 Adds the negation of the floating point value in the destination register to the product 3 writes the...

Page 198: ...e specifier If present it must be equal to the size in bits 32 or 64 of the registers in list list Is a list of extension registers to be loaded as a list of consecutively numbered doubleword or singleword registers separated by commas and surrounded by brackets Operation This instruction loads multiple consecutive extension registers from the stack Restrictions The list must contain at least one ...

Page 199: ...ecifier If present it must be equal to the size in bits 32 or 64 of the registers in list list Is a list of the extension registers to be stored as a list of consecutively numbered doubleword or singleword registers separated by commas and surrounded by brackets Operation This instruction Stores multiple consecutive extension registers to the stack Restrictions The restrictions are list must conta...

Page 200: ...ptional condition code see Conditional execution on page 3 18 Sd Specifies the destination floating point value Sm Specifies the operand floating point value Operation This instruction Calculates the square root of the value in a floating point register Writes the result to another floating point register Restrictions There are no restrictions Condition flags These instructions do not change the f...

Page 201: ...st be equal to the size in bits 32 or 64 of the registers in list Rn Specifies the base register The SP can be used is the function that causes the instruction to write a modified value back to Rn Required if mode DB list Is a list of the extension registers to be stored as a list of consecutively numbered doubleword or singleword registers separated by commas and surrounded by brackets Operation ...

Page 202: ...er for a singleword store Dd Specifies the source register for a doubleword store Rn Specifies the base register The SP can be used imm Is the or immediate offset used to form the address Values are multiples of 4 in the range 0 1020 imm can be omitted meaning an offset of 0 Operation This instruction Stores a single extension register to memory using an address from an ARM core register with an o...

Page 203: ...l condition code see Conditional execution on page 3 18 Sd Specifies the destination floating point value Sn Sm Are the operand floating point value Operation This instruction 1 Subtracts one floating point value from another floating point value 2 Places the results in the destination floating point register Restrictions There are no restrictions Condition flags These instructions do not change t...

Page 204: ...errupts CPS on page 3 159 CPSIE Change Processor State Enable Interrupts CPS on page 3 159 DMB Data Memory Barrier DMB on page 3 160 DSB Data Synchronization Barrier DSB on page 3 161 ISB Instruction Synchronization Barrier ISB on page 3 162 MRS Move from special register to register MRS on page 3 163 MSR Move from register to special register MSR on page 3 164 NOP No Operation NOP on page 3 165 S...

Page 205: ...ress is reached imm is ignored by the processor If required a debugger can use it to store additional information about the breakpoint The BKPT instruction can be placed inside an IT block but it executes unconditionally unaffected by the condition specified by the IT instruction Condition flags This instruction does not change the flags Examples BKPT 0x3 Breakpoint with immediate value set to 0x3...

Page 206: ... values See Exception mask registers on page 2 7 for more information about these registers Restrictions The restrictions are use CPS only from privileged software it has no effect if used in unprivileged software CPS cannot be conditional and so must not be used inside an IT block Condition flags This instruction does not change the condition flags Examples CPSID i Disable interrupts and configur...

Page 207: ...e 3 18 Operation DMB acts as a data memory barrier It ensures that all explicit memory accesses that appear in program order before the DMB instruction are completed before any explicit memory accesses that appear in program order after the DMB instruction DMB does not affect the ordering or execution of instructions that do not access memory Condition flags This instruction does not change the fl...

Page 208: ...ion code see Conditional execution on page 3 18 Operation DSB acts as a special data synchronization memory barrier Instructions that come after the DSB in program order do not execute until the DSB instruction completes The DSB instruction completes when all explicit memory accesses before it complete Condition flags This instruction does not change the flags Examples DSB Data Synchronisation Bar...

Page 209: ...ptional condition code see Conditional execution on page 3 18 Operation ISB acts as an instruction synchronization barrier It flushes the pipeline of the processor so that all instructions following the ISB are fetched from cache or memory again after the ISB instruction has been completed Condition flags This instruction does not change the flags Examples ISB Instruction Synchronisation Barrier ...

Page 210: ...ruction Operation Use MRS in combination with MSR as part of a read modify write sequence for updating a PSR for example to clear the Q flag In process swap code the programmers model state of the process being swapped out must be saved including relevant PSR contents Similarly the state of the process being swapped in must also be restored These operations use MRS in the state saving instruction ...

Page 211: ...ion The register access operation in MSR depends on the privilege level Unprivileged software can only access the APSR see Table 2 4 on page 2 5 Privileged software can access all special registers In unprivileged software writes to unallocated or execution state bits in the PSR are ignored Note When you write to BASEPRI_MAX the instruction writes to BASEPRI only if either Rn is non zero and the c...

Page 212: ...condition code see Conditional execution on page 3 18 Operation NOP does nothing NOP is not necessarily a time consuming NOP The processor might remove it from the pipeline before it reaches the execution stage Use NOP for padding for example to place the following instruction on a 64 bit boundary Condition flags This instruction does not change the flags Examples NOP No operation ...

Page 213: ...re cond Is an optional condition code see Conditional execution on page 3 18 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system It also sets the local event register to 1 see Power management on page 2 32 Condition flags This instruction does not change the flags Examples SEV Send Event ...

Page 214: ... imm Is an expression evaluating to an integer in the range 0 255 8 bit value Operation The SVC instruction causes the SVC exception imm is ignored by the processor If required it can be retrieved by the exception handler to determine what service is being requested Condition flags This instruction does not change the flags Examples SVC 0x32 Supervisor Call SVCall handler can extract the immediate...

Page 215: ...events occurs an exception unless masked by the exception mask registers or the current priority level an exception enters the Pending state if SEVONPEND in the System Control Register is set a Debug Entry request if Debug is enabled an event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction If the event register is 1 WFE clears it to 0 and returns ...

Page 216: ... Is an optional condition code see Conditional execution on page 3 18 Operation WFI is a hint instruction that suspends execution until one of the following events occurs a non masked interrupt occurs and is taken an interrupt masked by PRIMASK becomes pending a Debug Entry request Condition flags This instruction does not change the flags Examples WFI Wait for interrupt ...

Page 217: ...ter describes the ARM Cortex M4 core peripherals It contains the following sections About the Cortex M4 peripherals on page 4 2 Nested Vectored Interrupt Controller on page 4 3 System control block on page 4 11 System timer SysTick on page 4 33 Optional Memory Protection Unit on page 4 37 Floating Point Unit FPU on page 4 48 ...

Page 218: ...eripheral register regions Address Core peripheral Description 0xE000E008 0xE000E00F SyStem Control Block Table 4 12 on page 4 11 0xE000E010 0xE000E01F System timer Table 4 32 on page 4 33 0xE000E100 0xE000E4EF Nested Vectored Interrupt Controller Table 4 2 on page 4 3 0xE000ED00 0xE000ED3F System Control Block Table 4 12 on page 4 11 0xE000ED90 0xE000ED93 MPU Type Register Reads as zero indicatin...

Page 219: ...th no instruction overhead This provides low latency exception handling The hardware implementation of the NVIC registers is Table 4 2 NVIC register summary Address Name Type Required privilege Reset value Description 0xE000E100 0xE000E11C NVIC_ISER0 NVIC_ISER7 RW Privileged 0x00000000 Interrupt Set enable Registers on page 4 4 0XE000E180 0xE000E19C NVIC_ICER0 NVIC_ICER7 RW Privileged 0x00000000 I...

Page 220: ...EnableIRQ IRQn_Type IRQn a Enables an interrupt or exception void NVIC_DisableIRQ IRQn_Type IRQn a Disables an interrupt or exception void NVIC_SetPendingIRQ IRQn_Type IRQn a Sets the pending status of interrupt or exception to 1 void NVIC_ClearPendingIRQ IRQn_Type IRQn a Clears the pending status of interrupt or exception to 0 uint32_t NVIC_GetPendingIRQ IRQn_Type IRQn a Reads the pending status ...

Page 221: ... are pending See the register summary in Table 4 2 on page 4 3 for the register attributes The bit assignments are Note Writing 1 to the ISPR bit corresponding to an interrupt that is pending has no effect a disabled interrupt sets the state of that interrupt to pending Table 4 5 ICER bit assignments Bits Name Function 31 0 CLRENA Interrupt clear enable bits Write 0 no effect 1 disable interrupt R...

Page 222: ...interrupts are pending See the register summary in Table 4 2 on page 4 3 for the register attributes The bit assignments are Note Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt Table 4 7 ICPR bit assignments Bits Name Function 31 0 CLRPEND Interrupt clear pending bits Write 0 no effect 1 removes pending state an interrupt Read 0 interrupt is not pending 1 ...

Page 223: ...ty fields as shown See Accessing the Cortex M4 NVIC registers using CMSIS on page 4 4 for more information about the access to the interrupt priority array which provides the software view of the interrupt priorities Table 4 8 IABR bit assignments Bits Name Function 31 0 ACTIVE Interrupt active flags 0 interrupt not active 1 interrupt active ACTIVE bits 31 0 Table 4 9 IPR bit assignments Bits Name...

Page 224: ...pts A level sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal Typically this happens because the ISR accesses the peripheral causing it to clear the interrupt request A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock To ensure the NVIC detects the interrupt the peripheral must assert the interrupt signal ...

Page 225: ...nterrupt changes to pending which might cause the processor to immediately re enter the ISR If the interrupt signal is not pulsed while the processor is in the ISR when the processor returns from the ISR the state of the interrupt changes to inactive Software writes to the corresponding interrupt clear pending register bit For a level sensitive interrupt if the interrupt signal is still asserted t...

Page 226: ...IC_SetPriorityGrouping uint32_t priority_grouping Set the priority grouping void NVIC_EnableIRQ IRQn_t IRQn Enable IRQn void NVIC_DisableIRQ IRQn_t IRQn Disable IRQn uint32_t NVIC_GetPendingIRQ IRQn_t IRQn Return true IRQ Number if IRQn is pending void NVIC_SetPendingIRQ IRQn_t IRQn Set IRQn pending void NVIC_ClearPendingIRQ IRQn_t IRQn Clear IRQn pending status uint32_t NVIC_GetActive IRQn_t IRQn...

Page 227: ...ivileged 0xFA050000 Application Interrupt and Reset Control Register on page 4 16 0xE000ED10 SCR RW Privileged 0x00000000 System Control Register on page 4 19 0xE000ED14 CCR RW Privileged 0x00000200 Configuration and Control Register on page 4 19 0xE000ED18 SHPR1 RW Privileged 0x00000000 System Handler Priority Register 1 on page 4 21 0xE000ED1C SHPR2 RW Privileged 0x00000000 System Handler Priori...

Page 228: ...ved 9 DISOOFPa Disables floating point instructions completing out of order with respect to integer instructions 8 DISFPCAa Disables automatic update of CONTROL FPCA 7 3 Reserved 2 DISFOLD When set to 1 disables IT folding see About IT folding for more information 1 DISDEFWBUF When set to 1 disables write buffer use during default memory map accesses This causes all BusFaults to be precise BusFaul...

Page 229: ...PendSV and SysTick exceptions indicates the exception number of the exception being processed whether there are preempted active exceptions the exception number of the highest priority pending exception whether any interrupts are pending Table 4 14 CPUID register bit assignments Bits Name Function 31 24 Implementer Implementer code 0x41 ARM 23 20 Variant Variant number the r value in the rnpn prod...

Page 230: ...t priority exception normally the processor enter the NMI exception handler as soon as it registers a write of 1 to this bit and entering the handler clears this bit to 0 A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler 30 29 Reserved 28 PENDSVSET RW PendSV set pending bit Write 0 no effect 1 changes PendSV...

Page 231: ...rity pending enabled exception 0 no pending exceptions Nonzero the exception number of the highest priority pending enabled exception The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the PRIMASK register 11 RETTOBASE RO Indicates whether there are preempted active exceptions 0 there are preempted active exceptions to execute 1 there...

Page 232: ... See your vendor documentation for the alignment details of your device Note Table alignment requirements mean that bits 6 0 of the table offset are always zero 4 3 5 Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model endian status for data accesses and reset control of the system See the register summary in Table 4 12 on page 4 11...

Page 233: ...ty grouping field is implementation defined This field determines the split of group priority from subpriority see Binary point on page 4 18 7 3 Reserved 2 SYSRESETREQ WO System reset request bit is implementation defined 0 no system reset request 1 asserts a signal to the outer system that requests a reset This is intended to force a large system reset of all major components except for debug Thi...

Page 234: ...zero Note Determining preemption of an exception uses only the group priority field see Interrupt priority grouping on page 2 25 Table 4 18 Priority grouping Interrupt priority level value PRI_N 7 0 Number of PRIGROUP Binary pointa Group priority bits Subpriority bits Group priorities Subpriorities 0b000 bxxxxxxx y 7 1 0 128 2 0b001 bxxxxxx yy 7 2 1 0 64 4 0b010 bxxxxx yyy 7 3 2 0 32 8 0b011 bxxxx...

Page 235: ... 19 SCR bit assignments Bits Name Function 31 5 Reserved 4 SEVONPEND Send Event on Pending bit 0 only enabled interrupts or events can wakeup the processor disabled interrupts are excluded 1 enabled events and all interrupts including disabled interrupts can wakeup the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not...

Page 236: ...AULTMASK escalated handlers 0 data bus faults caused by load and store instructions cause a lock up 1 handlers running at priority 1 and 2 ignore data bus faults caused by load and store instructions Set this bit to 1 only when the handler and its data are in absolutely safe memory The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them 7 5 Re...

Page 237: ...2 22 for more information System Handler Priority Register 1 The bit assignments are 2 Reserved 1 USERSETMPEND Enables unprivileged software access to the STIR see Software Trigger Interrupt Register on page 4 8 0 disable 1 enable 0 NONBASETHRDENA Indicates how the processor enters Thread mode 0 processor can enter Thread mode only when no exception is active 1 processor can enter Thread mode from...

Page 238: ...The bit assignments are Table 4 22 SHPR2 register bit assignments Bits Name Function 31 24 PRI_11 Priority of system handler 11 SVCall 23 0 Reserved Table 4 23 SHPR3 register bit assignments Bits Name Function 31 24 PRI_15 Priority of system handler 15 SysTick exception 23 16 PRI_14 Priority of system handler 14 PendSV 15 0 Reserved 31 24 23 0 PRI_11 Reserved PRI_15 31 15 0 16 24 23 PRI_14 Reserve...

Page 239: ...dingb 14 BUSFAULTPENDED BusFault exception pending bit reads as 1 if exception is pendingb 13 MEMFAULTPENDED MemManage exception pending bit reads as 1 if exception is pendingb 12 USGFAULTPENDED UsageFault exception pending bit reads as 1 if exception is pendingb 11 SYSTICKACT SysTick exception active bit reads as 1 if exception is activec 10 PENDSVACT PendSV exception active bit reads as 1 if exc...

Page 240: ...ubsections describe the subregisters that make up the CFSR MemManage Fault Status Register on page 4 25 BusFault Status Register on page 4 26 UsageFault Status Register on page 4 28 The CFSR is byte accessible You can access the CFSR or its subregisters as follows access the complete CFSR with a word access to 0xE000ED28 access the MMFSR with a byte access to 0xE000ED28 access the MMFSR and BFSR w...

Page 241: ...xt area on the stack might be incorrect The processor has not written a fault address to the MMAR 3 MUNSTKERR MemManage fault on unstacking for a return from exception 0 no unstacking fault 1 unstack for an exception return has caused one or more access violations This fault is chained to the handler This means that when this bit is 1 the original return stack is still present The processor has no...

Page 242: ...returning to a stacked active BusFault handler whose BFAR value has been overwritten 6 Reserved 5 LSPERRa 0 no bus fault occurred during floating point lazy state preservation 1 a bus fault occurred during floating point lazy state preservation 4 STKERR BusFault on stacking for exception entry 0 no stacking fault 1 stacking for an exception entry has caused one or more BusFaults When the processor...

Page 243: ...efore the processor enters the handler for the imprecise BusFault the handler detects both IMPRECISERR set to 1 and one of the precise fault status bits set to 1 1 PRECISERR Precise data bus error 0 no precise data bus error 1 a data bus error has occurred and the PC value stacked for the exception return points to the instruction that caused the fault When the processor sets this bit is 1 it writ...

Page 244: ...n return points to the instruction that performed the divide by zero Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1 see Configuration and Control Register on page 4 19 8 UNALIGNED Unaligned access UsageFault 0 no unaligned access fault or unaligned access trapping not enabled 1 the processor has made an unaligned memory access Enable trapping of unaligned accesses b...

Page 245: ... instruction that tried to perform the illegal load of the PC 1 INVSTATE Invalid state UsageFault 0 no invalid state UsageFault 1 the processor has attempted to execute an instruction that makes illegal use of the EPSR When this bit is set to 1 the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR This bit is not set to 1 if an undefined...

Page 246: ...TBL Reserved Table 4 28 HFSR bit assignments Bits Name Function 31 DEBUGEVT Reserved for Debug use When writing to the register you must write 0 to this bit otherwise behavior is Unpredictable 30 FORCED Indicates a forced hard fault generated by escalation of a fault with configurable priority that cannot be handles either because of priority or because it is disabled 0 no forced HardFault 1 force...

Page 247: ...ry in Table 4 12 on page 4 11 for its attributes This register is read write to clear This means that bits in the register read normally but writing 1 to any bit clears that bit to 0 The bit assignments are Each AFSR bit maps directly to an AUXFAULT input of the processor and a single cycle HIGH signal on the input sets the corresponding AFSR bit to one It remains set to 1 until you write 1 to the...

Page 248: ...AR or BFAR value 2 Read the MMARVALID bit in the MMFSR or the BFARVALID bit in the BFSR The MMFAR or BFAR address is valid only if this bit is 1 Software must follow this sequence because another higher priority exception might change the MMFAR or BFAR value For example if a higher priority handler preempts the current fault handler the other fault might change the MMFAR or BFAR value ...

Page 249: ...nt a reference clock See the register summary in Table 4 32 for its attributes The bit assignments are Table 4 32 System timer registers summary Address Name Type Required privilege Reset value Description 0xE000E010 SYST_CSR RW Privileged a SysTick Control and Status Register 0xE000E014 SYST_RVR RW Privileged Unknown SysTick Reload Value Register on page 4 34 0xE000E018 SYST_CVR RW Privileged Unk...

Page 250: ...re activated when counting from 1 to 0 The RELOAD value is calculated according to its use For example to generate a multi shot timer with a period of N processor clock cycles use a RELOAD value of N 1 If the SysTick interrupt is required every 100 clock pulses set RELOAD to 99 2 CLKSOURCE Indicates the clock source 0 external clock 1 processor clock 1 TICKINT Enables SysTick exception request 0 c...

Page 251: ...sor clock or external clock 31 0 CURRENT Reserved 23 24 Table 4 35 SYST_CVR register bit assignments Bits Name Function 31 24 Reserved 23 0 CURRENT Reads return the current value of the SysTick counter A write of any value clears the field to 0 and also clears the SYST_CSR COUNTFLAG bit to 0 31 0 TENMS Reserved 23 24 30 SKEW NOREF 29 Table 4 36 SYST_CALIB register bit assignments Bits Name Functio...

Page 252: ...lock signals during deep sleep mode If this happens the SysTick counter stops Ensure software uses aligned word accesses to access the SysTick registers The SysTick counter reload and current value are not initialized by hardware This means the correct initialization sequence for the SysTick counter is 1 Program reload value 2 Clear current value 3 Program Control and Status register ...

Page 253: ... prohibited by the MPU the processor generates a MemManage fault This causes a fault exception and might cause termination of the process in an OS environment In an OS environment the kernel can update the MPU region setting dynamically based on the process to be executed Typically an embedded OS uses the MPU for memory protection Configuration of MPU regions is based on memory types see Memory re...

Page 254: ...00000000 Alias of RBAR see MPU Region Base Address Register on page 4 40 0xE000EDA8 MPU_RASR_A1 RW Privileged 0x00000000 Alias of RASR see MPU Region Attribute and Size Register on page 4 41 0xE000EDAC MPU_RBAR_A2 RW Privileged 0x00000000 Alias of RBAR see MPU Region Base Address Register on page 4 40 0xE000EDB0 MPU_RASR_A2 RW Privileged 0x00000000 Alias of RASR see MPU Region Attribute and Size R...

Page 255: ...alue of the ENABLE bit 31 1 0 Reserved HFNMIENA ENABLE 2 PRIVDEFENA 3 Table 4 40 MPU_CTRL register bit assignments Bits Name Function 31 3 Reserved 2 PRIVDEFENA Enables privileged software access to the default memory map 0 If the MPU is enabled disables use of the default memory map Any memory access to a location not covered by any enabled region causes a fault 1 If the MPU is enabled enables us...

Page 256: ...ble when handling a hard fault or NMI exception or when FAULTMASK is enabled Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities 4 5 3 MPU Region Number Register The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers See the register summary in Table 4 38 on page 4 38 for its attributes The bit assignments are Normally you wr...

Page 257: ...bregions See the register summary in Table 4 38 on page 4 38 for its attributes MPU_RASR is accessible using word or halfword accesses the most significant halfword holds the region attributes the least significant halfword holds the region size and the region and subregion enable bits VALID ADDR 31 N N 1 5 4 3 0 Reserved REGION If the region size is 32B the ADDR field is bits 31 5 and there is no...

Page 258: ...able bit 0 instruction fetches enabled 1 instruction fetches disabled 27 Reserved 26 24 AP Access permission field see Table 4 47 on page 4 44 23 22 Reserved 21 19 17 16 TEX C B Memory access attributes see Table 4 45 on page 4 43 18 S Shareable bit see Table 4 45 on page 4 43 15 8 SRD Subregion disable bits For each bit in this field 0 corresponding sub region is enabled 1 corresponding sub regio...

Page 259: ... Register on page 4 40 Note 0b00100 4 32B 5 Minimum permitted size 0b01001 9 1KB 10 0b10011 19 1MB 20 0b11101 29 1GB 30 0b11111 31 4GB 32 Maximum possible size Table 4 45 TEX C B and S encoding TEX C B S Memory type Shareability Other attributes 0b000 0 0 xa Strongly ordered Shareable 1 xa Device Shareable 1 0 0 Normal Not shareable Outer and inner write through No write allocate 1 Shareable 1 0 N...

Page 260: ... MPU_RBAR and MPU_RASR aliases to program up to four regions simultaneously using an STM instruction Updating an MPU region using separate words Simple code to configure one region R1 region number R2 size enable R3 attributes R4 address LDR R0 MPU_RNR 0xE000ED98 MPU region number register Table 4 46 Cache policy for memory attribute encoding Encoding AA or BB Corresponding cache policy 00 Non cac...

Page 261: ... the exception entry and exception return mechanism cause memory barrier behavior Software does not require any memory barrier instructions during MPU setup because it accesses the MPU through the PPB which is a Strongly Ordered memory region For example if you want all of the memory access behavior to take effect immediately after the programming sequence use a DSB instruction and an ISB instruct...

Page 262: ...n overlaps the disabled subregion the MPU issues a fault Regions of 32 64 and 128 bytes do not support subregions With regions of these sizes you must set the SRD field to 0x00 otherwise the MPU behavior is Unpredictable Example of SRD use Two regions with the same base address overlap Region one is 128KB and region two is 512KB To ensure the attributes from region one apply to the first 128KB reg...

Page 263: ... application code more portable The values given are for typical situations In special systems such as multiprocessor designs or designs with a separate DMA engine the shareability attribute might be important In these cases see the recommendations of the memory device manufacturer Table 4 48 Memory region attributes for a microcontroller Memory region TEX C B S Memory type and attributes Flash me...

Page 264: ...rocessor Access Control Register The CPACR register specifies the access privileges for coprocessors See the register summary in Cortex M4F floating point system registers for its attributes The bit assignments are Table 4 49 Cortex M4F floating point system registers Address Name Type Reset Description 0xE000ED88 CPACR RW 0x00000000 Coprocessor Access Control Register 0xE000EF34 FPCCR RW 0xC00000...

Page 265: ...bled or priority did not permit setting MON_PEND when the floating point stack frame was allocated 1 DebugMonitor is enabled and priority permits setting MON_PEND when the floating point stack frame was allocated 7 Reserved 6 BFRDY 0 BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating point stack frame was allocated 1 BusFault is enab...

Page 266: ...stack frame was allocated 0 LSPACT 0 Lazy state preservation is not active 1 Lazy state preservation is active floating point stack frame has been allocated but saving state to it has been deferred Table 4 51 FPCCR register bit assignments continued Bits Name Function Table 4 52 FPCAR register bit assignments Bits Name Function 31 3 ADDRESS The location of the unpopulated floating point register s...

Page 267: ...ield is 0b00 Round to Nearest RN mode 0b01 Round towards Plus Infinity RP mode 0b10 Round towards Minus Infinity RM mode 0b11 Round towards Zero RZ mode The specified rounding mode is used by almost all floating point instructions 21 8 Reserved 7 IDC Input Denormal cumulative exception bit see bits 4 0 6 5 Reserved 4 IXC Cumulative exception bits for floating point exceptions see also bit 7 Each o...

Page 268: ... for enabling the FPU in both privileged and user modes The processor must be in privileged mode to read from and write to the CPACR Example 4 1 Enabling the FPU CPACR is located at address 0xE000ED88 LDR W R0 0xE000ED88 Read CPACR LDR R1 R0 Set bits 20 23 to enable CP10 and CP11 coprocessors ORR R1 R1 0xF 20 Write back the modified value to the CPACR STR R1 R0 wait for store to complete DSB reset...

Page 269: ...ndix A Cortex M4 Options This appendix describes the configuration options for a Cortex M4 processor implementation It shows what features of a Cortex M4 implementation are determined by the device manufacturer It contains the following section Cortex M4 implementation options on page A 2 ...

Page 270: ...r NVIC registers in Table 4 2 on page 4 3 The appropriate register descriptions in sections Interrupt Set enable Registers on page 4 4 to Interrupt Priority Registers on page 4 7 Vector Table Offset Register on page 4 16 including the figure and Table 4 16 on page 4 16 See the configuration information in the section for guidance on the required configuration Number of priority bits The implemente...

Page 271: ...ented see Optional bit banding on page 2 16 and Memory model on page 2 12 SysTick timer The SYST_CALIB register is implementation defined This can affect SysTick Calibration Value Register on page 4 35 The entry for SYST_CALIB in Table 4 32 on page 4 33 Table A 1 Effects of the Cortex M4 implementation options continued Option Description and affected documentation ...

Page 272: ... are divisible by four and two respectively Banked register A register that has multiple physical copies where the state of the processor determines which copy is used The Stack Pointer SP R13 is a banked register Base register In instruction descriptions a register specified by a load or store instruction that is used to hold the base value for the address calculation for the instruction Dependin...

Page 273: ...ition field A four bit field in an instruction that specifies a condition under which the instruction can execute Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts executing it executes normally Otherwise the instruction does nothing Context The environment that each process operates in for a multitasking operating syste...

Page 274: ...ction descriptions the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction See also Base register Instruction cycle count The number of cycles that an instruction occupies the Execute stage o...

Page 275: ...te as 0 or all 0s for bit fields by software or preserved by writing the same value back that has been previously read from the same field on the same processor Thread safe In a multi tasking environment thread safe functions use safeguard mechanisms when accessing shared resources to ensure correct operation without the risk of shared access conflicts Thumb instruction One or two halfwords that s...

Page 276: ...he on line replacement following a cache miss Otherwise writes by the processor only update the cache This is also known as copyback Write buffer A block of high speed memory arranged as a FIFO buffer between the data cache and main memory whose purpose is to optimize stores to main memory Write through WT In a write through cache data is written to main memory at the same time as the cache is upd...

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