ARM ARM9TDMI Technical Reference Manual Download

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Debug Support

ARM DDI0145B

5-33

Figure 5-7 Debug exit sequence

It can be seen in Figure 5-8 on page 5-34 that two instructions are fetched after that
which breakpoints. Figure 5-8 on page 5-34, shows

DBGACK

masks the first three

instruction fetches out of the debug state, corresponding to the breakpoint instruction,
and the two instructions prefetched after it.

Note

When a system speed access occurs,

DBGACK

remains HIGH, masking any memory

access.

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Summary of Contents for ARM9TDMI

Page 2: ...t described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of th...

Page 3: ... 2 Processor block diagram 1 3 Chapter 2 Programmer s Model 2 1 About the programmer s model 2 2 2 2 Pipeline implementation and interlocks 2 4 Chapter 3 ARM9TDMI Processor Core Memory Interface 3 1 About the memory interface 3 2 3 2 Instruction interface 3 4 3 3 Endian effects for instruction fetches 3 6 3 4 Data interface 3 7 3 5 Unidirectional bidirectional mode interface 3 10 3 6 Endian effect...

Page 4: ...k switching during test 5 28 5 10 Determining the core state and system state 5 29 5 11 Exit from debug state 5 32 5 12 The behavior of the program counter during debug 5 35 5 13 EmbeddedICE macrocell 5 38 5 14 Vector catching 5 46 5 15 Single stepping 5 47 5 16 Debug communications channel 5 48 Chapter 6 Test Issues 6 1 About testing 6 2 6 2 Scan chain 0 bit order 6 3 Chapter 7 Instruction Cycle ...

Page 7: ...face introduces the ARM9TDMI Revision 1 and subsequent revisions which is a member of the ARM family of general purpose microprocessors It contains the following sections About this document on page viii Further reading on page ix Typographical conventions on page x Feedback on page xi ...

Page 8: ...al buses DD 31 0 and DDIN 31 0 instead of a single bidirectional data bus This is described in Unidirectional bidirectional mode interface on page 3 10 The value returned by the JTAG TAP controller IDCODE instruction is the value present on the new TAPID 31 0 input bus This allows the ID code to be easily changed for each chip design Intended audience This document has been written for experienced...

Page 9: ...ix Further reading This section lists publications by ARM Limited and by third parties ARM publications ARM Architecture Reference Manual ARM DDI 0100 ARM7TDMI Data Sheet ARM DDI 0029 Other reading IEEE Std 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture ...

Page 10: ...ate italic Highlights special terminology cross references and citations typewriter Denotes text that may be entered at the keyboard such as commands file names and program names and source code typewriter Denotes a permitted abbreviation for a command or option The underlined text may be entered instead of the full command or option name typewriter italic Denotes arguments to commands or function...

Page 11: ...cument please send an email to errata arm com giving the document title the document number the page number s to which your comments refer a concise explanation of your comments General suggestions for additions and improvements are also welcome Feedback on the ARM9TDMI If you have any comments or suggestions about the ARM9TDMI please contact your supplier giving the product name a concise explana...

Page 13: ...d All rights reserved 1 1 Chapter 1 Introduction This chapter introduces the ARM9TDMI Revision 1 and subsequent revisions and shows its processor block diagram under the headings About the ARM9TDMI on page 1 2 Processor block diagram on page 1 3 ...

Page 14: ...igh performance and high code density The ARM9TDMI supports the ARM debug architecture and includes logic to assist in both hardware and software debug The ARM9TDMI supports both bidirectional and unidirectional connection to external memory systems The ARM9TDMI also includes support for coprocessors The ARM9TDMI processor core is implemented using a five stage pipeline consisting of fetch decode ...

Page 15: ...cessor block diagram Figure 1 1 ARM9TDMI processor block diagram Instruction Decode and Datapath control logic Instruction Pipeline Vectors IAreg PSR B A Imm PSRRD DINFWD DIN RESULT PC REGBANK MUL BData AData IINC DAreg Shift Cmux IA IAScan ID DAScan SHIFTER Amux Bmux C ALU nALUOut Byte Rot Sign Ex IDScan Byte Word Repl DINC DA DDIN DDScan DD ...

Page 17: ...M Limited All rights reserved 2 1 Chapter 2 Programmer s Model This chapter describes the programmer s model for the ARM9TDMI under the headings About the programmer s model on page 2 2 Pipeline implementation and interlocks on page 2 4 ...

Page 18: ...Architecture v4 and v4T These differences are explained in more detail below 2 1 1 Data abort model The ARM9TDMI implements the Base Restored Data Abort Model which differs from the Base updated data abort model implemented by ARM7TDMI The difference in the Data Abort Model affects only a very small section of operating system code the data abort handler It does not affect user code With the Base ...

Page 19: ...ARM9TDMI and ARM7TDMI ARM Architecture v4 and v4T also introduced a number of instruction set extension spaces to the ARM instruction set These are arithmetic instruction extension space control instruction extension space coprocessor instruction extension space load store instruction extension space Instructions in these spaces are UNDEFINED they cause an Undefined Instruction Exception The ARM9T...

Page 20: ... ARM implementations are fully interlocked so that software will function identically across different implementations without concern for pipeline effects Interlocks do affect instruction execution times For example the following sequence suffers a single cycle penalty due to a load use interlock on register R0 LDR R0 R7 ADD R5 R0 R1 For more details see Chapter 7 Instruction Cycle Summary and In...

Page 21: ...ht 1998 1999 ARM Limited All rights reserved 2 5 Figure 2 1 ARM9TDMI processor core instruction pipeline ǽřŗǱŗǾǰ ǰ ǽřŗǱŖǾ ǽřŗǱŖǾǰ ǰ ǰ ǽřŗǱŖǾ ǽřŗǱŖǾ 0 QVWUXFWLRQ 0HPRU FFHVV 5HJLVWHU HFRGH 5HJLVWHU 5HDG 6KLIW 8 DWD 0HPRU FFHVV 5HJLVWHU ULWH ...

Page 23: ...re and so the memory interface is separated into the instruction interface and the data interface The information in this chapter is broken down as follows About the memory interface on page 3 2 Instruction interface on page 3 4 Endian effects for instruction fetches on page 3 6 Data interface on page 3 7 Unidirectional bidirectional mode interface on page 3 10 Endian effects for data transfers on...

Page 24: ...can operate in both big endian and little endian memory configurations and this is selected by the BIGEND input The endian configuration affects both interfaces so care must be taken in designing the memory interface logic to allow correct operation of the processor core For system purposes it is normally necessary to provide some mechanism whereby the data interface can access instruction memory ...

Page 25: ...s the internal core clock is exported on the ECLK signal This timing is shown below in Figure 3 1 Alternatively wait states may be inserted by stretching either phase of GCLK before it is applied to the processor ARM9TDMI does not contain any dynamic logic which relies on regular clocking to maintain its state Therefore there is no limit on the maximum period for which GCLK may be stretched in eit...

Page 26: ...ignal will indicate whether the fetch is sequential or non sequential to the previous access All these signals become valid towards the end of phase 2 of the cycle that precedes the instruction fetch The timing is shown in Figure 3 2 on page 3 5 The full encoding of InMREQ and ISEQ is as follows Note The 1 1 case does not occur in this implementation but may be used in the future Instruction fetch...

Page 27: ...Limited All rights reserved 3 5 Note A sequential cycle can occur immediately after an internal cycle Figure 3 2 shows the cycle timing for an N followed by an S cycle where there is a prefetch abort on the S cycle Figure 3 2 Instruction fetch timing ǽřŗǱŗǾ ǽřŗǱŖǾ 1 F FOH 6 F FOH ...

Page 28: ... are fetched When the processor is in ARM state its endian configuration does not affect the instruction fetches as all 32 bits of ID 31 0 are read However in Thumb state the processor will read either from the upper half of the instruction data bus ID 31 16 or from the lower half ID 15 0 This is determined by the endian configuration of the memory system which is indicated by the BIGEND signal an...

Page 29: ...ecomes valid at approximately the same time as the data address bus For reads DDIN 31 0 must be driven with valid data for the falling edge of GCLK at the end of phase 2 For writes by the processor data will become valid in phase 1 and remain valid throughout phase 2 Both reads and writes are illustrated in Figure 3 3 on page 3 9 See About the coprocessor interface on page 4 2 for further informat...

Page 30: ... multiple instructions and only ever goes HIGH when DnMREQ is LOW This signal effectively gives the same information as DSEQ but a cycle ahead This information is provided to allow external logic more time to decode sequential cycles Figure 3 3 on page 3 9 shows a load multiple of four words followed by an MCR followed by an aborted store Note the following The DMORE signal is active in the first ...

Page 32: ...ansfer write data It is only driven when the ARM9TDMI is performing a write to memory By wiring DD 31 0 to the input DDIN 31 0 bus externally to the ARM9TDMI a bidirectional data data bus can be formed If UNIEN is HIGH then DD 31 0 and all other ARM9TDMI outputs are permanently driven DD 31 0 then forms a unidirectional write data data bus In this mode the tristate enable pins IABE DABE DDBE TBE a...

Page 33: ...DD 15 8 and DD 7 0 This considerably eases the memory control logic design and helps overcome any endian effects For data reads the processor will read a specific part of the data bus This is determined by the endian configuration the size of the transfer and bits 1 and 0 of the data address bus Table 3 5 shows which bits of the data bus are read for 16 bit reads and Table 3 6 shows which bits are...

Page 34: ...hronously change to indicate an internal cycle If GCLK is LOW they will not change until after the GCLK goes HIGH When nRESET is driven HIGH the ARM9TDMI starts requesting memory again once the signal has been synchronized and the first memory access will start two cycles later The nRESET signal is sampled on the falling edge of GCLK with the first memory access starting two cycles later The behav...

Page 37: ... describes the ARM9TDMI coprocessor interface and details the following operations About the coprocessor interface on page 4 2 LDC STC on page 4 3 MCR MRC on page 4 9 Interlocked MCR on page 4 11 CDP on page 4 13 Privileged instructions on page 4 15 Busy waiting and interrupts on page 4 16 Coprocessor 15 MCRs on page 4 17 ...

Page 38: ...oprocessor determines when an instruction is being fetched by the ARM9TDMI so that the instruction can be loaded into the coprocessor and the pipeline follower advanced Note A cached ARM9TDMI core typically has an external coprocessor interface block the main purpose of which is to latch the instruction data bus ID one of the data buses DD 31 0 or DDIN 31 0 and relevant ARM9TDMI control signals be...

Page 39: ...RM Limited All rights reserved 4 3 4 2 LDC STC The number of words transferred is determined by how the coprocessor drives the CHSD 1 0 and CHSE 1 0 buses In the example four words of data are transferred Figure 4 1 on page 4 4 shows the ARM9TDMI LDC STC cycle timing ...

Page 40: ...98 1999 ARM Limited All rights reserved ARM DDI0145B Figure 4 1 ARM9TDMI LDC STC cycle timing ǽŘŝǱŖǾ ǽŗǱŖǾ ǽŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ HFRGH HFXWH 2 HFXWH 2 HFXWH 2 HFXWH 67 0HPRU ULWH HFRGH HFXWH 2 HFXWH 2 HFXWH 2 HFXWH 67 0HPRU ULWH 2 2 2 67 JQRUHG ...

Page 41: ...stage of the coprocessor pipeline the instruction in the decode stage of the coprocessor pipeline should enter its execute stage the fetched instruction should be latched In all other cases the ARM9TDMI pipeline is stalled and the coprocessor pipeline should not advance Figure 4 2 shows the timing for these signals and indicates when the coprocessor pipeline should advance its state In this timing...

Page 42: ...on the handshake signals indicate the ABSENT state In this case the ARM9TDMI processor core takes the undefined instruction trap WAIT If there is a coprocessor attached that can handle the instruction but not immediately the coprocessor handshake signals are driven to indicate that the ARM9TDMI processor core should stall until the coprocessor can catch up This is known as the busy wait condition ...

Page 43: ... the coprocessor drives the coprocessor handshake signals with a number of GO states and in the penultimate cycle LAST LAST indicating that the next transfer is the final one If there was only one transfer the sequence would be WAIT WAIT LAST For both MRC and STC instructions the DDIN 31 0 bus is owned by the coprocessor and can hence be driven by the coprocessor from the cycle after the relevant ...

Page 44: ...the ARM9TDMI processor will hang if a coprocessor enters the pipeline If multiple coprocessors are to be attached to the interface the handshaking signals can be combined by ANDing bit 1 and ORing bit 0 In the case of two coprocessors which have handshaking signals CHSD1 CHSE1 and CHSD2 CHSE2 respectively CHSD 1 CHSD1 1 AND CHSD2 1 CHSD 0 CHSD1 0 OR CHSD2 0 CHSE 1 CHSE1 1 AND CHSE2 1 CHSE 0 CHSE1 ...

Page 45: ...gure 4 3 Figure 4 3 ARM9TDMI MCR MRC transfer timing First InMREQ is driven LOW to denote that the instruction on ID is entering the decode stage of the pipeline This causes the coprocessor to decode the new instruction and drive CHSD 1 0 as required In the next cycle InMREQ is driven LOW to denote ǽřŗǱŖǾ ǽŗǱŖǾ ǽŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ HFRGH HFXWH 2 0HPRU 2 ULWH 67 HFRGH HFXWH 2 0HPRU 2 ULWH 67 357 67 ...

Page 46: ...nal is driven HIGH and the CHSD 1 0 handshake bus is examined it is ignored in all other cases For any successive execute cycles the CHSE 1 0 handshake bus is examined When the LAST condition is observed the instruction is committed In the case of an MCR the DD 31 0 bus is driven with the register data In the case of an MRC DDIN 31 0 is sampled at the end of the ARM9TDMI memory stage and written t...

Page 47: ... the ARM9TDMI pipeline will interlock for one or more cycles until the data is available An example of this is where the register being transferred is the destination from a preceding LDR instruction In this situation the MCR instruction will enter the decode stage of the coprocessor pipeline and remain there for a number of cycles before entering the execute stage Figure 4 4 on page 4 12 gives an...

Page 48: ...yright 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 4 4 ARM9TDMI interlocked MCR ǽřŗǱŖǾ ǽŗǱŖǾ ǽŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ HFRGH LQWHUORFN HFRGH HFXWH 7 HFXWH 67 0HPRU ULWH HFRGH HFRGH HFXWH 7 HFXWH 67 0HPRU ULWH 0 5 05 7 7 67 JQRUHG ...

Page 49: ... of execute if the coprocessor can execute the instruction immediately it drives CHSD 1 0 with LAST if the instruction requires a busy wait cycle the coprocessor drives CHSD 1 0 with WAIT and then CHSE 1 0 with LAST Figure 4 5 on page 4 14 shows a CDP which is cancelled due to the previous instruction causing a data abort The CDP instruction enters the execute stage of the pipeline and is signalle...

Page 50: ... 14 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 4 5 ARM9TDMI late cancelled CDP Ǳ Ǳ ǽřŗǱŖǾ ǽŗǱŖǾ ǽŗǱŖǾ HFXWH 0HPRU FHSWLRQ QWU 6WDUW FHSWLRQ RQWLQXHV HFRGH HFXWH HFRGH HFXWH 0HPRU DWH DQFHOOHG 357 67 JQRUHG ...

Page 51: ...TRANS changes after a mode change Figure 4 6 ARM9TDMI privileged instructions The first two CHSD responses are ignored by the ARM9TDMI because it is only the final CHSD response as the instruction moves from decode into execute that counts This allows the coprocessor to change its response as InTRANS InM 4 0 changes Ǳ Ǳ ǽřŗǱŖǾ Ȧ ǽŚǱŖǾ ǽŗǱŖǾ ǽŗǱŖǾ HFXWH HFXWH FOH HFXWH FOH 0HPRU ULWH HFRGH HFRGH HF...

Page 52: ...o CHSE 1 0 for as many cycles as necessary to keep the instruction in the busy wait loop For interrupt latency reasons the coprocessor may be interrupted while busy waiting thus causing the instruction to be abandoned Abandoning execution is done through PASS The coprocessor must monitor the stage of PASS during every busy wait cycle If it is HIGH the instruction should still be executed If it is ...

Page 53: ...or on the IA and DA buses To do this the coprocessor should drive GO on the coprocessor handshake signals for a number of cycles For each cycle that the coprocessor responded with GO on the handshake signals the coprocessor data will be driven onto IA and DA as shown in Figure 4 8 Figure 4 8 ARM9TDMI coprocessor 15 MCRs ǽřŗǱŖǾ ǽŗǱŖǾ ǽŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ HFRGH HFXWH 2 HFXWH 2 HFXWH 67 0HPRU U...

Page 55: ...nterface on page 5 11 The JTAG state machine on page 5 12 Test data registers on page 5 19 ARM9TDMI core clocks on page 5 26 Clock switching during debug on page 5 27 Clock switching during test on page 5 28 Determining the core state and system state on page 5 29 Exit from debug state on page 5 32 The behavior of the program counter during debug on page 5 35 EmbeddedICE macrocell on page 5 38 Vec...

Page 56: ...ug state At this point the internal state of the core and the external state of the system may be examined Once examination is complete the core and system state may be restored and program execution resumed The ARM9TDMI is forced into debug state either by a request on one of the external debug interface signals or by an internal functional unit known as the EmbeddedICE macrocell Once in debug st...

Page 57: ... host The debug host is a computer for example a personal computer running a software debugger such as armsd for example or ADW The debug host allows the user to issue high level commands such as set breakpoint at location XX or examine the contents of memory from 0x0 to 0x100 5 2 2 The protocol converter The debug host is connected to the ARM9TDMI development system via an interface an RS232 for ...

Page 58: ...bugging is the lowest level of the system The debug extensions allow the user to stall the core from program execution examine its internal state and the state of the memory system and then resume program execution The debug host and the protocol converter are system dependent The rest of this chapter describes the ARM9TDMI hardware debug extensions ...

Page 59: ...ving the EmbeddedICE macrocell an entire phase in which to perform the comparison This is shown in Figure 5 2 on page 5 6 External logic such as additional breakpoint comparators may be built to extend the functionality of the EmbeddedICE macrocell Their output should be applied to the IEBKPT input This signal is simply ORed with the internally generated Breakpoint signal before being applied to t...

Page 60: ...ndent and as the data may be incorrect the breakpoint may have been triggered incorrectly SWI and undefined instructions are treated in the same way as any other instruction which may have a breakpoint set on it Therefore the breakpoint takes priority over the SWI or undefined instruction On an instruction boundary if there is a breakpointed instruction and an interrupt IRQ or FIQ the interrupt is...

Page 61: ...ming of debug entry following a watchpointed load in this case is shown in Figure 5 3 on page 5 8 Note Although instruction 5 enters the execute state it is not executed and there is no state update as a result of this instruction Once the debugging session is complete normal continuation would involve a return to instruction 5 the next instruction in the code sequence which has not yet been execu...

Page 62: ...ght 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 5 3 Watchpoint entry with data processing instruction ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ GHEXJ GHEXJ GHEXJ 0 S S S 0 S S OGU OGU OGU 0OGU OGU 0 0 Z Z ZOGU Z S Z Z 5 S ...

Page 63: ...rt ARM DDI0145B Copyright 1998 1999 ARM Limited All rights reserved 5 9 Figure 5 4 Watchpoint entry with branch ǽřŗǱŗǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ GHEXJ GHEXJ GHEXJ 7 7 7 0 OGU OGU OGU 0OGU OGU 7 7 7 7 5 7 7 7 7 ...

Page 64: ... interfaces will indicate internal cycles This allows the rest of the memory system to ignore the ARM9TDMI and function as normal Since the rest of the system continues operation the ARM9TDMI will ignore aborts and interrupts The BIGEND signal should not be changed by the system while in debug state If it changes not only will there be a synchronization problem but the programmer s view of the ARM...

Page 65: ... is provided for an optional fourth scan chain This is intended to be used for an external boundary scan chain around the pads of a packaged device The signals provided for this scan chain are described on Scan chain 3 on page 5 25 The three scan chains of the ARM9TDMI are referred to as scan chain 0 1 and 2 Note The ARM9TDMI TAP controller supports 32 scan chains Scan chains 0 to 15 have been res...

Page 66: ...in the TAP controller The state numbers are also shown on the diagram These are output from the ARM9TDMI on the TAPSM 3 0 bits Figure 5 5 Test access port TAP controller state transitions 6HOHFW 5 6FDQ DSWXUH 5 WPV 6KLIW 5 WPV LW 5 WPV 3DXVH 5 WPV LW 5 WPV 8SGDWH 5 WPV WPV WPV WPV WPV WPV 6HOHFW 5 6FDQ DSWXUH 5 WPV 6KLIW 5 WPV LW 5 WPV 3DXVH 5 WPV LW 5 WPV 8SGDWH 5 WPV 7HVW RJLF 5HVHW 5XQ 7HVW GOH...

Page 67: ...n cells do not intercept any of the signals passing between the external system and the core 2 The IDCODE instruction is selected If the TAP controller is put into the Shift DR state and TCK is pulsed the contents of the ID register are clocked out of TDO 5 5 2 Pullup resistors The IEEE 1149 1 standard effectively requires TDI and TMS to have internal pullup resistors In order to minimize static c...

Page 68: ...and TDO When the instruction register is loaded with the EXTEST instruction all the scan cells are placed in their test mode of operation In the CAPTURE DR state inputs from the system logic and outputs from the output scan cells to the system are captured by the scan cells In the SHIFT DR state the previously captured test data is shifted out of the scan chain via TDO while new test data is shift...

Page 69: ...URE DR state the value of the data applied from the core logic to the output scan cells and the value of the data applied from the system logic to the input scan cells is captured In the SHIFT DR state the previously captured test data is shifted out of the scan chain via the TDO pin while new test data is shifted in via the TDI pin IDCODE 1110 The IDCODE instruction connects the device identifica...

Page 70: ... UPDATE DR state Note All unused instruction codes default to the BYPASS instruction CLAMP 0101 This instruction connects a 1 bit shift register the bypass register between TDI and TDO When the CLAMP instruction is loaded into the instruction register the state of all the output signals is defined by the values previously loaded into the currently loaded scan chain Note This instruction should onl...

Page 71: ...struction is to ensure that during production test each output can be disabled when its data value is either a logic 0 or logic 1 In the CAPTURE DR state a logic 0 is captured by the bypass register In the SHIFT DR state test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle The first bit shifted out will be a zero The bypass register is not affected i...

Page 72: ...tion is used to restart the processor on exit from debug state The RESTART instruction connects the bypass register between TDI and TDO and the TAP controller behaves as if the BYPASS instruction had been loaded The processor will resynchronize back to the memory system once the RUN TEST IDLE state is entered ...

Page 73: ...truction in the instruction register serial data is transferred from TDI to TDO in the SHIFT DR state with a delay of one TCK cycle There is no parallel output from the bypass register A logic 0 is loaded from the parallel input of the bypass register in CAPTURE DR state 5 6 2 ARM9TDMI device identification ID code register Purpose Reads the 32 bit device identification code No programmable supple...

Page 74: ...ent instruction On reset IDCODE becomes the current instruction 5 6 4 Scan chain select register Purpose Changes the current active scan chain Length 5 bits Operating mode After SCAN_N has been selected as the current instruction when in SHIFT DR state the scan chain select register is selected as the serial path between TDI and TDO During the CAPTURE DR state the value 0b10000 is loaded into this...

Page 75: ...ted by ARM are shown in Table 5 3 An external scan chain may take any other number The serial data stream applied to the external scan chain is made present on SDIN The serial data back from the scan chain must be presented to the TAP controller on the SDOUTBS input The scan chain present between SDIN and SDOUTBS will be connected between TDI and TDO whenever scan chain 3 is selected or when any o...

Page 76: ...ogic are captured in the output cells During SHIFT DR this captured data is shifted out while a new serial test pattern is scanned in thus applying known stimuli to the inputs During RUN TEST IDLE the core is clocked Normally the TAP controller should only spend one cycle in RUN TEST IDLE The whole operation may then be repeated EXTEST allows inter device testing useful for verifying the connectio...

Page 77: ...be scanned into DDEN to be driven into the rest of the system If a logic 1 is scanned into DDEN the data data bus DD 31 0 will drive out the values stored in its scan cells If a logic 0 is scanned into DDEN DD 31 0 will capture the current input values While debugging the value placed in the SYSSPEED control bit determines whether the ARM9TDMI synchronizes back to system speed before executing the...

Page 78: ...o 0 Length 38 bits To access this serial register scan chain 2 must first be selected via the SCAN_N TAP controller instruction The TAP controller must then be placed in INTEST mode No action is taken during CAPTURE DR During SHIFT DR a data value is shifted into the serial register Bits 32 to 36 specify the address of the EmbeddedICE macrocell register to be accessed During UPDATE DR this registe...

Page 79: ...AMP or CLAMPZ instruction is selected PCLKBS This is the update clock generated in the UPDATE DR state Typically the value scanned into the chain will be transferred to the cell output on the rising edge of this signal ICAPCLKBS ECAPCLKBS These are the capture clocks used to sample data into the scan cells during INTEST and EXTEST respectively These clocks are generated in the CAPTURE DR state SHC...

Page 80: ...e core is clocked by GCLK and internal logic holds DCLK LOW When the ARM9TDMI is in the debug state the core is clocked by DCLK under control of the TAP state machine and GCLK may free run The selected clock is output on the ECLK signal for use by the external system Note When the core is being debugged and is running from DCLK nWAIT has no effect The two cases in which the clocks switch are durin...

Page 81: ... The ARM9TDMI is forced to use DCLK as the primary clock until debugging is complete On exit from debug the core must be allowed to synchronize back to GCLK This must be done in the following sequence The final instruction of the debug sequence must be shifted into the instruction data bus scan chain and clocked in by asserting DCLK At this point RESTART must be clocked into the TAP controller reg...

Page 82: ...ler can now be used to perform serial testing on the ARM9TDMI If scan chain 0 and INTEST are selected DCLK is generated while the state machine is in RUN TEST IDLE state During EXTEST DCLK is not generated On exit from test RESTART must be selected as the TAP controller instruction When this is done GCLK can be allowed to resume After INTEST testing care should be taken to ensure that the core is ...

Page 83: ...orce the processor into ARM state the following sequence of Thumb instructions should be executed on the core STR R0 R1 Save R0 before use MOV R0 PC Copy PC into R0 STR R0 R1 Save the PC in R0 BX PC Jump into ARM state MOV R8 R8 NOP no operation MOV R8 R8 NOP The above use of R1 as the base register for the stores is for illustration only any register could be used Since all Thumb instructions are...

Page 84: ...s All these instructions are said to execute at debug speed Debug speed is much slower than system speed since between each core clock 67 scan clocks occur in order to shift in an instruction or shift out data Executing instructions more slowly than usual is fine for accessing the core s state since the ARM9TDMI is fully static However this same method cannot be used for determining the state of t...

Page 85: ...ected in the TAP controller and debugging can resume To determine whether a system speed instruction has completed the debugger must look at SYSCOMP bit 3 of the Debug status register To access memory the ARM9TDMI must access memory through the data data bus interface as this access may be stalled indefinitely by nWAIT Therefore the only way to determine whether the memory access has completed is ...

Page 86: ...hine is in RUN TEST IDLE state allows conditions to be set up in other devices in a multiprocessor system without taking immediate effect Then when RUN TEST IDLE state is entered all the processors resume operation simultaneously The function of DBGACK is to tell the rest of the system when the ARM9TDMI is in debug state This can be used to inhibit peripherals such as watchdog timers that have rea...

Page 87: ...nstructions are fetched after that which breakpoints Figure 5 8 on page 5 34 shows DBGACK masks the first three instruction fetches out of the debug state corresponding to the breakpoint instruction and the two instructions prefetched after it Note When a system speed access occurs DBGACK remains HIGH masking any memory access ǽřŗǱŗǾ ǽřŗǱŖǾ QWHUQDO FOHV 1 6 6 E E E ...

Page 89: ...eviously breakpointed address For example if the ARM9TDMI entered debug state from a breakpoint set on a given address and two debug speed instructions were executed a branch of 7 addresses must occur four for debug entry plus two for the instructions plus one for the final branch The following sequence shows ARM instructions scanned into scan chain 1 This is the Most Significant Bit MSB first so ...

Page 90: ...wo s complement 1 E1A00000 NOP MOV R0 R0 SYSSPEED bit is set This will force a branch back to the abort vector causing the instructions at that location to be refetched and executed Note that after the abort service routine the instruction that caused the abort and watchpoint will be re executed This will cause the watchpoint to be generated and hence the ARM9TDMI will enter debug state again 5 12...

Page 91: ...the problem is much harder to fix because the abort was not caused by an instruction in the main program and the PC does not point to the instruction that caused the abort An abort handler usually looks at the PC to determine the instruction that caused the abort and hence the abort address In this case the value of the PC is invalid but the debugger will know the address of the location that was ...

Page 92: ...it 3 of the control mask register is always clear and cannot be programmed HIGH Bit 3 also determines whether the internal Breakpoint or Watchpoint signal should be driven by the result of the comparison Figure 5 9 on page 5 40 gives an overview of the operation of the EmbeddedICE macrocell The ARM9TDMI EmbeddedICE macrocell has logic that allows single stepping through code This reduces the work ...

Page 93: ...011 32 Watchpoint 0 data mask 01100 9 Watchpoint 0 control value 01101 8 Watchpoint 0 control mask 10000 32 Watchpoint 1 address value 10001 32 Watchpoint 1 address mask 10010 32 Watchpoint 1 data value 10011 32 Watchpoint 1 data mask 10100 9 Watchpoint 1 control value 10101 8 Watchpoint 1 control mask Table 5 4 ARM9TDMI EmbeddedICE macrocell register map continued Address Width Function ...

Page 94: ...xffffffff all bits set to 1 to make the entire data bus value ignored 5 13 2 Using the mask registers For each value register there is an associated mask register in the same format Setting a bit to 1 in the mask register causes the corresponding bit in the value register to be ignored in any comparison GGUHVV DWD 5 6FDQ KDLQ 5HJLVWHU 9DOXH 0DVN RPSDUDWRU 5DQJHRXW GGUHVV HFRGHU RQWURO RQWURO 7 2 7...

Page 95: ...ster for data comparison bit functions Bit Function DnRW Compares against the data not read write signal from the core in order to detect the direction of the data data bus activity nRW is 0 for a read and 1 for a write DMAS 1 0 Compares against the DMAS 1 0 signal from the core in order to detect the size of the data data bus activity DnTRANS Compares against the data not translate signal from th...

Page 96: ... the CHAIN input of watchpoint 0 The CHAINOUT output is derived from a latch The address control field comparator drives the write enable for the latch and the input to the latch is the value of the data field comparator The CHAINOUT latch is cleared when the control value register is written or when nTRST is LOW RANGE Can be connected to the range output of another watchpoint register In the ARM9...

Page 97: ...mplement for example debugger requests of the form breakpoint on address YYY only when in process XXX In the ARM9TDMI EmbeddedICE macrocell the CHAINOUT output of watchpoint 1 is connected to the CHAIN input of watchpoint 0 The CHAINOUT output is derived from a latch The address control field comparator drives the write enable for the latch and the input to the latch is the value of the data field...

Page 98: ...g status register The function of each bit in this register is as follows Bits 1 and 0 Allow the values on the synchronized versions of DBGRQ and DBGACK to be read Bit 2 Allows the state of the core interrupt enable signal IFEN to be read Since the capture clock for the scan chain may be asynchronous to the processor clock the DBGACK output from the core is synchronized before being used to genera...

Page 99: ...mbeddedICE macrocell controls logic to enable accesses to the exception vectors to be trapped in an efficient manner This is controlled by the vector catch register as shown in Figure 5 14 The functionality is described in Vector catching on page 5 46 Figure 5 14 Vector catch register 5HVHUYHG B ERUW 4 54 3B ERUW 6 8QGHI 5HVHW ...

Page 100: ...ocessor executes a SWI instruction while bit 2 of the Vector catch register is set the ARM9TDMI fetches an instruction from location 0x8 The vector catch hardware detects this access and forces the internal Breakpoint signal HIGH into the ARM9TDMI control logic This in turn forces the ARM9TDMI to enter debug state The behavior of the hardware is independent of the watchpoint comparators leaving th...

Page 101: ...s function is enabled by setting bit 3 of the debug control register The state of this bit should only be altered while the processor is in debug state If the processor exits debug state and this bit is HIGH the processor fetches an instruction executes it and then immediately reenters debug state This happens independently of the watchpoint comparators If a system speed data access is performed w...

Page 102: ...r 14 5 16 1 Debug comms channel registers The debug comms control register is read only and allows synchronized handshaking between the processor and the debugger Figure 5 15 Debug comms control register The function of each register bit is described below Bits 31 28 Contain a fixed pattern that denotes the EmbeddedICE macrocell version number in this case 0010 Bits 27 2 Unused Bit 1 Denotes from ...

Page 103: ... write register MRC p14 0 Rd C1 C0 Returns the debug data read register into Rd Note The Thumb instruction set does not support coprocessors so the ARM9TDMI must be operated in ARM state in order to access the debug comms channel 5 16 2 Communications via the comms channel There are two methods of communicating via the comms channel transmitting and receiving The following descriptions detail thei...

Page 104: ...he systems interrupt controller Receiving a message from the debugger Message transfer from the debugger to the processor is similar to sending a message to the debugger In this case the debugger polls the R bit of the debug comms control register If the R bit is LOW the comms data read register is free and data can be placed there for the processor to read If the R bit is set previously deposited...

Page 105: ...99 ARM Limited All rights reserved 6 1 Chapter 6 Test Issues This chapter examines the test issues for the ARM9TDMI and lists the scan chain 0 bit order under the headings About testing on page 6 2 Scan chain 0 bit order on page 6 3 ...

Page 106: ...igh fault coverage The ARM9TDMI processor core has a fully JTAG compatible scan chain which intersects all the inputs and outputs This allows the test patterns to be serialized and injected to the processor via the JTAG interface Both the parallel and serial test patterns are supplied to ARM9TDMI processor core licensees The scan chain also supports EXTEST allowing the connections between the ARM9...

Page 107: ... Input 32 ID 31 Input 33 SYSSPEED Internal 34 WPTANDBKPT Internal 35 DDEN Output 36 DD 31 Bidirectional 37 DD 30 Bidirectional 38 66 DD 29 1 Bidirectional 67 DD 0 Bidirectional 68 DA 31 Output 69 DA 30 Output 70 98 DA 29 1 Output 99 DA 0 Output 100 IA 31 Output 101 IA 30 Output 102 129 IA 29 2 Output 130 IA 1 Output 131 IEBKPT Input 132 DEWPT Input 133 EDBGRQ Input 134 EXTERN0 Input 135 EXTERN1 In...

Page 108: ...put 142 DDBE Input 143 InMREQ Output 144 DnMREQ Output 145 DnRW Output 146 DMAS 1 Output 147 DMAS 0 Output 148 PASS Output 149 LATECANCEL Output 150 ITBIT Output 151 InTRANS Output 152 DnTRANS Output 153 nRESET Input 154 nWAIT Input 155 IABORT Input 156 IABE Input 157 DABORT Input 158 DABE Input 159 nFIQ Input 160 nIRQ Input Table 6 1 Scan chain 0 bit order continued Number Signal Direction ...

Page 109: ...nput 167 CHSE 0 Input 168 UNIEN Input 169 ISEQ Output 170 InM 4 Output 171 InM 3 Output 172 InM 2 Output 173 InM 1 Output 174 InM 0 Output 175 DnM 4 Output 176 DnM 3 Output 177 DnM 2 Output 178 DnM 1 Output 179 DnM 0 Output 180 DSEQ Output 181 DMORE Output 182 DLOCK Output 183 ECLK Output 184 INSTREXEC Output Table 6 1 Scan chain 0 bit order continued Number Signal Direction ...

Page 111: ...Limited All rights reserved 7 1 Chapter 7 Instruction Cycle Summary and Interlocks This chapter gives the instruction cycle times and shows the timing diagrams for interlock timing Instruction cycle times on page 7 2 Interlocks on page 7 5 ...

Page 112: ... register transfer C cycle I Internal cycle I cycle N Non sequential cycle N cycle S Sequential cycle S cycle Table 7 2 Instruction cycle bus times Instruction Cycles Instruction bus Data bus Comment Data Op 1 1S 1I Normal case PC not destination Data Op 2 1S 1I 2I With register controlled shift PC not destination Data Op 3 2S 1N 3I PC destination register Data Op 4 2S 1N 1I 4I With register contr...

Page 113: ...ded byte used by following instruction B BL BX 3 2S 1N 3I All cases SWI Undefined 3 2S 1N 3I All cases CDP b 1 1S bI 1 b I All cases LDC STC b n 1S b n 1 I bI 1N n 1 S All cases MCR b 1 1S bI bI 1C All cases MRC b 1 1S bI bI 1C Normal case MRC b 2 1S b 1 I b I I 1C Following instruction uses transferred data MRS 1 1S 1T All cases MSR 1 1S 1T If only flags are updated mask_f MSR 3 1S 2I 3I If any b...

Page 114: ... ARM multiply instructions or bits 2 0 of the Thumb multiply instructions For ARM MUL MLA SMULL SMLAL and Thumb MUL m is 1 if bits 31 8 of the multiplier operand are all zero or one 2 if bits 31 16 of the multiplier operand are all zero or one 3 if bits 31 24 of the multiplier operand are all zero or all one 4 otherwise For ARM UMULL UMLAL m is 1 if bits 31 8 of the multiplier operand are all zero...

Page 115: ...r examples of this are given below Example 1 In this first example the following code sequence is executed LDR R0 R1 ADD R2 R0 R1 The ADD instruction cannot start until the data is returned from the load Therefore the ADD instruction has to delay entering the execute stage of the pipeline by one cycle The behavior on the instruction memory interface is shown in Figure 7 1 Figure 7 1 Single load in...

Page 116: ...igure 7 2 Figure 7 2 Two cycle load interlock Example 3 In this third example the following code sequence is executed LDM R12 R1 R3 ADD R2 R2 R1 The LDM takes three cycles to execute in the memory stage of the pipeline The ADD is therefore delayed until the LDM begins its final memory fetch The behavior of both the instruction and data memory interface are shown in Figure 7 3 on page 7 7 ǽřŗǱŗǾ ǽř...

Page 117: ...99 ARM Limited All rights reserved 7 7 Figure 7 3 LDM interlock Example 4 In the fourth example the following code sequence is executed LDM R12 R1 R3 ADD R4 R3 R1 ǽřŗǱŗǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ OGPE OGPE OGPE 0OGPE 0OGPE 0OGPE OGPE DGG DGG DGG DGG DGG 0DGG DGG 0 5 5 5 ...

Page 118: ... multiples the lowest register specified is transferred first and the highest specified register last Because the ADD is dependent on R3 there must be a further cycle of interlock while R3 is loaded The behavior on the instruction and data memory interface is shown in Figure 7 4 Figure 7 4 LDM dependent interlock ǽřŗǱŗǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ ǽřŗǱŖǾ OGPE OGPE OGPE 0OGPE 0OGPE 0OGPE OGPE DGG DGG DGG ...

Page 119: ...99 ARM Limited All rights reserved 8 1 Chapter 8 ARM9TDMI AC Characteristics This chapter gives the timing diagrams and timing parameters for the ARM9TDMI ARM9TDMI timing diagrams on page 8 2 ARM9TDMI timing parameters on page 8 14 ...

Page 120: ...ed All rights reserved ARM DDI0145B 8 1 ARM9TDMI timing diagrams Figure 8 1 ARM9TDMI instruction memory interface output timing Figure 8 2 ARM9TDMI instruction address bus enable ǽřŗǱŗǾ ǽŚǱŖǾ 7 7 7 04 7 04 7 10 7 10 7 756 7 756 7 64 7 64 7 7 7 7 ǽřŗǱŗǾ ǽŚǱŖǾ 7 7 ...

Page 121: ...ARM9TDMI AC Characteristics ARM DDI0145B Copyright 1998 1999 ARM Limited All rights reserved 8 3 Figure 8 3 ARM9TDMI instruction memory interface input timing ǽřŗǱŖǾ 7 6 7 7 6 7 7 6 7 ...

Page 122: ...eristics 8 4 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 8 4 ARM9TDMI data memory interface output timing ǽřŗǱŖǾ ǽŚǱŖǾ ǽŗǱŖǾ 7 7 7 7 7 10 7 10 7 756 7 756 7 64 7 64 7 05 7 05 7 06 7 06 7 5 7 5 ...

Page 123: ...1999 ARM Limited All rights reserved 8 5 Figure 8 5 ARM9TDMI data address bus timing Figure 8 6 ARM9TDMI data ABORT and DnMREQ timing Figure 8 7 ARM9TDMI data data bus timing ǽřŗǱŖǾǰ ǽŚǱŖǾǰ ǽŗǱŖǾǰ 7 7 7 6 7 7 7 7 04 7 04 ǽřŗǱŖǾ ǽřŗǱŖǾ 7 6 7 7 2 7 2 7 36 7 3 ...

Page 124: ... 8 6 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 8 8 ARM9TDMI data bus enable Figure 8 9 ARM9TDMI miscellaneous signal timing ǽřŗǱŖǾ 7 7 7 176 7 17 7 6 6 7 6 7 6 7 7 96 7 9 781 6 781 71 6 71 75676 7567 ...

Page 125: ...ARM9TDMI AC Characteristics ARM DDI0145B Copyright 1998 1999 ARM Limited All rights reserved 8 7 Figure 8 10 ARM9TDMI coprocessor interface signal timing ǽŗǱŖǾ ǽŗǱŖǾ 73 6 73 6 7 7 7 7 7 66 7 6 ...

Page 126: ...MI AC Characteristics 8 8 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 8 11 ARM9TDMI JTAG output signals ŗ Ř ǽřǱŖǾ ǽřǱŖǾ ǽřǱŖǾ 77 5 77 77 77 5 7 56 7 56 7730 7730 77 2 77 2 772 772 ...

Page 127: ... Copyright 1998 1999 ARM Limited All rights reserved 8 9 Figure 8 12 ARM9TDMI external boundary scan chain output signals Figure 8 13 ARM9TDMI SDOUTBS to TDO relationship ŗ Ř 7 35 7 3 7 57 7 57 76 5 76 76 76 5 7 5 6 7 5 6 76 1 76 1 77 6 77 6 ...

Page 128: ...TDMI AC Characteristics 8 10 Copyright 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 8 14 ARM9TDMI nTRST to RSTCLKBS relationship Figure 8 15 ARM9TDMI JTAG input signal timing 7 567 77 6 77 ...

Page 129: ... AC Characteristics ARM DDI0145B Copyright 1998 1999 ARM Limited All rights reserved 8 11 Figure 8 16 ARM9TDMI GCLK related debug output timings Ŗ ŗ Ŗ ŗ 7 5 7 7 20 7 20 7 7 75 75 75 75 7 1 7 1 7 76 7 7 7 46 7 4 ...

Page 130: ...ight 1998 1999 ARM Limited All rights reserved ARM DDI0145B Figure 8 17 ARM9TDMI TCK related debug output timings Figure 8 18 ARM9TDMI nTRST to DBGRQI relationship Figure 8 19 ARM9TDMI EDBGRQ to DBGRQI relationship 77 77 5 7 7 7 4 5 7 4 7 4 ...

Page 132: ... ICAPCLKBS PCLKBS rising from TCK falling Tcaps Input setup time to TCK falling EXTEST capture Tchsh CHSD 1 0 CHSE 1 0 hold time from GCLK falling Tchss CHSD 1 0 CHSE 1 0 setup time to GCLK falling Tcomd COMMTX COMMRX output delay Tcomh COMMTX COMMRX output hold time Tdabe Delay from DABE rising to DA 31 0 DnTRANS DnM 4 0 DMAS 1 0 DnRW DLOCK driven valid Tdabh DABORT hold time from GCLK falling Td...

Page 133: ...nput setup time to GCLK falling Tdgid DBGRQI output delay from TCK falling Tdgih DBGRQI output hold time from TCK falling Tdih TDI and TMS hold time from TCK rising Tdis TDI and TMS setup time to TCK rising Tdlkd DLOCK delay from GCLK rising Tdlkh DLOCK hold time from GCLK rising Tdmqd DnMREQ delay from GCLK rising Tdmqh DnMREQ hold time from GCLK rising Tdmrd DMORE delay from GCLK rising Tdmrh DM...

Page 134: ... Tedqd DBGRQI output delay from EDBGRQ changing Tedqh DBGRQI output hold time from EDBGRQ changing Texth EXTERN0 EXTERN1 input hold time from GCLK falling Texts EXTERN0 EXTERN1 input setup time to GCLK falling Tgclkh Minimum GCLK HIGH period Tgclkl Minimum GCLK LOW period Tgekf GCLK falling to ECLK falling delay Tgekr GCLK rising to ECLK rising delay Thivh HIVECS hold time from GCLK rising Thivs H...

Page 135: ...h Interrupt nFIQ nIRQ hold time from GCLK falling Tints Interrupt nFIQ nIRQ setup time to GCLK falling Tinxd INSTREXEC output delay Tinxh INSTREXEC output hold time Tirsd IREG 3 0 SCREG 4 0 output delay from TCK falling Tirsh IREG 3 0 SCREG 4 0 hold time from TCK falling Tisqd ISEQ delay from GCLK rising Tisqh ISEQ hold time from GCLK rising Tisyh ISYNC hold time from GCLK falling Tisys ISYNC setu...

Page 136: ...hold time from GCLK rising Trsts nRESET setup time to GCLK rising Tsdnd SDIN output delay from TCK falling Tsdnh SDIN hold time from TCK falling Tshkf SHCLK1BS SHCLK2BS falling from TCK changing Tshkr SHCLK1BS SHCLK2BS rising from TCK changing Ttapidh TAPID 31 0 hold time to TCK falling Ttapids TAPID 31 0 setup time to TCK falling Ttbe Delay from TBE rising to outputs driven valid Ttbz Delay from ...

Page 137: ... Ttekf TCK falling to ECLK falling delay Ttekr TCK rising to ECLK rising delay Ttoed nTDOEN output delay from TCK falling Ttoeh nTDOEN hold time from TCK falling Ttpmd TAPSM 3 0 output delay from TCK falling Ttpmh TAPSM 3 0 hold time from TCK falling Tunis UNIEN input setup time to GCLK falling Tunih UNIEN input hold time to GCLK falling Table 8 1 ARM9TDMI timing parameters continued Timing parame...

Page 139: ...criptions This chapter lists and describes the ARM9TDMI signals Instruction memory interface signals on page A 2 Data memory interface signals on page A 3 Coprocessor interface signals on page A 5 JTAG and TAP controller signals on page A 6 Debug signals on page A 8 Miscellaneous signals on page A 10 ...

Page 140: ...ruction memory access is not allowed ID 31 0 Input Instruction Data Bus This input bus should be driven with the requested instruction data before the end of phase 2 of GCLK InM 4 0 Output Instruction Mode These signals indicate the current mode of the processor and are in the same form as the mode bits in the CPSR InMREQ Output Not Instruction Memory Request If LOW at the end of GCLK phase 2 the ...

Page 141: ...is an input which when LOW puts the Data Data Bus DD 31 0 into a high impedance state If UNIEN is HIGH this signal is ignored DDEN Output Data Data Bus Output Enabled This signal indicates when the processor is performing a write transfer on the Data Data Bus DD 31 0 DDIN 31 0 Input Data Input Bus This input is used to transfer load data between external memory and the processor It should be drive...

Page 142: ...cle is a read If HIGH it is a write DnTRANS Output Data Not Memory Translate If LOW the next data memory access is to be performed as a user mode access if HIGH the data memory access is to performed as a privileged mode access Note that the data memory access mode may differ from the current processor mode DSEQ Output Data Sequential Address If HIGH at the end of phase 2 any data memory access in...

Page 143: ...nt in the system CHSD 1 should be tied HIGH and CHSD 0 should be tied LOW CHSE 1 0 Input Coprocessor Handshake Execute The handshake signals from the execute stage of the coprocessors pipeline follower Note if no coprocessor is present in the system CHSE 1 should be tied HIGH and CHSE 0 should be tied LOW LATECANCEL Output Coprocessor Late Cancel If HIGH during the first memory cycle of a coproces...

Page 144: ...s output should be left unconnected IR 3 0 Output Tap Controller Instruction Register These four bits reflect the current instruction loaded into the TAP controller instruction register The bits change on the falling edge of TCK when the state machine is in the UPDATE IR state PCLKBS Output Boundary Scan Update Clock This is a TCK2 wide pulse generated when the TAP controller state machine is in t...

Page 145: ...tification The value on this bus will be captured when using the IDCODE instruction on the TAP controller state machine TAPSM 3 0 Output TAP Controller State Machine This bus reflects the current state of the TAP controller state machine These bits change off the rising edge of TCK TCK Input The JTAG clock the test clock TCK1 Output TCK Phase 1 TCK1 is HIGH when TCK is HIGH although there is a sli...

Page 146: ... allows external hardware to halt execution of the processor for debug purposes If HIGH at the end of phase 1 following a data memory request cycle it will cause the ARM9TDMI to enter debug state EDBGRQ Input External Debug Request When driven HIGH this causes the processor to enter debug state after execution of the current instruction completes EXTERN0 Input External Input 0 This is an input to ...

Page 147: ...ignal indicates that the EmbeddedICE macrocell watchpoint unit 1 has matched the conditions currently present on the address data and control buses This signal is independent of the state of the watchpoint s enable control bit TBE Input Test Bus Enable When driven LOW TBE forces the following signals to HIGH impedance DD 31 0 DA 31 0 DLOCK DMAS 1 0 DnM 4 0 DnRW DnTRANS DMORE DnMREQ DSEQ IA 31 0 In...

Page 148: ...r asynchronous depending on the state of ISYNC GCLK Input Clock This clock times all ARM9TDMI memory accesses both data and instruction and internal operations The clock has two distinct phases phase 1 in which GCLK is LOW and phase 2 in which GCLK is HIGH The clock may be stretched indefinitely in either phase to allow access to slow peripherals or memory Alternatively nWAIT may be used with a fr...

Page 149: ... a number of GCLK cycles by driving nWAIT LOW Internally the inverse of nWAIT is ORed with GCLK and must only change when GCLK is HIGH If nWAIT is not used it must be tied HIGH UNIEN Input Unidirectional Enable When HIGH all ARM9TDMI outputs are permanently driven the state of IABE DABE DDBE and TBE is ignored The DDIN 31 0 and DD 31 0 buses form a unidirectional data bus When LOW outputs can go t...

Page 151: ...rnally TCK generated clock 5 26 memory clock 5 26 switching 5 26 switching during debug 5 27 switching during test 5 28 system reset 5 28 coprocessor interface block 4 2 coprocessor handshake signals 4 6 encoding 4 7 states 4 6 coprocessor instructions busy wait 4 6 CDP 4 13 coprocessor 15 MCRs 4 17 during busy wait 4 16 during interrupts 4 16 interlocked MCR 4 11 LDC STC 4 3 MCR MRC 4 9 privilege...

Page 152: ...hing 5 46 EmbeddedICE macrocell 5 1 5 2 5 10 EmbeddedICE watchpoint units debugging 5 11 programming 5 11 testing 5 11 endian effects data transfer 3 11 instruction fetches 3 6 external scan chains 5 21 F five stage pipeline 2 4 H halting data interface 3 3 instruction interface 3 3 processor 3 3 I implementation options 2 2 instruction cycle counts and bus activity 7 2 data bus instruction times ...

Page 153: ... 24 scan chain 3 5 25 serial test and debug 5 12 signals coprocessor interface A 5 data memory interface A 3 debug A 8 instruction memory interface A 2 JTAG and TAP controller A 6 miscellaneous A 10 single stepping 5 47 SYSSPEED bit 5 31 system speed instructions 5 31 system state determining 5 30 scan chain 1 5 30 T TAP controller 5 11 5 12 5 21 TAP state machine 5 26 test clock switching 5 28 sy...

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