VIPER
Detailed hardware description
PC/104 interrupts
The PC/104 interrupts are logically OR’ed together so that any interrupt generated on
the PC/104 interface generates an interrupt input on GPIO1.
The PC/104 interrupting source can be identified by reading the PC104I register located
at offset 0x100000 from CS5 (0x14000000). The register indicates the status of the
interrupt lines at the time the register is read. The relevant interrupt has its
corresponding bit set to ‘1’. The PXA255 is not designed to interface to 8-bit
peripherals, so only the least significant byte from the word contains the data.
PC/104 interrupt register [PC104I]
Byte lane
Most Significant Byte
Least Significant Byte
Bit
15 14 13 12 11 10
9
8
7 6 5 4 3 2 1 0
Field
-
-
-
-
-
-
-
-
IRQ12 IRQ11 IRQ10 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3
Reset
X
X
X
X
X
X
X
X
0 0 0 0 0 0 0 0
R/W
-
-
-
-
-
-
-
-
R/W
Address 0x14100000
PC/104 interrupts IRQ9, IRQ14 and IRQ15 are not used by the VIPER, please
use an alternate interrupt source from the table above.
The ICR Register located at offset 0x100002 from CS5 (0x14000000) must be set-up
correctly for the OS running. The PC/104 interrupts are signaled and handled slightly
differently between embedded Linux / VxWorks and Windows CE .NET.
See the
following relevant subsections for specific PC/104 details for the target OS.
Interrupt configuration and reset register [ICR]
Byte lane
Most Significant Byte
Least Significant Byte
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field
-
-
-
-
-
-
-
-
-
-
-
-
-
R_DIS AUTO_
CLR RETRIG
Reset
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
R/W
-
-
-
-
-
-
-
-
W
Address 0x14100002
© 2004 Arcom Issue H
26
