VIPER
Detailed hardware description
Detailed hardware description
The following section provides a detailed description of the functions provided by the
VIPER. This information may be required during development after you have started
adding extra peripherals or are starting to use some of the embedded features.
VIPER block diagram
The diagram below illustrates the functional organization of the VIPER PC/104 SBC.
PXA255
64MB
SDRAM
1MB
Bootloader
FLASH
16 or 32MB
Silicon Disk
256kB
SRAM
DUART
PL4
COM 1
RS232
Transceiver
RS232
Transceiver
COM 2&3
COM 4
COM5
RS232
Transceiver
RS422/485
Transceiver
PL5
CF Power
Switch
USB Power
Switch
Buffers and
Transceivers
CPLD
Buffers and
Transceivers
A
dd
re
ss
&
D
at
a
C
F
&
P
C
/1
0
4
C
o
ntr
ol
S
ig
na
ls
PC/104 Control
PC/104 Address & Data
CF Address & Data
CF Control
CF_SWITCH
PL11
&
PL12
LAN91C111
PL1
&
PL2
10/100
baseTX
Serial
EEPROM
Transformer
Buffers and
Transceivers
PL9
IN[0:7] / OUT[0:7]
USB Host
Controller
PL7
USB1 & 2
X2
Voltage
Monitor
Triple Reg
Reg
Micropower
DAC
JTAG
X3
Clock
Generation
RTC
X1
PL6
AMP R+L
LINE IN R+L
LINE OUT R+L
MIC IN
AC'97
Codec
Power
Amp
AC'97
Signals
Dual
MOSFET
PL3
BLKEN &
LCDEN
LCD Signals
Reg
POSBIAS /
NEGBIAS
BLKSAFE &
LCDSAFE
LCDEN
VIPER
Control
Control
Control
Control
PL10
PL17
&
LK1
Control
PL16
Jumper Configuration
3.6864MHz
25MHz
14.318MHz
1.8432MHz
6MHz
8MHz
24.576MHz
14.318MHz
32.768kHz
3.3V
1.8V
3.3V
1.06-1.29V
3.3V
5V
VBAT_IN
3.3V
5V
© 2004 Arcom Issue H
13