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BIOS
3.5 Advanced Chipset Features
CAS Latency Time
It allows CAS latency time in HCLKs as 2 or 2.. The system board designer
should set the values in this field, depending on the DRAM installed. Do not
change the values in this field unless you change specifications of the installed
DRAM or CPU.
Setting: 2. (Default), 2.
Interleave Select
It allows you to Use the Interleave Select option to specify how the cache
memory is interleaved.
Setting: LOI (Default), HOI.
XOR BA0
Setting: Disabled (Default), Enabled.
XOR BA1
Setting: Disabled (Default), Enabled.
Summary of Contents for EmModule-621E
Page 1: ...EmModule 621E PC 104 CPU Module User s Manual Version 1 0 2009 11 85 85...
Page 2: ...This page is intentionally left blank...
Page 5: ...Introduction 1 Chapter 1 Introduction Chapter 1 Introduction...
Page 11: ...Introduction 1 10 Board Dimensions Unit mm...
Page 12: ...Introduction Unit mm...
Page 13: ...Installation 2 Chapter 2 Installation Chapter 2 Installation...
Page 29: ...25 BIOS 3 Chapter 3 BIOS Chapter 3 BIOS...
Page 47: ...43 BIOS 3 8 PC Health Status Current CPU Temperature CPU MEM VCore VCC3 5V 12V VBAT V 5VSB...
Page 57: ...53 Appendix 4 Chapter 4 Appendix Chapter 4 Appendix...
Page 64: ...60 Appendix This page is intentionally left blank...