DBS9900 User’s Manual
DBS9900 Operation
3-5
82-28993 Revision 01
Waveform:
5 µs min. pulse width.
May be dependent on module installed.
Overvoltage Protection:
± 20V max.
External Reference for PLL:
Inputs:
One front-panel-mounted SMA connector shared
with channel B external clock input.
Frequency Range:
10 MHz ± 1%.
Amplitude:
± 1V min. to ± 10V max.
Hysteresis:
± 40 mV
Threshold Setting:
Programmable ± 10V, ± 5% with 78 mV resolution.
Impedance: 4
k
Ω
± 5%.
Overvoltage Protection:
± 20V max.
External Trigger:
Inputs:
One for each plug-in module via 2 front-panel-
mounted SMA connectors or via VXI
TTLTRG/ECLTRG lines.
Edge Trigger Modes:
Programmable
Start on rising edge or start on falling edge.
Gated Trigger Modes:
Programmable.
Run when high and stop when low.
Or run when low and stop when high.
Amplitude:
± 1V min. to ± 10V max.
Hysteresis:
± 40 mV
Threshold Setting:
Programmable ± 10V, ± 5% with 78 mV resolution.
Impedance: 4
k
Ω
± 5%.
Trigger to External Clock Setup:
Time:
5 ns min.
Trigger to Internal Clock:
Uncertainty:
<1 clock period.
Overvoltage Protection:
± 20V max.
3.2.4 CONTROL
OUTPUTS
Front-panel-mounted 26 pin “D” connector. Supports DBS 9XX plug-in module
specific functions.
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