DBS9900 User’s Manual
7-22
DBS9900 Clock
82-28993 Revision 01
Table 32 – DAC Codes
DAC Code
Analog Output
FF
+9.921875
81
+78.125mV
80
0V
7F
-78.125mV
01
-9.921875V
00
-10.0V
Table 33 - Trigger
B Threshold Register Map
Base + 0x14
Base + 0X14
Trigger B
Register Map
Default
Data Bus
Function
D[07]
TRGB_THRESH[7] , MSB
Set to 0
R/W
D[06]
TRGB_THRESH[6]
Set to 0
R/W
D[05]
TRGB_THRESH[5]
Set to 0
R/W
D[04]
TRGB_THRESH[4]
Set to 0
R/W
D[03]
TRGB_THRESH[3]
Set to 0
R/W
D[02]
TRGB_THRESH[2]
Set to 0
R/W
D[01]
TRGB_THRESH[1]
Set to 0
R/W
D[00]
TRGB_THRESH[0], LSB
Set to 0
R/W
Table 34 - Time Base Address Map Base + 0x18 (Bh)
Base + 0X18
Time Base Address
FUNCTION
Default
Data Bus
TB CONTROL
D[03]
C[4]
Control bit, set to 1
Set to 0
R/W
D[02]
C[3]
Control bit, set to 0
Set to 0
R/W
D[01]
C[2]
Control bit, set to 1
Set to 0
R/W
D[00]
C[1]
Control bit, set to 1
Set to 0
R/W
Clock A/B and Trigger A/B Threshold Register CONTROL Lines
DAC_WR,
when set low makes the selected DAC latch transparent to data on the data bus until
DAC_WR
goes high. The selected DAC is determined by the
DAC_A1
and
DAC_A0
control
lines. The following table shows MAX506 DAC coding:
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