DBS9900 User’s Manual
7-18
DBS9900 Clock
82-28993 Revision 01
Table 21 - HSDIV Register Base + 0x14
Base + 0X14
HSDIV (PLL 1)
FUNCTION
Default
Data Bus
D[15]
Not Used
Not Used
Set to 0
R/W
D[14]
Not Used
Not Used
Set to 0
R/W
D[13]
Not Used
Not Used
Set to 0
R/W
D[12]
Not Used
Not Used
Set to 0
R/W
D[11]
Not Used
Not Used
Set to 0
R/W
D[10]
Not Used
Not Used
Set to 0
R/W
D[09]
Not Used
Not Used
Set to 0
R/W
D[08]
Not Used
Not Used
Set to 0
R/W
D[07]
Not Used
Not Used
Set to 0
R/W
D[06]
Not Used
Not Used
Set to 0
R/W
D[05]
Not Used
Not Used
Set to 0
R/W
D[04]
Not Used
Not Used
Set to 0
R/W
D[03]
HSDIV [3]
HSDIV, MSB
R = 0
R/W
D[02]
HSDIV [2]
HSDIV
R = 0
R/W
D[01]
HSDIV [1]
HSDIV
R = 0
R/W
D[00]
HSDIV [0]
HSDIV, LSB
R = 0
R/W
Table 22 - HSDIV Address Base + 0x18 (7h)
Base + 0X18
Address
FUNCTION
Default
Data Bus
C=7h
D[03]
C[4]
Control bit, set to 0
Set to 0
R/W
D[02]
C[3]
Control bit, set to 1
Set to 0
R/W
D[01]
C[2]
Control bit, set to 1
Set to 0
R/W
D[00]
C[1]
Control bit, set to 1
Set to 0
R/W
7.11 Clock A Threshold Register
The Clock A Threshold Register
(0x14, Base + 0x18 = 8h)
R/W,
stores the bits needed to set the
Clock A zero crossing thresholds. The byte,
D[07:00]
contains programming bits for clock A zero
crossing. To access this register, the software driver writes to the control bits located in
Base +
0x18 = 8h
of the VXI FPGA. This register instructs the FPGA that the next register writes the
Clock A Threshold Register
at
0x14
in the Time Base address space. The zero crossing of the
clock threshold is set by programming one of four DAC’s in a quad 8 bit DAC to a voltage, from –
10V to +9.921875V in 78.125mV steps. The coding is offset binary and the code map is as
follows:
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