DBS9900 User’s Manual
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DBS9900 User’s Manual
82-28993 Revision 01
6.12
JTAG Programming Register............................................................................................................................. 6-11
7
Clock................................................................................................................................ 7-1
7.1
Channel A/B Clock Selection: ............................................................................................................................. 7-1
7.2
Frequency Synthesizer: ........................................................................................................................................ 7-1
7.3
Time Base Divider: .............................................................................................................................................. 7-1
7.4
Program Sequence:............................................................................................................................................... 7-1
7.4.1
Sample
Rate
Calculation:
7-2
7.5
Phase Lock Loop.................................................................................................................................................. 7-3
7.6
LMX2306 Communications port ......................................................................................................................... 7-3
7.6.1
TIME BASE RESET
7-4
7.6.2
PLL
R-COUNTER
7-4
7.6.3
PLL
N-COUNTER
7-6
7.6.4
PLL FUNCTION LATCH
7-8
7.7
Clock Control Register....................................................................................................................................... 7-11
7.7.1
Clock
Control
Description
7-12
7.8
LSDIV Low Speed Divider Register.................................................................................................................. 7-12
7.9
Time Base Control Register ............................................................................................................................... 7-15
7.9.1
TIME BASE CLOCK Inputs
7-16
7.9.2
D[07:05]
MISCELANEOUS
Control
bits 7-16
7.10
High Speed Divider Data Register ..................................................................................................................... 7-17
7.11
Clock A Threshold Register............................................................................................................................... 7-18
7.12
Clock B Threshold Register ............................................................................................................................... 7-19
7.13
Trigger A Threshold Register ............................................................................................................................ 7-20
7.14
Trigger B Threshold Register............................................................................................................................. 7-21
8
Programming Examples: ............................................................................................... 8-1
8.1
Clock Programming Example: ............................................................................................................................. 8-1
9
Time Base Truth Table:.................................................................................................. 9-1
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