Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 893 / 1192

ADSP-214xx SHARC Processor Hardware Reference A-67
Registers Reference
Pulse Width Modulation Registers
The following registers control the operation of pulse width modulation
on the processor.
Global Control Register (PWMGCTL)
This register enables or disables the four PWM groups, in any combina-
tion and provides synchronization across the groups. Note that disable bits
have higher priority over the enable bits (bit 1 higher as bit 0 and so on).
This 16-bit register is shown in
Figure A-31 .
For the PWM global control register, the traditional read-modify-write
operations to disable the PWM group have changed. The action is to
directly write—this simplifies the enable/disable of the PWM groups and
can be done with fewer instructions. For example, instead of the following
code:
ustat3 = dm(PWMGCTL); /* PWM General Control Register */
bit set ustat3 PWM_DIS0; /* disables group 0 */
dm(PWMGCTL) = ustat3;
Use:
ustat3 = PWM_DIS0;
dm(PWMGCTL) = ustat3;
Figure A-30. MTMCTL Register (RW)
MTMDMA0ACT (WO)
MTMDEN
MTM DMA Ena b le
0=Disa b le
1=Ena b le
Memory Write DMA S tatus
MTMFLU S H (WOC)
1=Flush the FIFO and reset the
read/write pointers
MTMDMA1ACT
Memory Read DMA S tatus
3 1 3 0 29 2 8 27 26 25 24 2 3 22 21 20 19 1 8 17 16
0 9 8 3 7 5 6 4 2 1 14 12 11 10 1 3 15
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