Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 815 / 1192

ADSP-214xx SHARC Processor Hardware Reference 23-33
System Design
High Frequency Design
Because the processor must be able to operate at very high clock frequen-
cies, signal integrity and noise problems must be considered for circuit
board design and layout. The following sections discuss these topics and
suggest various techniques to use when designing and debugging target
systems.
Circuit Board Design
The processor is a CMOS device. It has input conditioning circuits which
simplify system design by filtering or latching input signals to reduce sus-
ceptibility to glitches or reflections.
The following sections describe why these circuits are needed and their
effect on input signals.
Clock Input Specifications and Jitter
The clock input signal must be free of ringing and jitter. Clock jitter can
easily be introduced into a system where more than one clock frequency
exists. Jitter should be kept to an absolute minimum. High frequency jit-
ter on the clock to the processor may result in abbreviated internal cycles.
Keep the portions of the system that operate at different frequencies as
physically separate as possible. The clock supplied to the processor must
have a maximum rise time and must meet or exceed a high and low voltage
of V
IH
and V
IL
, respectively.
Refer to the appropriate product data sheet for exact specifications.
www.BDTIC.com/ADI