Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 441 / 1192

ADSP-214xx SHARC Processor Hardware Reference 9-27
Digital Application/Digital Peripheral Interfaces
signal present at the corresponding pin buffer input (
PBxx_I
) is driven
off-chip as an output. When a pin buffer enable is cleared (= 0), the signal
present at the corresponding pin buffer input is ignored.
The pin enable control registers activate the drive buffer for each of the
DAI/DPI pins. When the pins are not enabled (driven), they can be used
as inputs.
Though peripherals are capable of operating bi-directionally, it is not
required that all peripheral’s _I and _O signals should be connected to the
pin buffer. If the system design only uses a signal in one direction, it is
simpler to connect the pin buffer enable pin directly to high or low as
appropriate.
Furthermore, signals in the SRU other than the pin buffer enable signal
(which is generated by the peripheral) may be routed to the pin buffer
enable input. For example, an outside source may be used to ‘gate’ a pin
buffer output by controlling the corresponding pin buffer enable.
Miscellaneous Signals
DAI group E or DPI group C connections are slightly different from the
others in that the inputs and outputs being routed vary considerably in
function. This group routes control signals and provides a means of con-
necting signals between groups.
For the DAI, the
MISCAx_I
signals appear as inputs in group E, but do not
directly feed any peripheral. Rather, the
MISCAx_O
signals reappear as out-
puts in group F.
For the DPI, the
MISCBx_I
signals appear as inputs in group A, but do not
directly feed any peripheral. Rather, the
MISCBx_O
signals reappear as out-
puts in group C.
Additional connections among groups provide a surprising amount of
utility. Since the output groups F and C dictate pin direction, these few
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