UG-1533
Evaluation Board User Guide
Rev. 0 | Page 4 of 31
EVALUATION BOARD HARDWARE
SETTING UP THE EVAL-ADAQ4003FMCZ
EVALUATION KIT
Figure 2 shows the simplified
block
diagram. Figure 33 to Figure 34 show the EV-ADAQ4003PMDZ
board schematics, which consists of the
(U4 and U7), the
(U6). The EV-ADAQ4003PMDZ is a flexible design
that enables the user to select components in addition to
operate from an adjustable bench top power supply.
) BOARD
The EV-ADAQ4003PMDZ evaluation kit uses a serial port
interface (SPI) and requires the system demonstration platform
(SDP-H1) to capture the data via a graphic user interface (GUI)
(see Figure 1). The SDP-H1 requires power from a 12 V wall
adapter. The SDP-H1 has a Xilinx® Spartan®-6 and an
processor with connectivity to the PC through a USB 2.0 high
speed port.
The SDP-H1 has an FMC low pin count connector with full
differential low voltage differential signaling (LVDS) and
singled-ended, low voltage, complementary metal-oxide
semiconductor (CMOS) support. The SDP-H1 also has a
120-pin connector that exposes the Blackfin® processor
peripherals. This connector provides a configurable serial,
parallel I
2
C and SPI and general-purpose input/output (GPIO)
communication lines to the attached daughter board.
–15V
–15V
+15V
EVAL-SDP-CH1Z
160-PIN
FMC CONNECTOR
12V
12V
WALL WART
USB PORT
POWER
SUPPLY
CIRCUITRY
ADSP-BF527
SPARTAN-6
FPGA
XC6SLX25
FMC TO PMOD
INTERPOSER
BOARD
EVAL-PMD-IB1Z
EVALUATION BOARD FOR THE µMODULE DATA ACQUISITION SYSTEM
IN+
OUT+
ADAQ4003
SCK
SDO
CNV
VIO
SDI
REF
VDD
–15V
+15V
+15V
+15V
+15.5V
–15.5V
VIN+
VIN–
ADA4898-1
ADA4898-1
GND
ADR4550
SPI
INTERFACE
+3.3V
LT3032
LT3023
ADP5070
VS–
VS+
OUT–
R1K1+
R1K+
R1K–
R1K1–
IN–
+1.8V
+5.5V
–15V
GND
(OPTIONAL)
+15V
EVAL-ADAQ4003FMCZ
202
1
1-
002
Figure 2. Simplified Evaluation Board Block Diagram
