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Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

The Analog Devices Blackfin ADSP-BF537 is a cutting-edge processor renowned for its exceptional performance and versatility. Unlock the full potential of this remarkable hardware by downloading the comprehensive and free Hardware Reference Manual from our website. All the information you need is just a click away.

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Programming Model

10-28

ADSP-BF537 Blackfin Processor Hardware Reference

 

Programming Model

The following sections describe the SPI programming model.

Beginning and Ending an SPI Transfer

The start and finish of an SPI transfer depend on whether the device is 
configured as a master or a slave, whether the 

CPHA

 mode is selected, and 

whether the transfer initiation mode (

TIMOD

) is selected. For a master SPI 

with 

CPHA

 

= 0

, a transfer starts when either 

SPI_TDBR

 is written to or 

SPI_RDBR

 is read, depending on 

TIMOD

. At the start of the transfer, the 

enabled slave select outputs are driven active (low). However, the 

SCK

 sig-

nal remains inactive for the first half of the first cycle of 

SCK

. For a slave 

with 

CPHA

 

= 0

, the transfer starts as soon as the 

SPISS

 input goes low.

For 

CPHA

 

= 1

, a transfer starts with the first active edge of 

SCK

 for both 

slave and master devices. For a master device, a transfer is considered fin-
ished after it sends the last data and simultaneously receives the last data 
bit. A transfer for a slave device ends after the last sampling edge of 

SCK

.

The 

RXS

 bit defines when the receive buffer can be read. The 

TXS

 bit 

defines when the transmit buffer can be filled. The end of a single word 
transfer occurs when the 

RXS

 bit is set, indicating that a new word has just 

been received and latched into the receive buffer, 

SPI_RDBR

. For a master 

SPI, 

RXS

 is set shortly after the last sampling edge of 

SCK

. For a slave SPI, 

RXS

 is set shortly after the last 

SCK

 edge, regardless of 

CPHA

 or 

CPOL

. The 

latency is typically a few 

SCLK

 cycles and is independent of 

TIMOD

 and the 

baud rate. If configured to generate an interrupt when 

SPI_RDBR

 is full 

(

TIMOD = 00

), the interrupt goes active one 

SCLK

 cycle after 

RXS

 is set. 

When not relying on this interrupt, the end of a transfer can be detected 
by polling the 

RXS

 bit.

To maintain software compatibility with other SPI devices, the 

SPIF

 bit is 

also available for polling. This bit may have a slightly different behavior 
from that of other commercially available devices. For a slave device, 

SPIF

 

Summary of Contents for Blackfin ADSP-BF537

Page 1: ...ADSP BF537 Blackfin Processor Hardware Reference Revision 2 0 December 2005 Part Number 82 000555 01 Analog Devices Inc One Technology Way Norwood Mass 02062 9106 a ...

Page 2: ...e and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo Blackfin the Blackfin logo CrossCore EZ KIT Lite SHARC TigerSHAR...

Page 3: ...lvii Supported Processors xlviii Product Information xlix MyAnalog com xlix Processor Product Information xlix Related Documents l Online Technical Documentation li Accessing Documentation From VisualDSP lii Accessing Documentation From Windows lii Accessing Documentation From the Web liii Printed Manuals liii VisualDSP Documentation Set liii Hardware Tools Manuals liv Processor Manuals liv Data S...

Page 4: ...I O Memory Space 1 7 DMA Support 1 7 External Bus Interface Unit 1 9 PC133 SDRAM Controller 1 9 Asynchronous Controller 1 9 Ports 1 10 General Purpose I O GPIO 1 10 Two Wire Interface 1 11 Controller Area Network 1 12 Ethernet MAC 1 14 Parallel Peripheral Interface 1 14 SPORT Controllers 1 16 Serial Peripheral Interface SPI Port 1 18 Timers 1 18 UART Ports 1 19 Real Time Clock 1 20 Watchdog Timer ...

Page 5: ... 1 24 Hibernate State 1 24 Voltage Regulation 1 24 Boot Modes 1 25 Instruction Set Description 1 27 Development Tools 1 29 CHIP BUS HIERARCHY Overview 2 1 Interface Overview 2 3 Internal Clocks 2 4 Core Bus Overview 2 4 Peripheral Access Bus PAB 2 6 PAB Arbitration 2 6 PAB Agents Masters Slaves 2 6 PAB Performance 2 7 DMA Access Bus DAB DMA Core Bus DCB DMA External Bus DEB 2 8 DAB Arbitration 2 8...

Page 6: ...M 3 5 L1 Data SRAM 3 7 L1 Data Cache 3 8 Boot ROM 3 8 External Memory 3 8 Processor Specific MMRs 3 8 DMEM_CONTROL Register 3 9 DTEST_COMMAND Register 3 10 SYSTEM INTERRUPTS Overview 4 1 Features 4 1 Interfaces 4 2 Description of Operation 4 2 Events and Sequencing 4 2 System Peripheral Interrupts 4 7 Programming Model 4 14 System Interrupt Initialization 4 14 System Interrupt Processing Summary 4...

Page 7: ...s 4 23 DIRECT MEMORY ACCESS Overview and Features 5 1 DMA Controller Overview 5 5 External Interfaces 5 6 Internal Interfaces 5 6 Peripheral DMA 5 7 Memory DMA 5 9 Handshaked Memory DMA Mode 5 11 Modes of Operation 5 12 Register based DMA Operation 5 12 Stop Mode 5 13 Autobuffer Mode 5 14 Two Dimensional DMA Operation 5 14 Examples of Two Dimensional DMA 5 15 Descriptor based DMA Operation 5 16 De...

Page 8: ... 28 DMA Receive 5 30 Stopping DMA Transfers 5 31 DMA Errors Aborts 5 32 DMA Control Commands 5 34 Restrictions 5 38 Transmit Restart or Finish 5 38 Receive Restart or Finish 5 39 Handshaked Memory DMA Operation 5 40 Pipelining DMA Requests 5 41 HMDMA Interrupts 5 43 DMA Performance 5 44 DMA Throughput 5 45 Memory DMA Timing Details 5 48 Static Channel Prioritization 5 48 Temporary DMA Urgency 5 50...

Page 9: ...escriptor Queue Using Minimal Interrupts 5 63 Software Triggered Descriptor Fetches 5 65 DMA Registers 5 67 DMA Channel Registers 5 68 DMAx_PERIPHERAL_MAP MDMA_yy_PERIPHERAL_MAP Registers 5 71 DMAx_CONFIG MDMA_yy_CONFIG Registers 5 74 DMAx_IRQ_STATUS MDMA_yy_IRQ_STATUS Registers 5 78 DMAx_START_ADDR MDMA_yy_START_ADDR Registers 5 82 DMAx_CURR_ADDR MDMA_yy_CURR_ADDR Registers 5 83 DMAx_X_COUNT MDMA...

Page 10: ...6 HMDMA Registers 5 98 HMDMAx_CONTROL Registers 5 99 HMDMAx_BCINIT Registers 5 101 HMDMAx_BCOUNT Registers 5 101 HMDMAx_ECOUNT Registers 5 102 HMDMAx_ECINIT Registers 5 103 HMDMAx_ECURGENT Registers 5 104 HMDMAx_ECOVERFLOW Registers 5 104 DMA Traffic Control Registers 5 105 DMA_TC_PER Register 5 105 DMA_TC_CNT Register 5 106 Programming Examples 5 107 Register Based 2D Memory DMA 5 107 Initializin...

Page 11: ...d Grant 6 8 Operation 6 8 AMC Overview and Features 6 9 Features 6 9 Asynchronous Memory Interface 6 9 Asynchronous Memory Address Decode 6 10 AMC Pin Description 6 10 AMC Description of Operation 6 11 Avoiding Bus Contention 6 11 External Access Extension 6 12 AMC Functional Description 6 12 Programmable Timing Characteristics 6 12 Asynchronous Reads 6 13 Asynchronous Writes 6 14 Adding External ...

Page 12: ...s 6 25 SDRAM Configurations Supported 6 26 SDRAM External Bank Size 6 27 SDC Address Mapping 6 27 Internal SDRAM Bank Select 6 29 Parallel Connection of SDRAMs 6 29 SDC Interface Overview 6 30 SDC Pin Description 6 30 SDRAM Performance 6 31 SDC Description of Operation 6 32 Definition of SDRAM Architecture Terms 6 32 Refresh 6 32 Row Activation 6 32 Column Read Write 6 32 Row Precharge 6 33 Intern...

Page 13: ...34 Mode Register Set MRS command 6 34 Extended Mode Register Set EMRS command 6 34 Bank Activate command 6 35 Read Write command 6 35 Precharge Precharge All Command 6 35 Auto refresh command 6 35 Enter Self Refresh Mode 6 35 Exit Self Refresh Mode 6 36 SDC Timing Specs 6 36 tMRD 6 36 tRAS 6 36 CL 6 37 tRCD 6 37 tRRD 6 37 tWR 6 37 tRP 6 38 tRC 6 38 tRFC 6 38 ...

Page 14: ...44 Changing System Clock During Runtime 6 44 Changing Power Management During Runtime 6 46 Deep Sleep Mode 6 46 Hibernate State 6 46 Shared SDRAM 6 46 SDC Commands 6 47 Mode Register Set Command 6 49 Extended Mode Register Set Command Mobile SDRAM 6 50 Bank Activation Command 6 51 Read Write Command 6 51 Write Command With Data Mask 6 51 Single Precharge Command 6 52 Precharge All Command 6 52 Aut...

Page 15: ...RAM System Block Diagrams 6 58 SDC Register Definitions 6 60 EBIU_SDRRC Register 6 60 EBIU_SDBCTL Register 6 62 Using SDRAMs With Systems Smaller than 16M byte 6 65 EBIU_SDGCTL Register 6 67 EBIU_SDSTAT Register 6 78 SDC Programming Examples 6 79 PARALLEL PERIPHERAL INTERFACE Overview 7 1 Features 7 1 Interface Overview 7 2 Description of Operation 7 5 Functional Description 7 6 ITU R 656 Modes 7 ...

Page 16: ...cs 7 16 1 2 or 3 External Frame Syncs 7 16 2 or 3 Internal Frame Syncs 7 17 Data Output TX Modes 7 18 No Frame Syncs 7 18 1 or 2 External Frame Syncs 7 18 1 2 or 3 Internal Frame Syncs 7 19 Frame Synchronization in GP Modes 7 20 Modes With Internal Frame Syncs 7 20 Modes With External Frame Syncs 7 21 Programming Model 7 23 DMA Operation 7 23 PPI Registers 7 26 PPI_CONTROL Register 7 26 PPI_STATUS...

Page 17: ...Clocking 8 4 Pins 8 5 Internal Interface 8 6 Power Management 8 7 Description of Operation 8 7 Protocol 8 7 MII Management Interface 8 7 Operation 8 10 MII Management Interface Operation 8 10 Receive DMA Operation 8 11 Frame Reception and Filtering 8 13 RX Automatic Pad Stripping 8 17 RX DMA Data Alignment 8 18 RX DMA Buffer Structure 8 18 RX Frame Status Buffer 8 19 RX Frame Status Classification...

Page 18: ... Direction Errors 8 30 Power Management 8 31 Ethernet Operation in the Sleep State 8 33 Magic Packet Detection 8 34 Remote Wake up Filters 8 35 Ethernet Event Interrupts 8 38 RX TX Frame Status Interrupt Operation 8 42 RX Frame Status Register Operation at Startup and Shutdown 8 43 TX Frame Status Register Operation at Startup and Shutdown 8 43 MAC Management Counters 8 43 Programming Model 8 46 C...

Page 19: ...Register Group 8 63 EMAC_OPMODE Register 8 64 EMAC_ADDRLO Register 8 70 EMAC_ADDRHI Register 8 71 EMAC_HASHLO and EMAC_HASHHI Registers 8 72 EMAC_STAADD Register 8 76 EMAC_STADAT Register 8 78 EMAC_FLC Register 8 78 EMAC_VLAN1 and EMAC_VLAN2 Registers 8 80 EMAC_WKUP_CTL Register 8 81 EMAC_WKUP_FFMSK0 EMAC_WKUP_FFMSK1 EMAC_WKUP_FFMSK2 and EMAC_WKUP_FFMSK3 Registers 8 84 EMAC_WKUP_FFCMD Register 8 8...

Page 20: ...E Register 8 107 EMAC_TX_STAT Register 8 108 EMAC_TX_STKY Register 8 112 EMAC_TX_IRQE Register 8 114 EMAC_MMC_RIRQS Register 8 115 EMAC_MMC_RIRQE Register 8 117 EMAC_MMC_TIRQS Register 8 119 EMAC_MMC_TIRQE Register 8 121 MAC Management Counter Registers 8 123 EMAC_MMC_CTL Register 8 124 Programming Examples 8 125 Ethernet Structures 8 126 MAC Address Setup 8 129 PHY Control Routines 8 130 CAN MODU...

Page 21: ... 9 15 Auto Transmission 9 15 Receive Operation 9 15 Data Acceptance Filter 9 18 Remote Frame Handling 9 19 Watchdog Mode 9 19 Time Stamps 9 20 Temporarily Disabling Mailboxes 9 21 Functional Operation 9 22 CAN Interrupts 9 23 Mailbox Interrupts 9 23 Global Interrupt 9 24 Event Counter 9 26 CAN Warnings and Errors 9 28 Programmable Warning Limits 9 28 CAN Error Handling 9 28 Error Frames 9 29 Error...

Page 22: ...Global Registers 9 42 CAN_CONTROL Register 9 43 CAN_STATUS Register 9 44 CAN_DEBUG Register 9 45 CAN_CLOCK Register 9 45 CAN_TIMING Register 9 46 CAN_INTR Register 9 46 CAN_GIM Register 9 47 CAN_GIS Register 9 47 CAN_GIF Register 9 48 Mailbox Mask Registers 9 48 CAN_AMxx Registers 9 49 CAN_MBxx_ID1 Registers 9 53 CAN_MBxx_ID0 Registers 9 55 CAN_MBxx_TIMESTAMP Registers 9 57 CAN_MBxx_LENGTH Registe...

Page 23: ...73 CAN_TRSx Registers 9 74 CAN_TRRx Registers 9 75 CAN_AAx Register 9 76 CAN_TAx Register 9 77 CAN_MBTD Register 9 78 CAN_RFHx Registers 9 78 CAN_MBIMx Registers 9 79 CAN_MBTIFx Registers 9 80 CAN_MBRIFx Registers 9 81 Universal Counter Registers 9 82 CAN_UCCNF Register 9 83 CAN_UCCNT Register 9 84 CAN_UCRC Register 9 84 Error Registers 9 85 CAN_CEC Register 9 85 CAN_ESR Register 9 85 CAN_EWR Regi...

Page 24: ...rface 10 4 Serial Peripheral Interface Clock Signal SCK 10 4 Master Out Slave In MOSI 10 5 Master In Slave Out MISO 10 5 Serial Peripheral Interface Slave Select Input Signal 10 6 Serial Peripheral Interface Slave Select Enable Output Signals 10 7 Slave Select Inputs 10 10 Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems 10 10 Internal Interfaces 10 12 DMA Functionality 10 12 SPI Transmit...

Page 25: ...sion Error TXCOL 10 22 Interrupt Output 10 23 Functional Description 10 23 Master Mode Operation 10 24 Transfer Initiation From Master Transfer Modes 10 25 Slave Mode Operation 10 26 Slave Ready for a Transfer 10 27 Programming Model 10 28 Beginning and Ending an SPI Transfer 10 28 Master Mode DMA Operation 10 30 Slave Mode DMA Operation 10 32 SPI Registers 10 40 Programming Examples 10 45 Core Ge...

Page 26: ...Transfer 10 51 TWO WIRE INTERFACE CONTROLLER Overview 11 1 Interface Overview 11 2 External Interface 11 3 Serial Clock signal SCL 11 3 Serial data signal SDA 11 4 TWI Pins 11 4 Internal Interfaces 11 5 Description of Operation 11 6 TWI Transfer Protocols 11 6 Clock Generation and Synchronization 11 6 Bus Arbitration 11 7 Start and Stop Conditions 11 8 General Call Support 11 9 Fast Mode 11 10 TWI...

Page 27: ...ode Clock Setup 11 22 Master Mode Transmit 11 22 Master Mode Receive 11 23 Repeated Start Condition 11 24 Transmit Receive Repeated Start Sequence 11 24 Receive Transmit Repeated Start Sequence 11 26 Programming Model 11 28 Register Descriptions 11 30 TWI_CONTROL Register 11 30 TWI_CLKDIV Register 11 30 TWI_SLAVE_CTL Register 11 31 TWI_SLAVE_ADDR Register 11 33 TWI_SLAVE_STAT Register 11 33 TWI_MA...

Page 28: ...V_DATA8 Register 11 45 TWI_RCV_DATA16 Register 11 46 Programming Examples 11 47 Master Mode Setup 11 47 Slave Mode Setup 11 52 Electrical Specifications 11 59 SPORT CONTROLLERS Overview 12 1 Features 12 2 Interface Overview 12 3 SPORT Pin Line Terminations 12 9 Description of Operation 12 10 SPORT Operation 12 10 SPORT Disable 12 10 Setting SPORT Modes 12 11 Stereo Serial Operation 12 12 Multichan...

Page 29: ...t for H 100 Standard Protocol 12 25 2X Clock Recovery Control 12 26 Functional Description 12 26 Clock and Frame Sync Frequencies 12 26 Maximum Clock Rate Restrictions 12 28 Word Length 12 28 Bit Order 12 28 Data Type 12 28 Companding 12 29 Clock Signal Options 12 30 Frame Sync Options 12 30 Framed Versus Unframed 12 31 Internal Versus External Frame Syncs 12 32 Active Low Versus Active High Frame...

Page 30: ... Registers 12 47 SPORTx_RCR1 and SPORTx_RCR2 Registers 12 52 Data Word Formats 12 57 SPORTx_TX Register 12 58 SPORTx_RX Register 12 60 SPORTx_STAT Register 12 63 SPORTx_TCLKDIV and SPORTx_RCLKDIV Registers 12 64 SPORTx_TFSDIV and SPORTx_RFSDIV Register 12 65 SPORTx_MCMCn Registers 12 66 SPORTx_CHNL Register 12 67 SPORTx_MRCSn Registers 12 68 SPORTx_MTCSn Registers 12 70 Programming Examples 12 72 ...

Page 31: ...RT Transfer Protocol 13 4 UART Transmit Operation 13 5 UART Receive Operation 13 6 IrDA Transmit Operation 13 8 IrDA Receive Operation 13 9 Interrupt Processing 13 10 Bit Rate Generation 13 12 Autobaud Detection 13 13 Programming Model 13 15 Non DMA Mode 13 15 DMA Mode 13 17 Mixing Modes 13 18 UART Registers 13 19 UARTx_LCR Registers 13 21 UARTx_MCR Registers 13 23 UARTx_LSR Registers 13 24 UARTx_...

Page 32: ... Programming Examples 13 32 GENERAL PURPOSE PORTS Overview 14 1 Features 14 2 Interface Overview 14 3 External Interface 14 4 Port F Structure 14 4 Port G Structure 14 5 Port H Structure 14 6 Port J Structure 14 7 Internal Interfaces 14 8 Performance Throughput 14 9 Description of Operation 14 9 Operation 14 9 General Purpose I O Modules 14 10 GPIO Interrupt Processing 14 14 Programming Model 14 2...

Page 33: ...ocessing 15 8 Illegal States 15 10 Modes of Operation 15 13 Pulse Width Modulation PWM_OUT Mode 15 13 Output Pad Disable 15 15 Single Pulse Generation 15 15 Pulse Width Modulation Waveform Generation 15 16 PULSE_HI Toggle Mode 15 18 Externally Clocked PWM_OUT 15 22 Using PWM_OUT Mode With the PPI 15 23 Stopping the Timer in PWM_OUT Mode 15 23 Pulse Width Count and Capture WDTH_CAP Mode 15 26 Autob...

Page 34: ...OUNTER Registers 15 45 TIMERx_PERIOD and TIMERx_WIDTH Registers 15 46 Summary 15 50 Programming Examples 15 52 CORE TIMER Overview and Features 16 1 Timer Overview 16 1 External Interfaces 16 2 Internal Interfaces 16 2 Description of Operation 16 2 Interrupt Processing 16 3 Core Timer Registers 16 4 TCNTL Register 16 4 TCOUNT Register 16 5 TPERIOD Register 16 6 TSCALE Register 16 7 Programming Exa...

Page 35: ... Operation 17 3 Register Definitions 17 5 WDOG_CNT Register 17 5 WDOG_STAT Register 17 6 WDOG_CTL Register 17 7 Programming Examples 17 9 REAL TIME CLOCK Overview 18 1 Interface Overview 18 2 Description of Operation 18 3 RTC Clock Requirements 18 4 Prescaler Enable 18 4 RTC Programming Model 18 6 Register Writes 18 7 Write Latency 18 8 Register Reads 18 9 Deep Sleep 18 9 Event Flags 18 10 ...

Page 36: ...Register 18 21 RTC_ALARM Register 18 22 RTC_PREN Register 18 22 Programming Examples 18 23 Enable RTC Prescaler 18 23 RTC Stopwatch For Exiting Deep Sleep Mode 18 24 RTC Alarm to Come Out of Hibernate State 18 26 SYSTEM RESET AND BOOTING Reset and Powerup 19 2 Hardware Reset 19 2 System Reset Configuration Register SYSCR 19 4 Software Resets and Watchdog Timer 19 5 Software Reset Register SWRST 19...

Page 37: ...ing a Different Application 19 27 Determining Boot Stream Start Addresses 19 29 Specific Blackfin Boot Modes 19 34 Bypass No Boot Mode BMODE 000 19 34 8 Bit Flash PROM Boot BMODE 001 19 36 16 Bit Flash PROM Boot BMODE 001 19 40 SPI Master Mode Boot from SPI Memory BMODE 011 19 42 SPI Memory Detection Routine 19 44 SPI Slave Mode Boot From SPI Host BMODE 100 19 48 TWI Master Boot Mode BMODE 101 19 ...

Page 38: ...nt Controller States 20 8 Full On Mode 20 9 Active Mode 20 9 Sleep Mode 20 9 Deep Sleep Mode 20 10 Hibernate State 20 11 Operating Mode Transitions 20 11 Programming Operating Mode Transitions 20 14 PLL Programming Sequence 20 15 PLL Programming Sequence Continues 20 17 Dynamic Supply Voltage Control 20 18 Power Supply Management 20 18 Controlling the Voltage Regulator 20 19 Changing Voltage 20 21...

Page 39: ...g Hibernate State 20 32 Changing Internal Voltage Levels 20 33 SYSTEM DESIGN Pin Descriptions 21 1 Managing Clocks 21 1 Managing Core and System Clocks 21 2 Configuring and Servicing Interrupts 21 2 Semaphores 21 2 Example Code for Query Semaphore 21 3 Data Delays Latencies and Throughput 21 4 Bus Priorities 21 4 External Memory Design Issues 21 5 Example Asynchronous Memory Interfaces 21 5 Avoidi...

Page 40: ...c Power Management Registers A 2 System Reset and Interrupt Control Registers A 2 Watchdog Timer Registers A 3 Real Time Clock Registers A 4 UART0 Controller Registers A 4 SPI Controller Registers A 5 Timer Registers A 6 Ports Registers A 8 SPORT0 Controller Registers A 12 SPORT1 Controller Registers A 14 External Bus Interface Unit Registers A 16 DMA Memory DMA Control Registers A 17 PPI Register...

Page 41: ...mer Registers A 36 Processor Specific Memory Registers A 36 TEST FEATURES JTAG Standard B 1 Boundary Scan Architecture B 2 Instruction Register B 4 Public Instructions B 5 EXTEST Binary Code 00000 B 5 SAMPLE PRELOAD Binary Code 10000 B 6 BYPASS Binary Code 11111 B 6 Boundary Scan Register B 6 GLOSSARY INDEX ...

Page 42: ...Contents xlii ADSP BF537 Blackfin Processor Hardware Reference ...

Page 43: ...the ADSP BF53x BF56x Blackfin Processor Programming Reference For timing electrical and package speci fications see the ADSP BF534 Embedded Processor Data Sheet or the ADSP BF536 ADSP BF537 Embedded Processor Data Sheet Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors This manual assumes that the audience has a working knowledge ...

Page 44: ...peripheral interrupts including setup and clearing of interrupt requests Chapter 5 Direct Memory Access Describes the peripheral DMA and Memory DMA controllers Includes performance software management of DMA and DMA errors Chapter 6 External Bus Interface Unit Describes the External Bus Interface Unit of the processor The chapter also discusses the asynchronous memory interface the SDRAM controlle...

Page 45: ...ety of SPI compatible peripheral devices Chapter 11 Two Wire Interface Controller Describes the Two Wire Interface TWI controller which allows a device to interface to an Inter IC bus as specified by the Philips I2 C Bus Specification version 2 1 dated January 2000 Chapter 12 SPORT Controllers Describes the two independent synchronous Serial Port Control lers SPORT0 and SPORT1 that provide an I O ...

Page 46: ...apter 19 System Reset and Booting Describes the booting methods booting process and specific boot modes for the processor Chapter 20 Dynamic Power Management Describes the clocking including the PLL and the dynamic power management controller Chapter 21 System Design Describes how to use the processor as part of an overall system It includes information about bus timing and latency numbers sema ph...

Page 47: ...ision 2 0 of the ADSP BF537 Blackfin Processor Hardware Ref erence Peripheral chapters have been expanded and reorganized and modifications and corrections based on errata reports against the Prelimi nary version of this manual have been made Technical or Customer Support You can reach Analog Devices Inc Customer Support in the following ways Visit the Embedded Processing and DSP products Web site...

Page 48: ...s to a family of 16 bit embedded processors VisualDSP currently supports the following Blackfin families ADSP BF53x and ADSP BF56x TigerSHARC ADSP TSxxx Processors The name TigerSHARC refers to a family of floating point and fixed point 8 bit 16 bit and 32 bit processors VisualDSP currently supports the following TigerSHARC families ADSP TS101 and ADSP TS20x SHARC ADSP 21xxx Processors The name SH...

Page 49: ...roducts you are interested in You can also choose to receive weekly e mail notifications containing updates to the Web pages that meet your interests MyAnalog com provides access to books application notes data sheets code examples and more Registration Visit www myanalog com to sign up Click Register to use MyAnalog com Registration takes about five minutes and serves as a means to select the inf...

Page 50: ...he FTP Web site at ftp ftp analog com or ftp 137 71 25 69 ftp ftp analog com Related Documents The following publications that describe the ADSP BF534 ADSP BF536 and ADSP BF537 Blackfin processor and related proces sors can be ordered from any Analog Devices sales office ADSP BF53x ADSP BF56x Blackfin Processor Programming Reference ADSP BF536 ADSP BF537 Blackfin Embedded Processor Data Sheet ADSP...

Page 51: ...library and Flexible License Manager FlexLM network license manager software documentation You can easily search across the entire VisualDSP documentation set for any topic of interest For easy printing supplementary PDF files of most manuals are also provided Each documentation file type is described as follows File Description CHM Help system files and manuals in Help format HTM or HTML Dinkum A...

Page 52: ...from context sensitive user interface items tool bar buttons menu commands and windows Accessing Documentation From Windows In addition to any shortcuts you may have constructed there are many ways to open VisualDSP online Help or the supplementary documenta tion from Windows Help system files CHM are located in the Help folder and PDF files are located in the Docs folder of your VisualDSP install...

Page 53: ...tp www analog com processors technical_library Select a processor family and book title Download archive ZIP files one for each manual Use any archive management software such as WinZip to decompress downloaded files Printed Manuals For general questions regarding literature ordering call the Literature Center at 1 800 ANALOGD 1 800 262 5643 and follow the prompts VisualDSP Documentation Set To pu...

Page 54: ...m the Analog Devices Web site Manuals may be ordered by title or by product number located on the back cover of each manual Data Sheets All data sheets preliminary and production may be downloaded from the Analog Devices Web site Only production final data sheets Rev 0 A B C and so on can be obtained from the Literature Center at 1 800 ANALOGD 1 800 262 5643 they also can be downloaded from the We...

Page 55: ...hin brackets indicates a range of registers or pins for example I 3 0 indicates I3 I2 I1 and I0 SMS 3 0 indi cates SMS3 SMS2 SMS1 and SMS0 0xabcd b 1111 A 0x prefix indicates hexadecimal a b prefix indicates binary Note For correct operation A Note provides supplementary information on a related topic In the online version of this book the word Note appears instead of this symbol Caution Incorrect...

Page 56: ...rt name the short name appears first in the bit description followed by the long name in parentheses The reset value appears in binary in the individual bits and in hexa decimal to the right of the register Table P 1 Short Form of Register Names Pattern Description Examples TIMERx_CONFIG The x refers to multiple instances of the peripheral TIMER0_CONFIG TIMER1_CONFIG TIMER2_CONFIG SIC_IARn The n r...

Page 57: ...t value of registers that contain such bits is undefined or depen dent on pin values at reset Shaded bits are reserved L To ensure upward compatibility with future implementations write back the value that is read for reserved bits in a register unless otherwise specified Examples of these conventions are shown in Figure P 1 ...

Page 58: ... mode 11 EXT_CLK mode PULSE_HI CLK_SEL Timer Clock Select TOGGLE_HI PWM_OUT PULSE_HI Toggle Mode ERR_TYP 1 0 Error Type RO PERIOD_CNT Period Count 0 Interrupt request disable 1 Interrupt request enable 0 Count to end of width 1 Count to end of period IRQ_ENA Interrupt Request Enable 0 Sample TMRx pin 1 Sample UART RX pin TIN_SEL Timer Input Select 0 Enable pad in PWM_OUT mode 1 Disable pad in PWM_...

Page 59: ...ossibility to scale up or down based on specific application demands The ADSP BF534 processor is pin compatible with the ADSP BF536 and ADSP BF537 but it does not include the embedded Ethernet controller like the ADSP BF536 and ADSP BF537 devices Peripherals The processor system peripherals include IEEE 802 3 compliant 10 100 Ethernet MAC Not included on the ADSP BF534 Controller Area Network CAN ...

Page 60: ... multiplication Debug JTAG interface These peripherals are connected to the core via several high bandwidth buses as shown in Figure 1 1 for the ADSP BF534 and in Figure 1 2 for the ADSP BF536 and ADSP BF537 All of the peripherals except for general purpose I O CAN TWI RTC and timers are supported by a flexible DMA structure There are also two separate memory DMA channels dedicated to data transfe...

Page 61: ...am VOLTAGE REGULATOR DMA CONTROLLER EVENT CONTROLLER CORE TIMER UART 0 1 TIMERS 0 7 PPI SPORT1 SPI EXTERNAL PORT FLASH SDRAM CONTROL BOOT ROM JTAG TEST AND EMULATION WATCHDOG TIMER L1 INSTRUCTION MEMORY L1 DATA MEMORY MMU B CORE SYSTEM BUS INTERFACE RTC TWI CAN SPORT0 GPIO PORT F GPIO PORT H GPIO PORT G PORT J ...

Page 62: ...de a good cost performance balance of some very fast low latency on chip memory as cache or SRAM and larger lower cost and lower performance off chip memory systems Table 1 1 shows the memory comparison for the ADSP BF534 ADSP BF536 and ADSP BF537 processors Figure 1 2 ADSP BF536 and ADSP BF537 Processor Block Diagram VOLTAGE REGULATOR DMA CONTROLLER EVENT CONTROLLER CORE TIMER UART 0 1 TIMERS 0 7...

Page 63: ...ry The memory DMA controller provides high bandwidth data movement capability It can perform block transfers of code or data between the internal memory and the external memory spaces Table 1 1 Memory Configurations Type of Memory ADSP BF534 ADSP BF536 ADSP BF537 Instruction SRAM cache lockable by way or line 16K byte 16K byte 16K byte Instruction SRAM 48K byte 48K byte 48K byte Data SRAM cache 32...

Page 64: ...e as data SRAM and cannot be configured as cache memory External Memory External off chip memory is accessed via the External Bus Interface Unit EBIU This 16 bit interface provides a glueless connection to a bank of synchronous DRAM SDRAM and as many as four banks of asynchro nous memory devices including flash memory EPROM ROM SRAM and memory mapped I O devices The PC133 compliant SDRAM controlle...

Page 65: ...verhead for the core DMA trans fers can occur between the internal memories and any of its DMA capable peripherals Additionally DMA transfers can be accomplished between any of the DMA capable peripherals and external devices connected to the external memory interfaces including the SDRAM controller and the asynchronous memory controller DMA capable peripherals include the SPORTs SPI ports UARTs a...

Page 66: ...ious memo ries of the system This enables transfers of blocks of data between any of the memories including external SDRAM ROM SRAM and flash memory with minimal processor intervention Memory DMA transfers can be controlled by a very flexible descriptor based methodology or by a standard register based autobuffer mechanism The ADSP BF534 ADSP BF536 and ADSP BF537 processors also include a handshak...

Page 67: ...ameters is available to configure the SDRAM bank to support slower memory devices The memory bank is 16 bits wide for minimum device count and lower system cost Asynchronous Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I O devices Each bank can be independently programmed with different timing parameters This allows conn...

Page 68: ...able pin shares functionality with other ADSP BF534 ADSP BF536 and ADSP BF537 processor peripherals via a multiplexing scheme however the GPIO functionality is the default state of the device upon powerup Neither GPIO output or input drivers are active by default Each general purpose port pin can be individually controlled by manipulation of the port control status and interrupt registers GPIO dir...

Page 69: ...rate hardware interrupts while output pins can be triggered by software interrupts GPIO interrupt sensitivity registers The two GPIO interrupt sen sitivity registers specify whether individual pins are level or edge sensitive and specify if edge sensitive whether just the ris ing edge or both the rising and falling edges of the signal are significant One register selects the type of sensitivity an...

Page 70: ...n and support for clock low extension Separate multiple byte receive and transmit FIFOs Low interrupt rate Individual override control of data and clock lines in the event of bus lock up Input filter for spike suppression Serial camera control bus support as specified in the OmniVision Serial Camera Control Bus SCCB Functional Specification version 2 1 Controller Area Network The Controller Area N...

Page 71: ... extended 29 bit identifiers Supports data rates of up to 1 Mbit second 32 mailboxes 8 transmit 8 receive 16 configurable Dedicated acceptance mask for each mailbox Data filtering first 2 bytes can be used for acceptance filtering Device Net mode Error status and warning registers Transmit priority by identifier Universal counter module Readable receive and transmit pin values These modes support ...

Page 72: ... bit as those of an MII operating at double the frequency The MAC is clocked internally from the CLKIN pin on the processor A buffered version of this clock can also be used to drive the external PHY via the CLKBUF pin A 25 MHz source should be used with an MII PHY A 50 MHz clock source is required to drive an RMII PHY Parallel Peripheral Interface The processor provides a Parallel Peripheral Inte...

Page 73: ...zontal and vertical blanking intervals Though not explicitly supported ITU R 656 output functionality can be achieved by setting up the entire frame structure including active video blanking and control information in memory and streaming the data out the PPI in a frame sync less mode The processor s 2D DMA features facilitate this transfer by allowing the static frame buffer blanking and control ...

Page 74: ...cations The SPORTs support these features Bidirectional I2 S capable operation Each SPORT has two sets of independent transmit and receive pins which enable eight channels of I2 S stereo audio Buffered eight deep transmit and receive ports Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data re...

Page 75: ...n be selected on the transmit and or receive channel of the SPORT without addi tional latencies DMA operations with single cycle overhead Each SPORT can automatically receive and transmit multiple buff ers of memory data The processor can link or chain sequences of DMA transfers between a SPORT and memory Interrupts Each transmit and receive port generates an interrupt upon com pleting the transfe...

Page 76: ...s baud rate and clock phase polarities are programmable and it has an integrated DMA controller configurable to support either transmit or receive datastreams The SPI s DMA controller can only ser vice unidirectional accesses at any given time During transfers the SPI port simultaneously transmits and receives by serially shifting data in and out of its two serial data lines The serial clock line ...

Page 77: ...riodic interrupts UART Ports The processor provides two half duplex Universal Asynchronous Receiver Transmitter UART ports which are fully compatible with PC standard UARTs The UART ports provide a simplified UART inter face to other peripherals or hosts providing half duplex DMA supported asynchronous transfers of serial data The UART ports include support for 5 to 8 data bits 1 or 2 stop bits an...

Page 78: ...obaud detec tion is supported The capabilities of the UART ports are further extended with support for the Infrared Data Association IrDA Serial Infrared Physical Layer Link Specification SIR protocol Real Time Clock The processor s Real Time Clock RTC provides a robust set of digital watch features including current time stopwatch and alarm The RTC is clocked by a 32 768 kHz crystal external to t...

Page 79: ... can wake up the processor from sleep mode or deep sleep mode upon generation of any RTC wakeup event An RTC wakeup event can also wake up the on chip internal voltage regula tor from a powered down state Watchdog Timer The processor includes a 32 bit timer that can be used to implement a software watchdog function A software watchdog can improve system availability by forcing the processor to a k...

Page 80: ...cessor s CLKIN pin The CLKIN input cannot be halted changed or operated below the specified frequency dur ing normal operation This clock signal should be a TTL compatible signal The core clock CCLK and system peripheral clock SCLK are derived from the input clock CLKIN signal An on chip Phase Locked Loop PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplicatio...

Page 81: ...d Active Mode Moderate Power Savings In the active mode the PLL is enabled but bypassed Because the PLL is bypassed the processor s core clock CCLK and system clock SCLK run at the input clock CLKIN frequency In this mode the CLKIN to VCO multi plier ratio can be changed although the changes are not realized until the full on mode is entered DMA access is available to appropriately config ured L1 ...

Page 82: ...he reset interrupt or by an asynchronous interrupt generated by the RTC When in deep sleep mode an RTC asynchronous interrupt causes the processor to transition to the active mode Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode Hibernate State For lowest possible power dissipation this state allows the internal supply VDDINT to be powered down whi...

Page 83: ...nstruction memory after a reset A seventh mode is provided to execute from external memory bypassing the boot sequence Execute from 16 bit external memory Execution starts from address 0x2000 0000 with 16 bit packing The boot ROM is bypassed in this mode All configuration settings are set for the slowest device possible 3 cycle hold time 15 cycle R W access times 4 cycle setup Boot from 8 bit and ...

Page 84: ...the LDR file from an SPI host master agent To hold off the host device from transmitting while the boot ROM is busy the Blackfin processor asserts a flag pin to signal the host device not to send any more bytes until the flag is deasserted The flag is chosen by the user and this information is transferred to the Blackfin processor via bits 8 5 of the FLAG header Boot from UART Using an autobaud ha...

Page 85: ...r can be used to select one processor at a time when booting multiple processors from a single TWI For each of the boot modes a 10 byte header is first read from an external memory device The header specifies the number of bytes to be transferred and the memory destination address Multiple memory blocks may be loaded by any boot sequence Once all blocks are loaded program execu tion commences from...

Page 86: ...y language which takes advantage of the processor s unique architecture offers these advantages Embedded 16 32 bit microcontroller features such as arbitrary bit and bit field manipulation insertion and extraction integer opera tions on 8 16 and 32 bit data types and separate user and supervisor stack pointers Seamlessly integrated DSP CPU features optimized for both 8 bit and 16 bit operations A ...

Page 87: ...a cycle accurate instruc tion level simulator a C C compiler and a C C runtime library that includes DSP and mathematical functions A key point for these tools is C C code efficiency The compiler has been developed for efficient translation of C C code to Blackfin processor assembly The Blackfin processor has architectural features that improve the efficiency of com piled C C code Debugging both C...

Page 88: ...cation code The VDK features include threads critical and unscheduled regions semaphores events and device flags The VDK also supports priority based pre emptive coopera tive and time sliced scheduling approaches In addition the VDK was designed to be scalable If the application does not use a specific feature the support code for that feature is excluded from the target system Because the VDK is ...

Page 89: ...stem loading or timing In addition to the software and hardware development tools available from Analog Devices third parties provide a wide range of tools support ing the Blackfin processor family Hardware tools include the ADSP BF537 EZ KIT Lite standalone evaluation development cards Third party software tools include DSP libraries real time operating sys tems and block diagram design tools ...

Page 90: ...Development Tools 1 32 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 91: ...erful chip bus hierarchy on which all data movement between the processor core internal memory external memory and its rich set of peripherals occurs The chip bus hierarchy includes the control lers for system interrupts test emulation and clock and power management Synchronous clock domain conversion is provided to sup port clock domain transactions between the core and the system The processor s...

Page 92: ...e on chip interfaces between the system and the peripherals via the Peripheral Access Bus PAB DMA Access Bus DAB DMA Core Bus DCB DMA External Bus DEB External Access Bus EAB The External Bus Interface Unit EBIU is the primary chip pin bus and is discussed in Chapter 6 External Bus Interface Unit ...

Page 93: ...AN GPIOS SPORTS SPI EBIU PPI UARTS TIMERS RTC DMA CONTROLLER L1 MEMORY CORE PROCESSOR INSTRUCTION LOAD DATA LOAD DATA EXTERNAL MEMORY DEVICES 64 32 32 16 32 STORE DATA SYSTEM CLOCK SCLK DOMAIN CORE CLOCK CCLK DOMAIN DMA ACCESS BUS DAB EXTERNAL PORT BUS EPB EXTERNAL ACCESS BUS EAB DMA EXTERNAL BUS DEB DMA CORE BUS DCB WATCHDOG TIMER TWI ETHERNET MAC PERIPHERAL ACCESS BUS PAB 16 16 16 16 16 2K ROM 1...

Page 94: ... divide register and must be set so that these buses run as specified in the processor data sheet and slower than or equal to the core clock frequency These buses can also be cycled at a programmable frequency to reduce power consumption or to allow the core processor to run at an optimal frequency Note all synchronous peripherals derive their timing from the SCLK For example the UART clock rate i...

Page 95: ...e bus structure between the processor and L1 memory runs at the full core frequency and has data paths up to 64 bits Figure 2 2 Core Block Diagram INT RESET VECTOR ACK CORE TIMER CORE EVENT CONTROLLER DEBUG AND JTAG INTERFACE JTAG DSP ID 8 BITS SYSTEM CLOCK AND POWER MANAGEMENT POWER AND CLOCK CONTROLLER PERFORMANCE MONITOR MEMORY MANAGEMENT UNIT L1 DATA L1 INSTRUCTION LD0 LD1 SD DA0 DA1 IAB IDB C...

Page 96: ...ls All peripheral resources accessed through the PAB are mapped into the system MMR space of the processor memory map The core accesses system MMR space through the PAB bus The core processor has byte addressability but the programming model is restricted to only 32 bit aligned access to the system MMRs Byte accesses to this region are not supported PAB Arbitration The core is the only master on t...

Page 97: ...erformance For the PAB the primary performance criteria is latency not throughput Transfer latencies for both read and write transfers on the PAB are two SCLK cycles For example the core can transfer up to 32 bits per access to the PAB slaves With the core clock running at 2x the frequency of the system clock the first and subsequent system MMR read or write accesses take four core clocks CCLK of ...

Page 98: ...emory DMA controller access their descriptor lists through the DAB The DCB has priority over the core processor on arbitration into L1 con figured as SRAM For off chip memory the core by default has priority over the DEB for accesses to the EPB The processor has a programmable priority arbitration policy on the DAB Table 2 1 shows the default arbi tration priority In addition by setting the CDPRIO...

Page 99: ...onsiderably higher due to the DAB s pipelined design Bus arbitration cycles are concurrent with the previous DMA access s data cycles Table 2 1 DAB DCB and DEB Arbitration Priority DAB DCB DEB Master Default Arbitration Priority PPI receive transmit 0 highest Ethernet receive 1 Ethernet transmit 2 SPORT0 receive 3 SPORT0 transmit 4 SPORT1 receive 5 SPORT1 transmit 6 SPI receive transmit 7 UART0 re...

Page 100: ... perform locked transfers DMA access to L1 memory can only be stalled by an access already in progress from another DMA channel Latencies caused by these stalls are in addition to any arbitration latencies L The core processor and the DAB must arbitrate for access to exter nal memory through the EBIU This additional arbitration latency added to the latency required to read off chip memory devices ...

Page 101: ...usly accessing on chip and off chip memory considerable throughput can be achieved The throughput rate for an on chip off chip memory access is limited by the slower of the two accesses In the case where the transfer is from on chip to on chip memory or from off chip to off chip memory the burst accesses cannot occur simulta neously The transfer rate is then determined by adding each transfer plus...

Page 102: ...r n Words from start of DMA to interrupt at end 16 bit SDRAM L1 data memory n 14 L1 data memory 16 bit SDRAM n 11 16 bit async memory L1 data memory xn 12 where x is the number of wait states setup hold SCLK cycles minimum x 2 L1 data memory 16 bit async memory xn 9 where x is the number of wait states setup hold SCLK cycles minimum x 2 16 bit SDRAM 16 bit SDRAM 10 17n 7 16 bit async memory 16 bit...

Page 103: ... proces sor system memory map Figure 3 2 on page 3 4 shows this information for the ADSP BF536 processor and Figure 3 3 on page 3 5 for the ADSP BF537 processor For a detailed discussion of how to use them see the ADSP BF53x BF56x Blackfin Processor Programming Reference Note the architecture does not define a separate I O space All resources are mapped through the flat 32 bit address space The me...

Page 104: ...ce Within the external memory map four banks of asynchronous memory space and one bank of SDRAM memory are available Each of the asyn chronous banks is 1M byte and the SDRAM bank is up to 512M byte Table 3 1 Memory Configurations Type of Memory ADSP BF534 ADSP BF536 ADSP BF537 Instruction SRAM Cache lockable by Way or line 16K byte 16K byte 16K byte Instruction SRAM 48K byte 48K byte 48K byte Data...

Page 105: ...ED 0xFFA1 4000 0xFF80 4000 0xFFE0 0000 SYSTEM MMR REGISTERS 2M BYTE 0xFFB0 1000 INSTRUCTION SRAM CACHE 16K BYTE DATA BANK A SRAM 16K BYTE 0x2030 0000 0x2010 0000 0x2020 0000 0x0000 0000 0x2040 0000 0xEF00 0000 0x2000 0000 INTERNAL MEMORY EXTERNAL MEMORY BOOT ROM 2K BYTE RESERVED ASYNC MEMORY BANK 3 1M BYTE ASYNC MEMORY BANK 2 1M BYTE ASYNC MEMORY BANK 1 1M BYTE ASYNC MEMORY BANK 0 1M BYTE 0xFF80 0...

Page 106: ...2K BYTE RESERVED RESERVED 0xFFA1 4000 0xFF80 4000 0xFFE0 0000 SYSTEM MMR REGISTERS 2M BYTE 0xFFB0 1000 INSTRUCTION SRAM CACHE 16K BYTE RESERVED 0x2030 0000 0x2010 0000 0x2020 0000 0x0000 0000 0x2040 0000 0xEF00 0000 0x2000 0000 INTERNAL MEMORY EXTERNAL MEMORY BOOT ROM 2K BYTE RESERVED ASYNC MEMORY BANK 3 1M BYTE ASYNC MEMORY BANK 2 1M BYTE ASYNC MEMORY BANK 1 1M BYTE ASYNC MEMORY BANK 0 1M BYTE 0x...

Page 107: ... BYTE 512M BYTE ADSP BF537 MEMORY MAP 0xEF00 0800 RESERVED 0xFF90 4000 0xFFA 00000 0xFFA0 8000 0xFFA0 C000 0xFFA1 0000 0xFFB0 0000 INSTRUCTION BANK A SRAM 32K BYTE RESERVED RESERVED 0xFFA1 4000 0xFF80 4000 0xFFE0 0000 SYSTEM MMR REGISTERS 2M BYTE 0xFFB0 1000 INSTRUCTION SRAM CACHE 16K BYTE DATA BANK A SRAM 16K BYTE 0x2030 0000 0x2010 0000 0x2020 0000 0x0000 0000 0x2040 0000 0xEF00 0000 0x2000 0000...

Page 108: ...ubbanks Table 3 2 L1 Instruction Memory Subbanks Memory Subbank Memory Start Location ADSP BF534 ADSP BF536 ADSP BF537 0 0xFFA0 0000 1 0xFFA0 1000 2 0xFFA0 2000 3 0xFFA0 3000 4 0xFFA0 4000 5 0xFFA0 5000 6 0xFFA0 6000 7 0xFFA0 7000 8 0xFFA0 8000 9 0xFFA0 9000 10 0xFFA0 A000 11 0xFFA0 B000 12 0xFFA1 0000 13 0xFFA1 1000 14 0xFFA1 2000 15 0xFFA1 3000 ...

Page 109: ...xFF80 2000 Data Bank A Subbank 3 0xFF80 3000 Data Bank A Subbank 4 0xFF80 4000 0xFF80 4000 Data Bank A Subbank 5 0xFF80 5000 0xFF80 5000 Data Bank A Subbank 6 0xFF80 6000 0xFF80 6000 Data Bank A Subbank 7 0xFF80 7000 0xFF80 7000 Data Bank B Subbank 0 0xFF90 0000 Data Bank B Subbank 1 0xFF90 1000 Data Bank B Subbank 2 0xFF90 2000 Data Bank B Subbank 3 0xFF90 3000 Data Bank B Subbank 4 0xFF90 4000 0...

Page 110: ...ry The boot ROM not only contains boot strap loader code it also provides some subfunctions that are user callable at runtime For more information see Chapter 19 System Reset and Booting External Memory The external memory space is shown in Figure 3 1 on page 3 3 One of the memory regions is dedicated to SDRAM support The size of the SDRAM bank is programmable and can range in size from 16M byte t...

Page 111: ...A 1 DAG0 non cacheable fetches use port B Valid only when DMC 1 0 11 Determines whether Address bit A 14 or A 23 is used to select the L1 data cache bank 0 Address bit 14 is used to select Bank A or B for cache access If bit 14 of address is 1 select L1 Data Memory Data Bank A if bit 14 of address is 0 select L1 Data Memory Data Bank B 1 Address bit 23 is used to select Bank A or B for cache acces...

Page 112: ...bbank 0 01 Access subbank 1 10 Access subbank 2 11 Access subbank 3 Subbank Access 1 0 SRAM ADDR 13 12 Reset Undefined Read Write Access Access Way Instruction Address Bit 11 0 Access Way0 Instruction bit 11 0 1 Access Way1 Instruction bit 11 1 Data Instruction Access 0 Access Data 1 Access Instruction 0 Read access 1 Write access Array Access 0 Access tag array 1 Access data array Double Word Ind...

Page 113: ... system has numerous peripherals which therefore require many supporting interrupts Features The Blackfin architecture provides a two level interrupt processing scheme The Core Event Controller CEC runs in the CCLK clock domain It interacts closely with the program sequencer and manages the Event Vector Table EVT The CEC processes not only core related interrupts such as exceptions core errors and...

Page 114: ...own in Figure 4 1 are not available on ADSP BF534 parts Description of Operation The following sections describe the operation of the system interrupts Events and Sequencing The processor employs a two level event control mechanism The proces sor SIC works with the CEC to prioritize and control all system interrupts The SIC provides mapping between the many peripheral inter rupt sources and the pr...

Page 115: ...P CORE TIMER HARDWARE ERROR EXCEPTIONS NMI SIC_IAR3 SIC_IAR2 SIC_IAR1 SIC_IAR0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SIC_ISR SIC_IWR SIC_IMASK RESET EMULATION IMASK IPEND ILAT IVG15 IVG14 IVG13 IVG12 IVG11 IVG10 IVG9 IVG8 IVG7 IVG6 IVG5 IVG3 IVG2 IVG1 IVG0 TWI CAN RX CAN TX TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 PORTG IRQ B MDMA0 MDMA1 PORTF IRQ A P...

Page 116: ...t may be pre empted by one of higher priority The CEC supports nine general purpose interrupts IVG7 IVG15 in addition to the dedicated interrupt and exception events that are described in Table 4 1 It is common for applications to reserve the lowest or the two lowest priority interrupts IVG14 and IVG15 for software interrupts leaving eight or seven prioritized interrupt inputs IVG7 IVG13 for perip...

Page 117: ...ror interrupt MAC error interrupt PPI error interrupt SPORT0 error interrupt SPORT1 error interrupt SPI error interrupt UART0 error interrupt UART1 error interrupt IVG7 Real Time clock interrupts DMA0 interrupt PPI IVG8 DMA3 interrupt SPORT0 RX DMA4 interrupt SPORT0 TX DMA5 interrupt SPORT1 RX DMA6 interrupt SPORT1 TX IVG9 Table 4 1 System and Core Event Mapping Cont d Event Source Core Event Name...

Page 118: ...VG10 Port H interrupt A CAN RX interrupt CAN TX interrupt DMA1 interrupt MAC RX DMA2 interrupt MAC TX Port H interrupt B IVG11 Timer 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt Timer 6 interrupt Timer 7 interrupt Port F interrupt A Port G interrupt A Port G interrupt B IVG12 MDMA0 interrupt MDMA1 interrupt Software watchdog timer Port F int...

Page 119: ...ral interrupt to the appropriate general purpose interrupt level in the core The mapping is controlled by the system interrupt assignment regis ter SIC_IARx settings as detailed in Figure 4 4 on page 4 18 Figure 4 5 on page 4 18 Figure 4 6 on page 4 19 and Figure 4 7 on page 4 19 If more than one interrupt source is mapped to the same interrupt they are logically ORed with no hardware prioritizati...

Page 120: ...f the interrupt usually by writing a system MMR to the time the SIC senses that the interrupt has been deasserted Depending on how interrupt sources map to the general purpose interrupt inputs of the core the interrupt service routine may have to interrogate multiple interrupt status bits to determine the source of the interrupt One of the first instructions executed in an interrupt service routin...

Page 121: ...34 does not include the MAC requests shown in Figure 4 2 However for code compatibility all default assignments are the same as on the ADSP BF536 and ADSP BF537 For dynamic power management any of the peripherals can be configured to wake up the core from its idled state to process the interrupt simply by enabling the appropriate bit in the system interrupt wakeup enable regis ter SIC_IWR refer to...

Page 122: ...in SIC_IMASK the core wakes up if it is idled but it does not generate an interrupt Figure 4 2 Default Peripheral to DMA Mapping DMA0 IRQ DMA0_PERIPHERAL_MAP DMA1 IRQ DMA2 IRQ DMA3 IRQ DMA4 IRQ DMA5 IRQ DMA6 IRQ DMA7 IRQ DMA8 IRQ DMA9 IRQ DMA10 IRQ DMA11 IRQ DMA1_PERIPHERAL_MAP DMA2_PERIPHERAL_MAP DMA3_PERIPHERAL_MAP DMA4_PERIPHERAL_MAP DMA5_PERIPHERAL_MAP DMA6_PERIPHERAL_MAP DMA7_PERIPHERAL_MAP D...

Page 123: ...nt Default DMA Source Mapping Peripheral Interrupt ID Default Mapping Default Core Interrupt ID PLL wakeup 0 IVG7 0 DMA error generic 1 IVG7 0 DMAR0 block interrupt 1 IVG7 0 DMAR1 block interrupt 1 IVG7 0 DMAR0 overflow error 1 IVG7 0 DMAR1 overflow error 1 IVG7 0 CAN error 2 IVG7 0 MAC error1 2 IVG7 0 SPORT 0 error 2 IVG7 0 SPORT 1 error 2 IVG7 0 PPI error 2 IVG7 0 SPI error 2 IVG7 0 UART0 error ...

Page 124: ... channel 9 UART0 TX 12 IVG10 3 DMA channel 10 UART1 RX 13 IVG10 3 DMA channel 11 UART1 TX 14 IVG10 3 CAN RX 15 IVG11 4 CAN TX 16 IVG11 4 DMA channel 11 MAC RX 17 IVG11 4 Port H interrupt A 17 IVG11 4 DMA channel 21 MAC TX 18 IVG11 4 Table 4 2 System Interrupt Controller SIC Cont d Peripheral Interrupt Event Default DMA Source Mapping Peripheral Interrupt ID Default Mapping Default Core Interrupt I...

Page 125: ...Timer 2 21 IVG12 5 Timer 3 22 IVG12 5 Timer 4 23 IVG12 5 Timer 5 24 IVG12 5 Timer 6 25 IVG12 5 Timer 7 26 IVG12 5 Port F G interrupt A 27 IVG12 5 Port G interrupt B 28 IVG12 5 Memory DMA stream 0 29 IVG13 6 Memory DMA stream 1 30 IVG13 6 Software watchdog timer 31 IVG13 6 Port F interrupt B 31 IVG13 6 1 MAC error and DMA requests are not available on the ADSP BF534 However the DMA chan nels 1 and ...

Page 126: ... the specific peripheral interrupts in SIC_IMASK that the system requires System Interrupt Processing Summary Referring to Figure 4 3 on page 4 16 note when an interrupt interrupt A is generated by an interrupt enabled peripheral 1 SIC_ISR logs the request and keeps track of system interrupts that are asserted but not yet serviced that is an interrupt service rou tine hasn t yet cleared the interr...

Page 127: ... ILAT bit Thus IPEND tracks all pending interrupts as well as those being presently serviced 9 When the interrupt service routine ISR for interrupt A has been executed the RTI instruction clears the appropriate IPEND bit However the relevant SIC_ISR bit is not cleared unless the inter rupt service routine clears the mechanism that generated interrupt A or if the process of servicing the interrupt ...

Page 128: ...spurious or lost interrupt activity these registers should be written to only when all peripheral interrupts are disabled Figure 4 3 Interrupt Processing Block Diagram INTERRUPT A SYSTEM INTERRUPT MASK SIC_IMASK ASSIGN SYSTEM PRIORITY SIC_IAR0 3 CORE EVENT CONTROLLER SYSTEM INTERRUPT CONTROLLER NOTE NAMES IN PARENTHESES ARE MEMORY MAPPED REGISTERS EMU RESET NMI EVX IVTMR IVHW PERIPHERAL INTERRUPT ...

Page 129: ... Interrupts Table 4 3 defines the value to write in SIC_IARx to configure a peripheral for a particular IVG priority Table 4 3 IVG Select Definitions General purpose Interrupt Value in SIC_IAR IVG7 0 IVG8 1 IVG9 2 IVG10 3 IVG11 4 IVG12 5 IVG13 6 IVG14 7 IVG15 8 ...

Page 130: ... 16 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 DMA Channel 5 SPORT1 RX Interrupt DMA Channel 4 SPORT0 TX Interrupt Reset 0x2221 1000 DMA Channel 0 PPI Interrupt DMA Channel 3 SPORT0 RX Interrupt DMA Error generic DMAR0 Block DMAR1 Block DMAR0 Overflow Error and DMAR1 Overflow Error Interrupt 0xFFC0 0110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DMA Channel 6 SPORT1 TX Interrupt TW...

Page 131: ...mer 1 Interrupt Reset 0x5555 5444 CAN TX Interrupt DMA Channel 1 Ethernet RX on ADSP BF536 and ADSP BF537 Interrupt and Port H Interrupt A Timer 2 Interrupt Timer 4 Interrupt 0xFFC0 0118 Timer 3 Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 System Interrupt Assignment Register 3 SIC_IAR3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1...

Page 132: ...rupt TWI Interrupt RTC Interrupt DMA11 Interrupt UART1 TX DMA10 Interrupt UART1 RX DMA7 Interrupt SPI DMA6 Interrupt SPORT1 TX DMA5 Interrupt SPORT1 RX DMA4 Interrupt SPORT0 TX DMA3 Interrupt SPORT0 RX DMA0 Interrupt PPI DMA Error generic DMARx Block Interrupt DMARx Overflow Error Interrupt DMA9 Interrupt UART0 TX DMA8 Interrupt UART0 RX Timer 2 Interrupt Port G Interrupt B Interrupt Port F G Inte...

Page 133: ...t RTC Interrupt DMA11 Interrupt UART1 TX DMA10 Interrupt UART1 RX DMA7 Interrupt SPI DMA6 Interrupt SPORT1 TX DMA5 Interrupt SPORT1 RX DMA4 Interrupt SPORT0 TX DMA3 Interrupt SPORT0 RX DMA0 Interrupt PPI DMA Error generic DMARx Block Interrupt DMARx Overflow Error Interrupt DMA9 Interrupt UART0 TX DMA8 Interrupt UART0 RX Timer 2 Interrupt Port G Interrupt B Interrupt Port F G Interrupt A Interrupt...

Page 134: ... Interrupt A Wakeup MDMA1 Wakeup Software Watchdog Timer Port F Inter rupt B Wakeup PLL Wakeup CAN Error MAC Error SPORTx Error PPI Error SPI Error UARTx Error Wakeup CAN TX Wakeup CAN RX Wakeup TWI Wakeup RTC Wakeup DMA11 Wakeup UART1 TX DMA10 Wakeup UART1 RX DMA7 Wakeup SPI DMA6 Wakeup SPORT1 TX DMA5 Wakeup SPORT1 RX DMA4 Wakeup SPORT0 TX DMA3 Wakeup SPORT0 RX DMA0 Wakeup PPI MDMA0 Wakeup Timer ...

Page 135: ...ps requesting the respective ILAT bit is set again immediately and the service routine is invoked again as soon as its first run terminates by an RTI instruction Every software routine that services peripheral interrupts must clear the signalling interrupt request in the respective peripheral The individual peripherals provide customized mechanisms for how to clear interrupt requests Receive inter...

Page 136: ...oad and instruction history The program sequencer does not wait until the instruction completes and con tinues program execution immediately The SSYNC instruction ensures that the W1C command indeed cleared the request in the GPIO peripheral before the RTI instruction executes However the SSYNC instruction does not guarantee that the release of interrupt request has also been recognized by the CEC...

Page 137: ...a common service routine typically interrogates the SIC_ISR register to determine the signalling interrupt source If multiple peripherals are requesting interrupts at the same time it is up to the service routine to either service all requests in a single pass or to service them one by one If only one request is serviced and the respective request is cleared by soft ware before the RTI instruction...

Page 138: ...Programming Examples 4 26 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 139: ...ommon to all the DMA channels as well as how DMA operations are set up For specific peripheral features see the appropriate peripheral chapter for additional information Perfor mance and bus arbitration for DMA operations can be found in DAB DCB and DEB Performance on page 2 10 Overview and Features The processor uses DMA to transfer data between memory spaces or between a memory space and a perip...

Page 140: ...tween memory and memory The processor has two MDMA modules each consisting of independent memory read and memory write channels Handshaking Memory DMA HMDMA transfers data between off chip peripherals and memory This enhancement of the MDMA channels enables external hardware to control the timing of individual data transfers or block transfers All DMAs can transport data to and from on chip and of...

Page 141: ..._X_MODIFY register A circular auto refreshing buffer that interrupts on each full buffer A similar buffer that interrupts on fractional buffers for example 1 2 1 4 2D DMA 1D DMA using a set of identical ping pong buffers defined by a linked ring of 3 word descriptors each containing link pointer 32 bit address 1D DMA using a linked list of 5 word descriptors containing link pointer 32 bit address ...

Page 142: ...lackfin Processor Hardware Reference SPORT0 receive SPORT0 transmit SPORT1 receive SPORT1 transmit SPI receive transmit UART0 receive UART0 transmit UART1 receive UART1 transmit MDMA0 destination MDMA0 source MDMA1 destination MDMA1 source ...

Page 143: ... CONTROL PMAP FIFO DMA 5 CONTROL PMAP FIFO DMA 6 CONTROL PMAP FIFO DMA 7 CONTROL PMAP FIFO DMA 8 CONTROL PMAP FIFO DMA 9 CONTROL PMAP FIFO DMA 10 CONTROL PMAP FIFO DMA 11 CONTROL PMAP FIFO MDMA 1 DESTINATION CONTROL HMDMA 1 FIFO MDMA 1 SOURCE CONTROL MDMA 0 DESTINATION CONTROL HMDMA 0 FIFO MDMA 0 SOURCE CONTROL DMA TRAFFIC CONTROL DMAR0 DMAR1 IRQ 4 IRQ 17 IRQ 18 IRQ 5 IRQ 6 IRQ 7 IRQ 8 IRQ 10 IRQ ...

Page 144: ...ackfin processor memory Both DMARx pins reside on port F and compete with UART0 signals To enable their function set the PFDE bit in the PORT_MUX register and the PF0 and or PF1 bits in the PORTF_FER register The REP bit in the respective HMDMAx_CONTROL register controls whether the DMARx inputs trigger on fall ing or rising edges of the connect strobe Internal Interfaces Figure 2 1 on page 2 3 of...

Page 145: ...cycles as the DCB bus is used for both source and destination transfer Similarly trans fers between two off chip devices require EBIU and DEB resources twice Peripheral DMA transfers can be performed every other SCLK cycle For more details on DMA performance see DMA Performance on page 5 44 Peripheral DMA As can be seen in Figure 5 1 on page 5 5 the DMA controller features 12 channels that perform...

Page 146: ...BF534 devices L Note a 1 1 mapping should exist between DMA channels and peripherals The user is responsible for ensuring that multiple DMA channels are not mapped to the same peripheral and that multiple peripherals are not mapped to the same DMA port If multiple channels are mapped to the same peripheral only one channel is connected the lowest priority channel If a nonexistent peripheral for ex...

Page 147: ...peripheral side DAB side of the FIFO for transmit operations Refer to the SYNC bit in the DMAx_CONFIG register for details Memory DMA This section describes the two MDMA controllers which provide mem ory to memory DMA transfers among the various memory spaces These include L1 memory and external synchronous asynchronous memories Each MDMA controller contains a DMA FIFO an 8 word by 16 bit FIFO blo...

Page 148: ...ect to 16 bit buses Source and destination channel must be programmed to the same word size In other words the MDMA transfer does not perform packing or unpacking of data each read results in one write Both ends of the MDMA FIFO for a given stream are granted priority at the same time Each pair shares an 8 word deep 16 bit FIFO The source DMA engine fills the FIFO while the destination DMA engine ...

Page 149: ...AR1 input with MDMA1 Once a trigger event is detected a programmable portion of data is transferred and then the MDMA stalls again and waits for the next trigger Handshake operation is not only useful to control the timing of mem ory to memory transfers it also enables the MDMA to operate with asynchronous FIFO style devices connected to the EBIU port The Black fin processor acknowledges a DMA req...

Page 150: ...eration For basic operation the software performs these steps Write the source or destination address to the 32 bit DMAx_START_ ADDR register Write the number of data words to be transferred to the 16 bit DMAx_X_COUNT register Write the address modifier to the 16 bit DMAx_X_MODIFY register This is the two s complement value added to the address pointer after every transfer This value must always b...

Page 151: ...s finished Set the FLOW field to 0x0 for stop mode or 0x1 for autobuffer mode Once the DMAEN bit is set the DMA channel starts its operation While running the DMAx_CURR_ADDR and the DMAx_CURR_X_COUNT registers can be monitored to determine the current progress of the DMA operation The DMAx_IRQ_STATUS register signals whether the DMA has finished DMA_DONE bit whether a DMA error has occurred DMA_ER...

Page 152: ...alue An interrupt may also be generated Autobuffer mode is entered if the FLOW field in the DMAx_CONFIG register is 1 The NDSIZE bit must be 0 in autobuffer mode Two Dimensional DMA Operation Register based and descriptor based DMA can operate in one dimensional mode or two dimensional mode In two dimensional 2D mode the DMAx_X_COUNT register is accompanied by the DMAx_Y_COUNT register supporting ...

Page 153: ...er loop count DMAx_CURR_Y_COUNT also expires by decrementing from 1 to 0 After the last transfer completes DMAx_CURR_Y_COUNT 1 DMAx_CURR_X_ COUNT 0 and DMAx_CURR_ADDR is equal to the last item s address plus DMAx_X_MODIFY Note if the DMA channel is programmed to refresh auto matically autobuffer mode then these registers will be loaded from DMAx_X_COUNT DMAx_Y_COUNT and DMAx_START_ADDR upon the fi...

Page 154: ...ollowing address offsets from the start address 0 N M 2 N M 1 N M 1 2 N M 1 2 N M 2 2 N M 2 N M 1 2 N M 1 3 N M 1 Descriptor based DMA Operation In descriptor based DMA operation software does not set up DMA sequences by writing directly into DMA controller registers Rather soft ware keeps DMA configurations called descriptors in memory On demand the DMA controller loads the descriptor from memory...

Page 155: ...r to immediately fetch the descriptor from the address pointed to by the DMAx_NEXT_DESC_PTR register The fetch overwrites the DMAx_CONFIG register again If the DMAEN bit is still set the channel starts DMA processing The DFETCH bit in the DMAx_IRQ_STATUS register tells whether a descriptor fetch is ongoing on the respective DMA channel whereas the DMAx_CURR_ DESC_PTR points to the descriptor value...

Page 156: ...r and therefore their address is known Variable Descriptor Size In any descriptor based mode the NDSIZE field in the configuration word specifies how many 16 bit words of the next descriptor need to be loaded on the next fetch In descriptor based operation NDSIZE must be non zero The descriptor size can be any value from 1 entry the lower 16 bits of DMAx_START_ADDR only to 9 entries all the DMA pa...

Page 157: ...ed Note that every descriptor fetch steals bandwidth from either the DCB bus or DEB bus and the external memory interface so it is best to keep the size of descriptors as small as possible Mixing Flow Modes The FLOW mode of a DMA is not a global setting If the DMA configura tion word is reloaded with a descriptor fetch the FLOW and NDSIZE bit fields can also be altered A small descriptor might be ...

Page 158: ...fore initiating DMA for the first time on a given channel be sure to initialize all parameter registers Be especially careful to ini tialize the upper 16 bits of the DMAx_NEXT_DESC_PTR and DMAx_ START_ADDR registers because they might not otherwise be accessed depending on the chosen FLOW mode of operation Also note that the DMAx_X_MODIFY and DMAx_Y_MODIFY are not preset to a default value at rese...

Page 159: ...ew 1 of 2 COPY FLOW NDSIZE FROM DMA_CONFIG INTO TEMPORARY DESCRIPTOR FETCH COUNTERS B COPY NEXT DESCRIPTOR POINTER TO CURRENT DESCRIPTOR POINTER USER WRITES SOME OR ALL DMA PARAMETER REGISTERS AND THEN WRITES DMA_CONFIG SET DFETCH IN IRQ_STATUS SET DMA_RUN IN IRQ_STATUS BAD DMA_CONFIG TEST DMAEN TEST FLOW TEST FLOW Y N DMA ERROR DMAEN 1 DMAEN 0 FLOW 4 6 OR 7 DMA STOPPED CLEAR DMA_RUN IN IRQ_STATUS...

Page 160: ... COUNTS EXPIRE TEST DI_EN TEST FLOW TEST SYNC WNR DMA STOPPED CLEAR DMA_RUN IN IRQ_STATUS MEMORY WRITE DESTINATION SYNC 0 MEMORY READ FLOW 0 DI_EN 0 DI_EN 1 SIGNAL AN INTERRUPT TO THE CORE SET DMA_DONE IN IRQ_STATUS TRANSFER DATA FROM FIFO TO PERIPHERAL UNTIL EMPTY MAX SIZE DEPENDS ON FLOW IF FLOW 4 MAX_SIZE 7 IF FLOW 6 MAX_SIZE 8 IF FLOW 7 MAX_SIZE 9 NDSIZE 0 OR NDSIZE MAX_SIZE NDSIZE 0 AND NDSIZ...

Page 161: ...value determines whether to load more cur rent registers from descriptor elements in memory while the NDSIZE bits detail how many descriptor elements to fetch before starting DMA DMA registers not included in the descriptor are not modified from their prior values If the FLOW value specifies small or large descriptor list modes the DMAx_ NEXT_DESC_PTR is copied into DMAx_CURR_DESC_PTR Then fetches...

Page 162: ...t descriptor from memory After the above steps DMA data transfer operation begins The DMA channel immediately attempts to fill its FIFO subject to channel prior ity a memory write RX DMA channel begins accepting data from its peripheral and a memory read TX DMA channel begins memory reads provided the channel wins the grant for bus access When the DMA channel performs its first data memory access ...

Page 163: ...register If FLOW 0 stop only Stops operation by clearing the DMA_RUN bit in DMAx_IRQ_STATUS after any data in the channel s DMA FIFO has been transferred to the peripheral During the fetch in FLOW modes 4 6 and 7 the DMA controller sets the DFETCH bit in DMAx_IRQ_STATUS to 1 At this point the DMA operation depends on whether FLOW 4 6 or 7 as follows If FLOW 4 descriptor array Loads a new descripto...

Page 164: ... the 32 bit DMAx_NEXT_DESC_PTR into DMAx_CURR_DESC_PTR Next fetches a descriptor from memory into DMA registers via the new contents of DMAx_CURR_DESC_PTR while incrementing DMAx_ CURR_DESC_PTR The first descriptor element loaded is a new 32 bit value for the full DMAx_NEXT_DESC_PTR followed by the rest of the descriptor elements The high 16 bits of DMAx_NEXT_DESC_PTR may differ from their former ...

Page 165: ...begins again as shown in Figure 5 3 on page 5 22 Work Unit Transitions Transitions from one work unit to the next are controlled by the SYNC bit in the DMAx_CONFIG register of the work units In general continuous tran sitions have lower latency at the cost of restrictions on changes of data format or addressed memory space in the two work units These latency gains and data restrictions arise from ...

Page 166: ... source channels the SYNC bit controls the interrupt timing at the end of the work unit and the han dling of the DMA FIFO between the current and next work unit If SYNC 0 a continuous transition is selected In a continuous transition just after the last data item is read from memory these four operations all start in parallel The interrupt if any is signalled The DMA_DONE bit in the DMAx_IRQ_STATU...

Page 167: ...riting DMAEN 0 the data in the FIFO is lost If SYNC 1 a synchronized transition is selected in which the DMA FIFO is first drained to the destination memory or peripheral before any inter rupt is signalled and before any subsequent descriptor or data is fetched This incurs greater latency but provides direct synchronization between the DMA interrupt and the state of the data at the peripheral For ...

Page 168: ...rictions on the DMA descriptors L If the SYNC bit is 0 on the first descriptor of a descriptor chain after a DMA pause the DMA word size of the new chain must not change from the word size of the previous descriptor chain active before the pause unless the DMA channel is reset between chains by writing the DMAEN bit to 0 and then 1 If the SYNC bit is 1 in the new work unit s DMAx_CONFIG value a sy...

Page 169: ...tops automatically after the work unit is complete If a list or array of descriptors is used to control DMA and if every descriptor contains a DMACFG element then the final DMACFG element should have a FLOW 0 setting to gracefully stop the channel In autobuffer FLOW 1 mode or if a list or array of descriptors without DMACFG elements is used then the DMA transfer process must be termi nated by an M...

Page 170: ..._RUN goes to 0 and any prefetched data is discarded In addition a DMA_ERROR interrupt is asserted There is only one DMA_ERROR interrupt for the whole DMA controller which is asserted whenever any of the channels has detected an error condition The DMA_ERROR interrupt handler must do these things for each channel Read each channel s DMAx_IRQ_STATUS register to look for a channel with the DMA_ERR bi...

Page 171: ... address DMAx_CURR_ ADDR crossed the 0xF000 0000 boundary or the current descriptor pointer DMAx_CURR_DESC_PTR crossed the 0xF000 0000 boundary A memory access error occurred Either an access attempt was made to an internal address not populated or defined as cache or an external access caused an error signaled by the external memory interface Some prohibited situations are not detected by the DMA...

Page 172: ...the associated DMA channel over internal DMA request buses These request buses con sist of three wires per DMA management capable peripheral The DMA control commands extend the set of operations available to the peripheral beyond the simple request data command used by peripherals in general Note that while these DMA control commands are not visible to or con trollable by the user their use by a p...

Page 173: ...ceive and transmit channels of this peripheral use DMA control commands ADSP BF534 processors are not equipped with DMA management capable peripherals MDMA channels do not service peripherals and therefore do not support DMA control commands The DMA control commands are shown in Table 5 4 Table 5 4 DMA Control Commands Code Name Description 000 NOP No operation 001 Restart Restarts the current wor...

Page 174: ...ads from memory DMA data requests from the periph eral are granted as soon as new prefetched data is available in the DMA FIFO The peripheral can thus use the restart command to re attempt a failed transmission of a work unit If a channel programmed for receive memory write receives a restart control command the channel stops writing to memory discards any data held in its DMA FIFO and resets its ...

Page 175: ...rrupt if enabled and begins fetching the next descriptor if any DMA data requests from the peripheral are granted as soon as new prefetched data is available in the DMA FIFO If a channel programmed for receive memory write receives a fin ish control command the channel stops granting new DMA requests while it drains its FIFO Any DMA data received by the DMA Controller prior to the finish command i...

Page 176: ...ready performed at least one DMA transfer in the current work unit and b the current work unit has more than four items remaining in DMAx_ CURR_X_COUNT DMAx_CURR_Y_COUNT thus not yet read from memory Otherwise the current work unit may already have completed memory operations and can no longer be restarted or finished properly If the DMAx_CURR_X_COUNT DMAx_CURR_Y_COUNT of the current work unit is ...

Page 177: ...rocess of completion and transition between work units Similarly if a finish command ended the previous work unit and at least one subsequent DMA data transfer has occurred then the fact that the DMA channel issued the grant guarantees that the previous work unit has already completed the process of draining its data to memory and transi tioning to the new work unit Note that if a peripheral termi...

Page 178: ...read side fills the 8 depth DMA buffers immediately after the receive being enabled issues 8 read commands The HMDMAx_BCINIT registers control how many data transfers are per formed upon every DMA request If set to one the peripheral can time every individual data transfer If greater than one the peripheral must fea ture sufficient buffer size to provide or consume the number of words programmed O...

Page 179: ...are incremented every time a significant edge is detected on the respective DMARx input and are decremented when the MDMA completes the block transfer These read only registers use a 16 bit two s complement data representation if they return zero all requested block transfers have been performed A positive value signals up to 32767 requests that haven t been served yet and indicates that the MDMA ...

Page 180: ... case In the receive example shown in Figure 5 5 the Blackfin processor again does not use the FIFO s internal control mechanism Rather than testing the empty flag the processor counts the number of data words available in the FIFO by its own HMDMAx_ECOUNT register Theoretically the MDMA could immediately process data as soon as it is written into the FIFO by the write strobe but the fast MDMA eng...

Page 181: ...UTE bit in the HMDMAx_CONTROL register set the MDMA gets higher priority as soon as a positive value in the HMDMAx_ECOUNT register becomes higher than the threshold held by the HMDMAx_ECURGENT register HMDMA Interrupts In addition to the normal MDMA interrupt channels the handshake hardware provides two new interrupt sources for each DMARx input All interrupt sources are routed to the global DMA e...

Page 182: ... before enabling the function by the OIE bit Then the overflow interrupt is issued when the value of the HMDMA_ECOUNT register exceeds the threshold in the HMDMA_ECOVERFLOW register DMA Performance The DMA system is designed to provide maximum throughput per chan nel and maximum utilization of the internal buses while accommodating the inherent latencies of memory accesses The Blackfin architectur...

Page 183: ...ts own data FIFO which lies between the DAB bus and the memory buses These FIFOs automatically prefetch data from memory for transmission and buffer received data for later memory writes This allows the peripheral to be granted a DMA transfer with very low latency compared to the total latency of a pipelined memory access permitting the repeat rate bandwidth of each DMA channel to be as fast as po...

Page 184: ... can cause delays for example for accessing the same L1 bank for opening closing SDRAM pages or while filling cache lines Each direction change from RX to TX on the DAB bus imposes a one SCLK cycle delay Direction changes on the DCB bus for example write followed by read to the same bank of internal memory can impose delays Direction changes for example read followed by write on the DEB bus to ext...

Page 185: ...ures described in the next section The MDMA controllers are clocked by SCLK If source and destination are in different memory spaces one internal and one external the internal and external memory transfers are typically simultaneous and continuous maintaining 100 bus utilization of the internal and external memory interfaces This performance is affected by core to system clock frequency ratios At ...

Page 186: ...e source buffer The resulting data is deposited in the MDMA channel s 8 location FIFO and then after a latency of 2 SCLK cycles the destination MDMA channel begins writing data to the destination memory buffer Static Channel Prioritization DMA channels are ordinarily granted service strictly according to their priority The priority of a channel is simply its channel number where lower priority num...

Page 187: ...ority and Default Mapping of Peripheral to DMA Priority DMA Channel PMAP Default Value Peripheral Mapped by Default Highest DMA 0 0x0 PPI receive or transmit DMA 1 0x1 Ethernet MAC receive DMA 2 0x2 Ethernet MAC transmit DMA 3 0x3 SPORT0 receive DMA 4 0x4 SPORT0 transmit DMA 5 0x5 SPORT1 receive DMA 6 0x6 SPORT1 transmit DMA 7 0x7 SPI DMA 8 0x8 UART0 receive DMA 9 0x9 UART0 transmit DMA 10 0xA UAR...

Page 188: ...tiates a flurry of requests perhaps for descriptor fetches or to fill a FIFO in the DMA or in the peripheral If congestion persists lower priority DMA peripherals may become starved for data Even though the peripheral s priority is low if the neces sary data transfer does not take place before the end of the peripheral s regular interval system failure may result To minimize this possibility the D...

Page 189: ...sfer is marked for expedited processing in the targeted memory system L1 or external and so are all prior incomplete memory transfers ahead of it in that memory system This may cause a series of external memory core accesses to be delayed for a few cycles so that a peripheral s urgent request may be accommodated The preferential handling of urgent DMA transfers is completely auto matic No user con...

Page 190: ...OBIN_PERIOD field is set to some nonzero value in the range 1 P 31 then a round robin scheduling method is used The two MDMA streams are granted bus access in alternation in bursts of up to P data transfers This could be used in systems where two transfer pro cesses need to coexist each with a guaranteed fraction of the available bandwidth For example one stream might be programmed for inter nal t...

Page 191: ...associated with reversal of read write direction to memory for example By selection of various round robin period values P which limit how often the MDMA streams alternate maximal transfer efficiency can be maintained Traffic Control In the Blackfin DMA architecture there are two completely separate but simultaneous prioritization processes the DAB bus prioritization and the memory bus DCB and DEB...

Page 192: ...ter See Memory DMA Priority and Scheduling on page 5 51 Using the traffic control features the DMA system preferentially grants data transfers on the DAB or memory buses which are going in the same read write direction as the previous transfer until either the traffic control counter times out or until traffic stops or changes direction on its own When the traffic counter reaches zero the preferen...

Page 193: ...y DMA on page 5 9 Such software needs to be able to accept requests for new DMA transfers from other software tasks integrate these transfers into existing transfer queues and reliably notify other tasks when the transfers are complete In the processor it is possible for each peripheral DMA and memory DMA stream to be managed by a separate task or to be managed together with any other stream Each ...

Page 194: ...pt interaction among the interrupts of differ ent peripherals is much simpler to manage Polling of the DMAx_CURR_ADDR DMAx_CURR_DESC_PTR or DMAx_CURR_X_ COUNT DMAx_CURR_Y_COUNT registers is not recommended as a method of precisely synchronizing DMA with data processing due to DMA FIFOs and DMA memory pipelining The current address pointer and count registers change several cycles in advance of the...

Page 195: ...ry become strictly ordered If the DMA FIFO length and the DMA memory pipeline length are added an estimate can be made of the maximum number of incomplete memory operations in progress at one time Note this is a maximum as the DMA memory pipeline may include traffic from other DMA channels For example assume a peripheral DMA channel is transferring a work unit of 100 data elements into internal me...

Page 196: ...om software ending with the write to the DMAx_CONFIG register The simplest way to signal completion of DMA is by an interrupt This is selected by the DI_EN bit in the DMAx_CONFIG register and by the necessary setup of the system interrupt controller If it is desirable not to use an interrupt the software can poll for completion by reading the DMAx_IRQ_ STATUS register and testing the DMA_RUN bit I...

Page 197: ...buffer could be used to receive 16 bit peripheral data with these settings DMAx_START_ADDR buffer base address DMAx_CONFIG 0x10D7 FLOW 1 DI_EN 1 DI_SEL 1 DMA2D 1 WDSIZE 01 WNR 1 DMAEN 1 DMAx_X_COUNT 512 DMAx_X_MODIFY 2 for 16 bit data DMAx_Y_COUNT 2 for two sub buffers DMAx_Y_MODIFY 2 same as DMAx_X_MODIFY for contigu ous sub buffers 2D polled if interrupt overhead is unacceptable but the loose sy...

Page 198: ...y be appropriate to build a simple FIFO Here the DMA channel may be programmed using 1D Autobuffer mode addressing without any interrupts or polling Descriptor Structures DMA descriptors may be used to transfer data to or from memory data structures that are not simple 1D or 2D arrays For example if a packet of data is to be transmitted from several different locations in memory a header from one ...

Page 199: ...ust all agree with the current descriptor the WDSIZE DI_EN DI_SEL SYNC and DMA2D fields will be taken from the DMAx_CONFIG value in the descriptor read from memory and the field val ues initially written to the register are ignored See Initializing Descriptors in Memory on page 5 111 in the Programming Examples section for information on how descriptors can be set up Descriptor Queue Management A ...

Page 200: ...abling an interrupt on every descriptor This method should only be used if system design can guarantee that each interrupt event will be serviced separately no interrupt overrun To maintain synchronization of the descriptor queue the non interrupt software maintains a count of descriptors added to the queue while the interrupt handler maintains a count of completed descriptors removed from the que...

Page 201: ...e are no more descriptors to process or because the last descriptor was queued too late that is the modification of the next to last descriptor s DMAx_CONFIG ele ment occurred after that element was read into the DMA unit In this case the interrupt handler should write the DMAx_CONFIG value appropriate for the last descriptor to the DMA channel s DMAx_CONFIG register incre ment the completed descr...

Page 202: ...ive queue and then issue one interrupt Also this arrangement makes it easy to start the waiting queue within the interrupt handler by a single DMAx_CONFIG register write After queuing a new waiting descriptor the non interrupt software should leave a message for its interrupt handler in a memory mailbox location containing the desired DMAx_CONFIG value to use to start the first waiting descriptor ...

Page 203: ...ng the first descriptor s DMAx_CONFIG value to the channel s DMAx_ CONFIG register If the queue is not stopped however the non interrupt software must not write the DMAx_CONFIG register which would cause a DMA error but instead it should queue the descriptor onto the waiting queue and update its mailbox directed to the interrupt handler Software Triggered Descriptor Fetches If a DMA has been stopp...

Page 204: ...next descriptor is fetched if FLOW equals 0x4 0x6 or 0x7 In this mode of opera tion the NDSIZE field should at least span up to the DMACFG field to overwrite the configuration register immediately One possible procedure is 1 Write to DMAx_NEXT_DESC_PTR 2 Write to DMAx_CONFIG with FLOW 0x8 NDSIZE 0xA DI_EN 0 DMAEN 1 3 Automatically fetched DMACFG has FLOW 0x0 NDSIZE 0x0 SYNC 1 for transmitting DMAs...

Page 205: ... the whole DMA transaction can be broken into pieces that are individually triggered by software L Source and destination channels of a MDMA may differ in descrip tor structure However the total work count must match when the DMA stops Whenever a MDMA is stopped destination and source channels should both provide the same FLOW 0 mode after exactly the same number of words Accordingly both channels...

Page 206: ...ry mapped Registers MMR Offset Generic MMR Name MMR Description Register Category Name of Corresponding Descriptor Element in Memory 0x00 NEXT_DESC_PTR Link pointer to next descrip tor Parameter NDPH upper 16 bits NDPL lower 16 bits 0x04 START_ADDR Start address of current buffer Parameter SAH upper 16 bits SAL lower 16 bits 0x08 CONFIG DMA Configuration regis ter including enable bit Parameter DM...

Page 207: ...ins Completion and DMA Error Interrupt status and channel state Run Fetch Paused Control Status N A 0x2C PERIPHERAL_MAP Peripheral to DMA Channel Mapping Contains a 4 bit value speci fying the peripheral to associ ate with this DMA channel Read only for MDMA channels Control Status N A 0x30 CURR_X_COUNT Current count 1D or intra row X count 2D counts down from X_ COUNT Current N A 0x34 Reserved Re...

Page 208: ...CONFIG and DMAx_X_COUNT that can be loaded directly from descriptor elements descriptor ele ments are listed in Table 5 6 Current registers such as DMAx_CURR_ADDR and DMAx_CURR_X_COUNT Control status registers such as DMAx_IRQ_STATUS and DMAx_ PERIPHERAL_MAP All DMA registers can be accessed as 16 bit entities However the follow ing registers may also be accessed as 32 bit registers DMAx_NEXT_DESC...

Page 209: ...ERIPHERAL_MAP with 0x7000 and DMA7_PERIPHERAL_ MAP with 0x6000 3 Enable DMA on channels 6 and or 7 Figure 5 6 Peripheral Map Registers X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X 0x0 PPI 0x1 Ethernet MAC Receive reserved on ADSP BF534 0x2 Ethernet MAC Transmit reserved on ADSP BF534 0x3 SPORT0 Receive 0x4 SPORT0 Transmit 0x5 SPORT1 Receive 0x6 SPORT1 Transmit 0x7 SPI 0x8 ...

Page 210: ...AP 0xFFC0 0CAC DMA3_PERIPHERAL_MAP 0xFFC0 0CEC DMA4_PERIPHERAL_MAP 0xFFC0 0D2C DMA5_PERIPHERAL_MAP 0xFFC0 0D6C DMA6_PERIPHERAL_MAP 0xFFC0 0DAC DMA7_PERIPHERAL_MAP 0xFFC0 0DEC DMA8_PERIPHERAL_MAP 0xFFC0 0E2C DMA9_PERIPHERAL_MAP 0xFFC0 0E6C DMA10_PERIPHERAL_MAP 0xFFC0 0EAC DMA11_PERIPHERAL_MAP 0xFFC0 0EEC MDMA_D0_PERIPHERAL_MAP 0xFFC0 0F2C MDMA_S0_PERIPHERAL_MAP 0xFFC0 0F6C MDMA_D1_PERIPHERAL_MAP 0x...

Page 211: ...P default setting on ADSP BF534 DMA3 SPORT0 receive b 0011 0000 0000 0000 DMA4 SPORT0 transmit b 0100 0000 0000 0000 DMA5 SPORT1 receive b 0101 0000 0000 0000 DMA6 SPORT1 transmit b 0110 0000 0000 0000 DMA7 SPI receive transmit b 0111 0000 0000 0000 DMA8 UART0 receive b 1000 0000 0000 0000 DMA9 UART0 transmit b 1001 0000 0000 0000 DMA10 UART1 receive b 1010 0000 0000 0000 DMA11 UART1 transmit b 10...

Page 212: ...tor list large model Configuration Registers DMAx_CONFIG MDMA_yy_CONFIG NDSIZE 3 0 Flex Descriptor Size Size of next descriptor 0000 Required if in Stop or Autobuffer mode 0001 1001 Descriptor size 1010 1111 Reserved FLOW 2 0 Next Operation DMAEN DMA Channel Enable 0 Disable DMA channel 1 Enable DMA channel WNR DMA Direction 0 DMA is a memory read source operation 1 DMA is a memory write destinati...

Page 213: ...MAx_IRQ_STATUS register changes from 1 to 0 while the DMAEN bit in the DMAx_CONFIG register is unchanged In this state the channel is paused Peripheral Table 5 9 Configuration Register Memory mapped Addresses Register Name Memory mapped Address DMA0_CONFIG 0xFFC0 0C08 DMA1_CONFIG 0xFFC0 0C48 DMA2_CONFIG 0xFFC0 0C88 DMA3_CONFIG 0xFFC0 0CC8 DMA4_CONFIG 0xFFC0 0D08 DMA5_CONFIG 0xFFC0 0D48 DMA6_CONFIG...

Page 214: ...L elements Because the descriptor does not contain a next descriptor pointer entry the DMA engine defaults to using the DMAx_CURR_DESC_PTR register to step through descriptors thus allowing a group of descriptors to follow one another in memory like an array 0x6 descriptor list small model mode This mode fetches a descriptor from memory that includes NDPL but not NDPH There fore the high 16 bits o...

Page 215: ... the interrupt timing at the end of the work unit and the handling of the DMA FIFO between the current and next work unit L Work unit transitions for MDMA streams are controlled by the SYNC bit of the MDMA source channel s DMAx_CONFIG register The SYNC bit of the MDMA destination channel is reserved and must be 0 DMA2D DMA mode This bit specifies whether DMA mode involves only DMAx_X_COUNT and DMA...

Page 216: ...rupt status register DMAx_IRQ_STATUS MDMA_yy_IRQ_STATUS shown in Figure 5 8 contains bits that record whether the DMA channel Is enabled and operating enabled but stopped or disabled Is fetching data or a DMA descriptor Has detected that a global DMA interrupt or a channel interrupt is being asserted Has logged occurrence of a DMA error Note the DMA_DONE interrupt is asserted when the last memory ...

Page 217: ...ed and operating either transferring data or fetching a DMA descriptor Interrupt Status Registers DMAx_IRQ_STATUS MDMA_yy_IRQ_STATUS DFETCH DMA Descriptor Fetch RO DMA_RUN DMA Channel Running RO DMA_DONE DMA Comple tion Interrupt Status W1C 0 No interrupt is being asserted for this channel 1 DMA work unit has completed and this DMA channel s interrupt is being asserted DMA_ERR DMA Error Inter rupt...

Page 218: ...r Memory mapped Addresses Register Name Memory mapped Address DMA0_IRQ_STATUS 0xFFC0 0C28 DMA1_IRQ_STATUS 0xFFC0 0C68 DMA2_IRQ_STATUS 0xFFC0 0CA8 DMA3_IRQ_STATUS 0xFFC0 0CE8 DMA4_IRQ_STATUS 0xFFC0 0D28 DMA5_IRQ_STATUS 0xFFC0 0D68 DMA6_IRQ_STATUS 0xFFC0 0DA8 DMA7_IRQ_STATUS 0xFFC0 0DE8 DMA8_IRQ_STATUS 0xFFC0 0E28 DMA9_IRQ_STATUS 0xFFC0 0E68 DMA10_IRQ_STATUS 0xFFC0 0EA8 DMA11_IRQ_STATUS 0xFFC0 0EE8 ...

Page 219: ...te one to clear W1C a When switching a peripheral from DMA to non DMA mode the peripheral s interrupts should be disabled during the mode switch via the appropriate peripheral registers or SIC_IMASK so that no unintended interrupt is generated on the shared DMA interrupt request line Table 5 11 Data Driven Interrupts Interrupt Name Description No Interrupt Interrupts can be disabled for a given wo...

Page 220: ...ss DMA0_START_ADDR 0xFFC0 0C04 DMA1_START_ADDR 0xFFC0 0C44 DMA2_START_ADDR 0xFFC0 0C84 DMA3_START_ADDR 0xFFC0 0CC4 DMA4_START_ADDR 0xFFC0 0D04 DMA5_START_ADDR 0xFFC0 0D44 DMA6_START_ADDR 0xFFC0 0D84 DMA7_START_ADDR 0xFFC0 0DC4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X DMA Start Address 31 16 X X X X X X X X X X X X X X X Start Address Registers DMAx_START_ADDR MDMA_yy_START_ADDR 15 14 13 1...

Page 221: ...k unit the DMAx_CURR_ADDR register is loaded from the DMAx_START_ADDR register and it is incremented as each transfer occurs The current address register contains 32 bits DMA8_START_ADDR 0xFFC0 0E04 DMA9_START_ADDR 0xFFC0 0E44 DMA10_START_ADDR 0xFFC0 0E84 DMA11_START_ADDR 0xFFC0 0EC4 MDMA_D0_START_ADDR 0xFFC0 0F04 MDMA_S0_START_ADDR 0xFFC0 0F44 MDMA_D1_START_ADDR 0xFFC0 0F84 MDMA_S1_START_ADDR 0xF...

Page 222: ...4 DMA8_CURR_ADDR 0xFFC0 0E24 DMA9_CURR_ADDR 0xFFC0 0E64 DMA10_CURR_ADDR 0xFFC0 0EA4 DMA11_CURR_ADDR 0xFFC0 0EE4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X Current Address 31 16 X X X X X X X X X X X X X X X Current Address Registers DMAx_CURR_ADDR MDMA_yy_CURR_ADDR R W prior to enabling channel RO after enabling channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X Current Address 15 0 X X X X X ...

Page 223: ...ts MDMA_D0_CURR_ADDR 0xFFC0 0F24 MDMA_S0_CURR_ADDR 0xFFC0 0F64 MDMA_D1_CURR_ADDR 0xFFC0 0FA4 MDMA_S1_CURR_ADDR 0xFFC0 0FE4 Figure 5 11 Inner Loop Count Registers Table 5 13 Current Address Register Memory mapped Addresses Cont d Register Name Memory mapped Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X_COUNT 15 0 Inner Loop Count X X X X X X X X X X X X X X X Inner Loop Count Registers DMAx_X_C...

Page 224: ... is reloaded with the value in the DMAx_X_ COUNT register this occurs at the same time that the value in the DMAx_ CURR_Y_COUNT register is decremented Otherwise it is decremented each Table 5 14 Inner Loop Count Register Memory mapped Addresses Register Name Memory mapped Address DMA0_X_COUNT 0xFFC0 0C10 DMA1_X_COUNT 0xFFC0 0C50 DMA2_X_COUNT 0xFFC0 0C90 DMA3_X_COUNT 0xFFC0 0CD0 DMA4_X_COUNT 0xFFC...

Page 225: ...ed Address DMA0_CURR_X_COUNT 0xFFC0 0C30 DMA1_CURR_X_COUNT 0xFFC0 0C70 DMA2_CURR_X_COUNT 0xFFC0 0CB0 DMA3_CURR_X_COUNT 0xFFC0 0CF0 DMA4_CURR_X_COUNT 0xFFC0 0D30 DMA5_CURR_X_COUNT 0xFFC0 0D70 DMA6_CURR_X_COUNT 0xFFC0 0DB0 DMA7_CURR_X_COUNT 0xFFC0 0DF0 DMA8_CURR_X_COUNT 0xFFC0 0E30 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X CURR_X_COUNT 15 0 Current Inner Loop Count X X X X X X X X X X X X X X X Curren...

Page 226: ...after transferring each element in the inner loop up to but not including the last element in each inner loop After the last element in each inner loop the DMAx_Y_MODIFY register is applied instead except on the very last transfer of each work unit The DMAx_X_MODIFY register is always applied on the last transfer of a work unit DMA9_CURR_X_COUNT 0xFFC0 0E70 DMA10_CURR_X_COUNT 0xFFC0 0EB0 DMA11_CUR...

Page 227: ...dress DMA0_X_MODIFY 0xFFC0 0C14 DMA1_X_MODIFY 0xFFC0 0C54 DMA2_X_MODIFY 0xFFC0 0C94 DMA3_X_MODIFY 0xFFC0 0CD4 DMA4_X_MODIFY 0xFFC0 0D14 DMA5_X_MODIFY 0xFFC0 0D54 DMA6_X_MODIFY 0xFFC0 0D94 DMA7_X_MODIFY 0xFFC0 0DD4 DMA8_X_MODIFY 0xFFC0 0E14 DMA9_X_MODIFY 0xFFC0 0E54 DMA10_X_MODIFY 0xFFC0 0E94 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X_MODIFY 15 0 Inner Loop Address Increment X X X X X X X X X X X X ...

Page 228: ...Y 0xFFC0 0ED4 MDMA_D0_X_MODIFY 0xFFC0 0F14 MDMA_S0_X_MODIFY 0xFFC0 0F54 MDMA_D1_X_MODIFY 0xFFC0 0F94 MDMA_S1_X_MODIFY 0xFFC0 0FD4 Figure 5 14 Outer Loop Count Registers Table 5 16 Inner Loop Address Increment Register Memory mapped Addresses Cont d Register Name Memory mapped Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X Y_COUNT 15 0 Outer Loop Count X X X X X X X X X X X X X X X Outer Loop Coun...

Page 229: ... register The register is decremented each time the DMAx_CURR_X_COUNT register expires during 2D DMA operation 1 to Table 5 17 Outer Loop Count Register Memory mapped Addresses Register Name Memory mapped Address DMA0_Y_COUNT 0xFFC0 0C18 DMA1_Y_COUNT 0xFFC0 0C58 DMA2_Y_COUNT 0xFFC0 0C98 DMA3_Y_COUNT 0xFFC0 0CD8 DMA4_Y_COUNT 0xFFC0 0D18 DMA5_Y_COUNT 0xFFC0 0D58 DMA6_Y_COUNT 0xFFC0 0D98 DMA7_Y_COUNT...

Page 230: ..._CURR_Y_COUNT 0xFFC0 0CB8 DMA3_CURR_Y_COUNT 0xFFC0 0CF8 DMA4_CURR_Y_COUNT 0xFFC0 0D38 DMA5_CURR_Y_COUNT 0xFFC0 0D78 DMA6_CURR_Y_COUNT 0xFFC0 0DB8 DMA7_CURR_Y_COUNT 0xFFC0 0DF8 DMA8_CURR_Y_COUNT 0xFFC0 0E38 DMA9_CURR_Y_COUNT 0xFFC0 0E78 DMA10_CURR_Y_COUNT 0xFFC0 0EB8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X CURR_Y_COUNT 15 0 Current Outer Loop Count X X X X X X X X X X X X X X X Current Outer Loop C...

Page 231: ...n page 5 14 L Note DMAx_Y_MODIFY is specified in bytes regardless of the DMA transfer size DMA11_CURR_Y_COUNT 0xFFC0 0EF8 MDMA_D0_CURR_Y_COUNT 0xFFC0 0F38 MDMA_S0_CURR_Y_COUNT 0xFFC0 0F78 MDMA_D1_CURR_Y_COUNT 0xFFC0 0FB8 MDMA_S1_CURR_Y_COUNT 0xFFC0 0FF8 Figure 5 16 Outer Loop Address Increment Registers Table 5 18 Current Outer Loop Count Register Memory mapped Addresses Cont d Register Name Memor...

Page 232: ...list modes At the start of a descriptor fetch in either of these modes the Table 5 19 Outer Loop Address Increment Register Memory mapped Addresses Register Name Memory mapped Address DMA0_Y_MODIFY 0xFFC0 0C1C DMA1_Y_MODIFY 0xFFC0 0C5C DMA2_Y_MODIFY 0xFFC0 0C9C DMA3_Y_MODIFY 0xFFC0 0CDC DMA4_Y_MODIFY 0xFFC0 0D1C DMA5_Y_MODIFY 0xFFC0 0D5C DMA6_Y_MODIFY 0xFFC0 0D9C DMA7_Y_MODIFY 0xFFC0 0DDC DMA8_Y_M...

Page 233: ...arded and fetching is controlled only by the DMAx_CURR_DESC_PTR register Figure 5 17 Next Descriptor Pointer Registers Table 5 20 Next Descriptor Pointer Register Memory mapped Addresses Register Name Memory mapped Address DMA0_NEXT_DESC_PTR 0xFFC0 0C00 DMA1_NEXT_DESC_PTR 0xFFC0 0C40 DMA2_NEXT_DESC_PTR 0xFFC0 0C80 DMA3_NEXT_DESC_PTR 0xFFC0 0CC0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X Nex...

Page 234: ...ore loading each descriptor Then the address in the DMAx_CURR_DESC_PTR register increments as each descriptor element is read in When the entire descriptor has been read the DMAx_CURR_DESC_PTR regis ter contains this value Descriptor Start Address 2 x Descriptor Size of elements DMA4_NEXT_DESC_PTR 0xFFC0 0D00 DMA5_NEXT_DESC_PTR 0xFFC0 0D40 DMA6_NEXT_DESC_PTR 0xFFC0 0D80 DMA7_NEXT_DESC_PTR 0xFFC0 0...

Page 235: ...FFC0 0CA0 DMA3_CURR_DESC_PTR 0xFFC0 0CE0 DMA4_CURR_DESC_PTR 0xFFC0 0D20 DMA5_CURR_DESC_PTR 0xFFC0 0D60 DMA6_CURR_DESC_PTR 0xFFC0 0DA0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X Current Descriptor Pointer 31 16 X X X X X X X X X X X X X X X Current Descriptor Pointer Registers DMAx_CURR_DESC_PTR MDMA_yy_CURR_DESC_PTR R W prior to enabling channel RO after enabling channel Reset Undefined Upp...

Page 236: ...E20 DMA9_CURR_DESC_PTR 0xFFC0 0E60 DMA10_CURR_DESC_PTR 0xFFC0 0EA0 DMA11_CURR_DESC_PTR 0xFFC0 0EE0 MDMA_D0_CURR_DESC_PTR 0xFFC0 0F20 MDMA_S0_CURR_DESC_PTR 0xFFC0 0F60 MDMA_D1_CURR_DESC_PTR 0xFFC0 0FA0 MDMA_S1_CURR_DESC_PTR 0xFFC0 0FE0 Table 5 22 Naming Conventions for Handshake MDMA Registers Handshake MDMA MMR Name x 0 or 1 HMDMAx_CONTROL HMDMAx_BCINIT HMDMAx_BCOUNT HMDMAx_ECOUNT HMDMAx_ECINIT Ta...

Page 237: ...Priority Description 00 Disabled The MDMA request is disabled 01 Enabled S Normal MDMA channel priority The channel in this mode is limited to single memory transfers separated by one idle system clock Request single transfer from MDMA channel 10 Enabled M Normal MDMA channel functionality and priority Request multiple transfers from MDMA channel default 11 Urgent The MDMA channel priority is elev...

Page 238: ...rs from MDMA channel BDI Block Done Interrupt Generated W1C HMDMAEN Handshake MDMA Enable 0 Disable handshake Operation 1 Enable handshake Operation REP HMDMA Request Polarity 0 Increment ECOUNT on falling edges of DMARx input 1 Increment ECOUNT on rising edges of DMARx input UTE Urgency Threshold Enable 0 Disable urgency threshold 1 Enable urgency threshold OIE Overflow Interrupt Enable 0 Disable...

Page 239: ...d if this count is greater than 0 Examples 0000 0 transfers remaining FFFF 65535 transfers remaining The BCOUNT field is loaded with BCINIT when ECOUNT is greater than 0 and BCOUNT is expired 0 Also if the RBC bit in the HMDMAx_CONTROL register is written to a 1 BCOUNT is loaded with BCINIT The BCOUNT field is decre mented with each MDMA grant It is cleared when HMDMA is disabled Figure 5 20 Hands...

Page 240: ...ement representation An edge is detected on the respective DMARx input Requests occur if this count is greater than or equal to 0 and BCOUNT is greater than 0 When the handshake mode is enabled ECOUNT is loaded and the resulting number of requests is Number of edges N where N is the number loaded from ECINIT The number N is a positively or negatively signed number Examples 7FFF 32767 edges remaini...

Page 241: ...HMDMAx_ECOUNT when handshake DMA is enabled This num ber is in a signed two s complement representation Figure 5 22 Handshake MDMA Current Edge Count Registers Figure 5 23 Handshake MDMA Initial Edge Count Registers 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 Handshake MDMA Current Edge Count Register HMDMAx_ECOUNT ECOUNT 15 0 Edges Remaining to be Serviced Reset 0x0000 H...

Page 242: ...rrupt threshold If the ECOUNT field in the handshake MDMA edge count register is greater than this threshold an overflow interrupt is generated Figure 5 24 Handshake MDMA Edge Count Urgent Registers Figure 5 25 Handshake MDMA Edge Count Overflow Interrupt Registers 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 Handshake MDMA Edge Count Urgent Registers HMDMAx_ECURGENT UTHE ...

Page 243: ... is allowed up to that number of DMA transfers to the exclusion of the other MDMA streams DMA Traffic Control Counter Period Register DMA_TC_PER DAB_TRAFFIC_PERIOD 2 0 000 No DAB bus transfer grouping performed Other Preferred length of unidirectional bursts on the DAB bus between the DMA and the peripherals MDMA_ROUND_ROBIN_ PERIOD 4 0 DCB_TRAFFIC_PERIOD 3 0 DEB_TRAFFIC_PERIOD 3 0 Reset 0x0000 00...

Page 244: ...wn from DAB_TRAFFIC_PERIOD to 0 on each system clock except for DMA stalls While this count is nonzero same direction DAB accesses are treated preferentially When this count decre ments from 1 to 0 the opposite direction DAB access is treated preferentially which may result in a direction change When this count is 0 and a DAB bus access occurs the count is reloaded from DAB_TRAFFIC_ PERIOD to begi...

Page 245: ...g in the DCB traffic period It initializes to DCB_TRAFFIC_PERIOD whenever DMA_TC_PER is written or whenever the DCB bus changes direction or becomes idle It then counts down from DCB_TRAFFIC_PERIOD to 0 on each system clock except for DMA stalls While this count is nonzero same direction DCB accesses are treated preferentially When this count decre ments from 1 to 0 the opposite direction DCB acce...

Page 246: ...e channel re sort elements and to let the destination buffer store linearly Listing 5 1 Register Based 2D Memory DMA include defBF537 h define X 5 define Y 6 section L1_data_a byte2 aSource X Y 1 7 13 19 25 2 8 14 20 26 3 9 15 21 27 4 10 16 22 28 5 11 17 23 29 6 12 18 24 30 section L1_data_b byte2 aDestination X Y section L1_code global _main Figure 5 28 DMA Example 2D Array 1 2 3 4 5 6 8 7 9 10 1...

Page 247: ...he destination channel Also it is common to synchro nize interrupts with the destination channel because only those interrupts indicate completion of both DMA read and write operations Listing 5 2 Two Dimensional Memory DMA Setup Example memdma_setup sp r7 setup 1D source DMA for 16 bit transfers r7 l lo aSource r7 h hi aSource p0 MDMA_S0_START_ADDR MDMA_S0_CONFIG r7 r7 l 2 w p0 MDMA_S0_X_MODIFY M...

Page 248: ... WDSIZE_16 WNR DMAEN w p0 MDMA_D0_CONFIG MDMA_S0_CONFIG r7 r7 sp rts memdma_setup end For simplicity the example shown in Listing 5 3 polls the DMA status rather than using interrupts which was the normal case in a real application Listing 5 3 Polling DMA Status memdma_wait sp r7 memdma_wait test r7 w p0 MDMA_D0_IRQ_STATUS MDMA_S0_CONFIG z CC bittst r7 bitpos DMA_DONE if CC jump memdma_wait test r...

Page 249: ...Listing 5 4 uses multiple variables of either 16 bit or 32 bit size to describe DMA descriptors This example has two descriptors in small list flow mode that point to each other mutually At the end of the second work unit an interrupt is generated without discontinuing the DMA pro cessing The trailing end label is required to let the linker know that a descriptor forms a logical unit It prevents t...

Page 250: ...header files The header file descriptor h could look like Listing 5 5 Listing 5 5 Header File to Define Descriptor Structures ifndef __INCLUDE_DESCRIPTORS__ define __INCLUDE_DESCRIPTORS__ ifdef _LANGUAGE_C typedef struct void pStart short dConfig short dXCount short dXModify short dYCount short dYModify dma_desc_arr typedef struct void pNext void pStart short dConfig short dXCount short dXModify s...

Page 251: ... file is required to import the C style header file and can finally take advantage of the structures See Listing 5 6 Listing 5 6 Using Descriptor Structures include descriptors h import descriptors h section L1_data_a align 4 var arrBlock3 N var arrBlock4 N struct dma_desc_list descBlock3 descBlock4 arrBlock3 FLOW_LARGE NDSIZE_7 WDSIZE_32 DMAEN length arrBlock3 4 0 0 unused values struct dma_desc_...

Page 252: ...iptor and thus overwrites the configuration value again with the new settings Note the requirement that source and destination channels stop after the same number of transfers In between stops the two channels can have completely individual structure Listing 5 7 Software Triggered Descriptor Fetch define N 4 section L1_data_a byte2 arrSource1 N 0x1001 0x1002 0x1003 0x1004 byte2 arrSource2 N 0x2001...

Page 253: ...1 2 0 0 unused values struct dma_desc_list descDest2 descDest1 arrDest2 DI_EN WDSIZE_16 WNR DMAEN length arrDest2 2 0 0 unused values section L1_code _main write descriptor address to next descriptor pointer p0 h hi MDMA_S0_CONFIG p0 l lo MDMA_S0_CONFIG r0 h hi descDest1 r0 l lo descDest1 p0 MDMA_D0_NEXT_DESC_PTR MDMA_S0_CONFIG r0 r0 h hi descSource1 r0 l lo descSource1 p0 MDMA_S0_NEXT_DESC_PTR MD...

Page 254: ...r0 wait for any software or hardware event here start next work unit w p0 MDMA_S0_CONFIG MDMA_S0_CONFIG r6 w p0 MDMA_D0_CONFIG MDMA_S0_CONFIG r7 jump _main wait _main end Handshaked Memory DMA Example The functional block for the handshaked MDMA operation can be seen completely separately from the MDMA channels themselves Therefore the following HMDMA setup routine can be combined with any of the ...

Page 255: ...1 r0 every single transfer requires one DMAR1 event p1 l lo HMDMA1_BCINIT r0 l 1 w p1 r0 start with balanced request counter p1 l lo HMDMA1_ECINIT r0 l 0 w p1 r0 enable for rising edges p1 l lo HMDMA1_CONTROL r2 l REP HMDMAEN w p1 r2 If the HMDMA is intended to copy from internal memory to external devices the above setup is sufficient If however the data flow is from out side the processor to int...

Page 256: ...ntil eight DMAR1 requests have been received Note that doing so the transmitter is required to add eight trailing dummy writes after all data words have been sent This is because the transmit channel still has to drain the DMA FIFO Listing 5 9 HMDMA With Delayed Processing wait for eight requests p1 l lo HMDMA1_ECOUNT r0 7 z initial_requests r1 w p1 z CC r1 r0 if CC jump initial_requests disable a...

Page 257: ... external bus controller The address of the request determines whether the request is serviced by the EBIU SDRAM controller or the EBIU asynchronous memory controller The DMA controller provides high bandwidth data movement capability The Memory DMA MDMA channels can perform block transfers of code or data between the internal memory and the external memory spaces The MDMA channels also feature a ...

Page 258: ...range in size from 16M byte to 512M byte The start address of the SDRAM memory space is 0x0000 0000 The area from the end of the SDRAM memory space up to address 0x2000 0000 is reserved The next four regions are dedicated to supporting asynchronous memo ries Each asynchronous memory region can be independently programmed to support different memory device characteristics Each region has its own me...

Page 259: ...Y BANK 1 1 MByte SDRAM MEMORY 16 MByte 512 MByte 0x2000 0000 0x2010 0000 EXTERNAL MEMORY MAP 0x2040 0000 ASYNC MEMORY BANK 2 1 MByte 0x2020 0000 0x2030 0000 0xEEFF FFFF NOTE RESERVED OFF CHIP MEMORY AREAS ARE LABELED IN THE DIAGRAM ABOVE ALL OTHER OFF CHIP SYSTEM RESOURCES ARE ADDRESSABLE BOTH THE CORE AND THE SYSTEM ASYNC MEMORY BANK 3 1 MByte RESERVED RESERVED ...

Page 260: ...rol address and data pins for each memory type are multiplexed together at the pins of the device The Asynchronous Memory Controller AMC and the SDRAM Controller SDC effectively arbitrate for the shared pin resources Figure 6 2 External Bus Interface Unit EBIU ABE 1 0 SDQM 1 0 EBIU ASYNCHRONOUS MEMORY CONTROLLER AMC SDRAM CONTROLLER SDC EXTERNAL BUS CONTROLLER EBC EAB PAB DEVICE PADS DATA 15 0 ADD...

Page 261: ...o access the EBIU Since the AMC and SDC share the same interface to the external pins access is sequential and must be arbitrated based on requests from the EAB The third bus PAB is used only to access the memory mapped control and status registers of the EBIU The PAB connects separately to the AMC and SDC it does not need to arbitrate with or take access cycles from the EAB bus The External Bus C...

Page 262: ...ntrol register EBIU_SDBCTL SDRAM refresh rate control register EBIU_SDRRC SDRAM control status register EBIU_SDSTAT Each of these registers is described in detail in the AMC and SDC sections later in this chapter Shared Pins Both the AMC and the SDC share the external interface address and data pins as well as some of the control signals These pins are shared ADDR 19 1 address bus DATA 15 0 data b...

Page 263: ...sses reserved or disabled memory or functions It responds by completing the bus operation asserting the appropriate number of acknowledges as speci fied by the bus master and by asserting the bus error signal for these error conditions Any access to a disabled external memory bank Any access to reserved SDRAM memory space Any access to unpopulated SDRAM space If the core requested the faulting bus...

Page 264: ...ry control signals can optionally be three stated Asserting the bus grant BG signal The processor may halt program execution if the bus is granted to an external device and an instruction fetch or data read write request is made to external memory When the external device releases BR the processor deasserts BG and continues execution from the point at which it stopped The processor asserts the BGH...

Page 265: ...s AMC supports 8 bit data masking writes AMC has control of the EBIU while auto refresh is performed to SDRAM AMC supports asynchronous access extension ARDY pin Supports instruction fetch Allows booting from bank 0 AMS0 Asynchronous Memory Interface The asynchronous memory interface allows a glueless interface to a variety of memory and peripheral types These include SRAM ROM EPROM flash memory a...

Page 266: ...ble to allow a flexible interface to devices of differ ent speeds For example interfaces see Chapter 21 System Design AMC Pin Description The following table describes the signals associated with each interface Table 6 1 Asynchronous Memory Bank Address Range Memory Bank Select Address Start Address End AMS 3 0x2030 0000 0x203F FFFF AMS 2 0x2020 0000 0x202F FFFF AMS 1 0x2010 0000 0x201F FFFF AMS 0...

Page 267: ...r The first case is a read followed by a write to the same memory space In this case the data bus drivers can potentially contend with those of the memory device addressed by the read The second case is back to back reads from two different AWE O Asynchronous memory write enable ARE O Asynchronous memory read enable AOE O Asynchronous memory output enable In most cases the AOE pin should be connec...

Page 268: ... write access timer has counted down or to ignore this input signal If enabled and disabled at the sample window ARDY can be used to extend the access time as required The polarity of ARDY is programmable on a per bank basis Since ARDY is not sampled until an access is in progress to a bank in which the ARDY enable is asserted ARDY does not need to be driven by default For more information see Add...

Page 269: ...signals are low during the read 2 At the beginning of the read access period and after the 2 setup cycles ARE asserts 3 At the beginning of the hold period read data is sampled on the rising edge of the EBIU clock The ARE pin deasserts after this ris ing edge 4 At the end of the hold period AOE deasserts unless this bus cycle is followed by another asynchronous read to the same memory space Also A...

Page 270: ... followed by an asyn chronous read cycle to the same bank with timing programmed as setup 2 cycles write access 2 cycles read access 3 cycles hold 1 cycle and transition time 1 cycle Figure 6 3 Asynchronous Read Bus Cycles CLKOUT ADDR 19 1 DATA 15 0 SETUP 2 CYCLES READ ACCESS 2 CYCLES HOLD TRANSITION TIME 1 CYCLE 1 CYCLE AOE ARE AWE 3 0 1 0 ABE AMS ...

Page 271: ...alid See Byte Enables on page 6 18 for more information 2 At the beginning of the write access period AWE asserts 3 At the beginning of the hold period AWE deasserts Figure 6 4 Asynchronous Write and Read Bus Cycles SETUP 2 CYCLES WRITE ACCESS 2 CYCLES HOLD 1 CYCLE SETUP 2 CYCLES READ ACCESS 3 CYCLES HOLD CLKOUT ADDR 19 1 DATA 15 0 TRANSITION TIME D2 BE1 A1 A2 D1 DATA LATCHED 1 CYCLE 1 CYCLE AOE A...

Page 272: ... same memory bank is queued internally the AMC appends the programmed number of memory transition time cycles Adding External Access Extension The ARDY pin is used to insert extra wait states The EBIU starts sampling ARDY on the clock cycle before the end of the programmed strobe period If ARDY is sampled as deasserted the access period is extended The ARDY pin is then sampled on each subsequent c...

Page 273: ...ternal Bus Interface Unit Figure 6 5 Inserting Wait States Using ARDY PROGRAMMED READ ACCESS ACCESS EXTENDED READY SAMPLED ARDY EAD CLKOUT ADDR 19 1 DATA 15 0 X 1 0 READ D SETUP 2 CYCLES 4 CYCLES 3 CYCLES HOLD 1 CYCLE DATA LATCHED ADDRESS AOE ARE AWE ABE AMS ...

Page 274: ...a specific byte can be modified for a 16 bit devices using the ABE 1 0 pins See Table 6 3 The ABE 1 0 pins are both low during all asynchronous reads and 16 bit asynchronous writes When an asynchronous write is made to the upper byte of a 16 bit memory ABE1 0 and ABE0 1 When an asynchronous write is made to the lower byte of a 16 bit memory ABE1 1 and ABE0 0 AMC Programming Model The asynchronous ...

Page 275: ...gates back to the requesting bus master This generates a hardware exception to the core if it is the requester For DMA mastered requests the error is captured in the respective status register If a bank is not fully populated with memory then the memory likely aliases into multiple address regions within the bank This aliasing condition is not detected by the EBIU and no error response is asserted...

Page 276: ...hese four parameters Setup the time between the beginning of a memory cycle AMS x low and the read enable assertion ARE low or write enable asser tion AWE low Read access the time between read enable assertion ARE low and deassertion ARE high Write access the time between write enable assertion AWE low and deassertion AWE high Hold the time between read enable deassertion ARE high or write enable ...

Page 277: ...egister 0 0 0 Asynchronous Memory Global Control Register EBIU_AMGCTL AMBEN 2 0 AMCKEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 Disable CLKOUT for asynchronous memory region accesses 1 Enable CLKOUT for asynchronous memory region accesses Enable asynchronous memory banks 000 All banks disabled 001 Bank0 enabled 010 Bank0 and Bank1 enabled 011 Bank0 Bank1 and Bank2 enabled ...

Page 278: ... completes if ARDY sampled high Bank 1 ARDY enable 0 Ignore ARDY for accesses to this memory bank 1 After access time countdown use state of ARDY to deter mine completion of access Reset 0xFFC2 FFC2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 B0RDYPOL B0TT 1 0 B0ST 1 0 B0RDYEN B0HT 1 0 B0RAT 3 0 B0WAT 3 0 Bank 0 write access time number of cycles AWE is held asserted 0000...

Page 279: ...nsition completes if ARDY sampled high Bank 3 ARDY enable 0 Ignore ARDY for accesses to this memory bank 1 After access time countdown use state of ARDY to deter mine completion of access Reset 0xFFC2 FFC2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 B2RDYPOL B2TT 1 0 B2ST 1 0 B2RDYEN B2HT 1 0 B2RAT 3 0 B2WAT 3 0 Bank 2 write access time number of cycles AWE is held assert...

Page 280: ...2 0x3344 0x5566 0x7788 section SRAM_bank_0 byte2 dest N section L1_code I0 L lo source I0 H hi source I1 L lo dest I1 H hi dest R0 L w I0 P5 N 1 lsetup lp lp LC0 P5 lp R0 L w I0 w I1 R0 L w I1 R0 L Listing 6 2 8 Bit Core Transfers to SRAM Using Byte Mask ABE 1 0 Pins section L1_data_b byte source N 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 section SRAM_bank_0 byte dest N p0 L lo source p0 H hi sourc...

Page 281: ...o a maximum total capacity of 512M bytes of SDRAM Features The EBIU SDC provides a glueless interface with standard SDRAMs Fea tures include I O width 16 bit I O supply 2 5 or 3 3 V Maximum throughput of 266 M bytes second Supports up to 512M byte of SDRAM in external bank Types of 64 128 256 and 512M bit with I O of x4 x8 and x16 Supports SDRAM page sizes of 512 byte 1K 2K and 4K byte Supports mu...

Page 282: ...fresh mode for power savings During hibernate state self refresh mode is supported Supports instruction fetch SDRAM Configurations Supported Table 6 4 shows all possible bank sizes and SDRAM discrete component configurations that can be gluelessly interfaced to the SDC The bank width for all cases is 16 bits Table 6 4 SDRAM Discrete Component Configurations Supported System Size M byte System Size...

Page 283: ...dress into SDRAM To access SDRAM the SDC uses the bank interleaving map scheme which fills each internal SDRAM bank before switching to the next internal bank Since the SDRAMs have four internal banks the entire SDRAM address space is therefore divided into four sub address regions containing the addresses of each internal bank See Figure 6 10 128 64M x 16 64M x 4 4 128 64M x 16 64M x 8 2 128 64M ...

Page 284: ...dress Internal SDRAM bank address L A good understanding of the SDC s address map scheme in con junction with the multibank operation is required to obtain optimized system performance Figure 6 9 Multiplexed SDRAM Addressing Scheme Table 6 5 External Bank Size Encodings EBSZ Bank Size Mbyte Valid SDRAM Addresses 000 16 0x0000 0000 0x00FF FFFF 001 32 0x0000 0000 0x01FF FFFF 010 64 0x0000 0000 0x03F...

Page 285: ...64 For the ADSP BF537 I 0 capabilities of 1 x 16 bit 2 x 8 bit or 4 x 4 bit are given The reason to use a system of 4 x 4 bit vs 2 x 8 bit or 1 x 16 bit is determined by the SDRAM s page size All 3 systems have the same exter nal bank size but different page sizes On one hand the higher the page size the higher the performance On the other hand the higher the page size the higher the hardware layo...

Page 286: ... pins Bank address is output on ADDR 19 18 and should be connected to SDRAM BA 1 0 pins SRAS O SDRAM row address strobe pin Connect to SDRAM s RAS pin SCAS O SDRAM column address strobe pin Connect to SDRAM s CAS pin SWE O SDRAM write enable pin Connect to SDRAM s WE pin ABE 1 0 SDQM 1 0 O SDRAM data mask pins Connect to SDRAM s DQM pins SMS O Memory select pin of external memory bank config ured ...

Page 287: ...stem clock frequency Connect to the SDRAM s CLK pin 1 Pin Types I Input O Output Table 6 7 SDRAM Performance Between Internal Data Memory and SDRAM Type of access Performance DAG access write 1 SCLK cycle per 16 bit word DAG access read 8 SCLK cycles per 16 bit word MemDMA access write 1 SCLK cycle per 16 bit word MemDMA access read 1 1 SCLK cycles per 16 bit word Table 6 8 SDRAM Performance For O...

Page 288: ...g on leak age effects the SDRAM cell needs to be refreshed periodically with the refresh command Row Activation SDRAM accesses are multiplexed which means any first access will open a row page before the column access is performed It stores the row in a row cache called row activation Column Read Write The row s columns represent a page which can be accessed with successive read or write commands ...

Page 289: ...the SDC address the SDRAM L Do not confuse the internal banks which are internal to the SDRAM and are selected with the BA 1 0 pins with the external bank that is enabled by the CS pin Memory Size Since the 2D memory is based on rows and columns the size is mem size rows x columns x internal banks x I O Mbit Burst Length The burst length determines the number of words that the SDRAM device stores ...

Page 290: ...n the SDRAM s mode register during the SDRAM powerup sequence Data I O Mask Function SDRAMs allow a data byte masking capability on writes The mask pins DQM 1 0 are used to block the data input buffer of the SDRAM during write operations SDRAM Commands SDRAM commands are not based on typical read or write strobes The pulsed CS RAS CAS and WE lines determine the command on the rising clock edge by ...

Page 291: ... column address For the write command SDRAM latches the column address Data is also asserted in the same cycle The start address is set according to the column address Precharge Precharge All Command The precharge command closes a specific active page in an internal bank and the precharge all command closes all 4 active pages in all 4 banks Auto refresh command When the SDC refresh counter times o...

Page 292: ... information L Any absolute timing parameter must be normalized to the system clock which allows the SDC to adapt to the timing parameter of the device tMRD This is the required delay between issuing a mode register set and an acti vate command during powerup Dependency system clock frequency SDC setting 3 system clock cycles SDC usage MRS command tRAS This is the required delay between issuing a ...

Page 293: ...irst bank A read or write command Dependency system clock frequency SDC setting 1 7 normalized system clock cycles SDC usage first read write command tRRD This is the required delay between a bank A activate command and a bank B activate command This spec is used for multibank operation Dependency system clock frequency SDC setting tRCD 1 normalized system clock cycles SDC usage multiple bank acti...

Page 294: ...activate commands Dependency system clock frequency SDC setting tRAS tRP normalized system clock cycles SDC usage single column read write command tRFC This is the required delay between issuing successive auto refresh com mands all banks Dependency system clock frequency SDC setting tRAS tRP normalized system clock cycles SDC usage auto refresh exit self refresh command tXSR This is the required ...

Page 295: ...ck frequency SDC setting tREFI normalized system clock cycles RDIV register SDC usage auto refresh command SDC Functional Description The functional description of the SDC is provided in the following sections SDC Operation The AMC normally generates an external memory address which then asserts the corresponding CS select along with RD and WR strobes However these control signals are not used by ...

Page 296: ...equired refresh rate based on the clock fre quency used The refresh counter period is specified with the RDIV field in the SDRAM refresh rate control register To allow auto refresh commands to execute in parallel with any AMC access a separate A10 pin SA10 is provided Figure 6 10 Simplified SDC Architecture A 28 0 DATA LATCH DRIVE BUSY CKE ADSP BF537 BA0 BA1 A10 A 0 9 A 11 12 CLK DQ15 0 D 15 0 DQM...

Page 297: ...k control register The SDC uses no burst mode BL 1 for read and write operations This requires the SDC to post every read or write address on the bus as for non sequential reads or writes but does not cause any performance degra dation For read commands there is a latency from the start of the read command to the availability of data from the SDRAM equal to the CAS latency This latency is always p...

Page 298: ...s with the SDRAM device pins Table 6 10 SDRAM Address Connections for 16 bit Banks External Address Pin SDRAM Address Pin ADDR 19 BA 1 ADDR 18 BA 0 ADDR 16 A 15 ADDR 15 A 14 ADDR 14 A 13 ADDR 13 A 12 ADDR 12 A 11 ADDR 11 Not used SA 10 A 10 ADDR 10 A 9 ADDR 9 A 8 ADDR 8 A 7 ADDR 7 A 6 ADDR 6 A 5 ADDR 5 A 4 ADDR 4 A 3 ADDR 3 A 2 ADDR 2 A 1 ADDR 1 A 0 ...

Page 299: ...o is repeated until all 4 banks A D are opened and results in an effective page size up to 4 pages because no latency causes switching between these open pages compared to 1 page in only one bank at the time Any access to any closed page in any opened bank A D forces a precharge command only to that bank If for example 2 MemDMA channels are pointing to the same internal SDRAM bank this always forc...

Page 300: ...ry DMAs have priority over core accesses For the purposes of this discussion core accesses include both data fetches and instruction fetches Changing System Clock During Runtime All timing specs are normalized to the system clock Since most of them are minimum specs except tREF which is a maximum spec a variation of system clock will on one hand violate a specific spec and on the other hand cause ...

Page 301: ...mpleted 2 Set the SDRAM to self refresh mode by writing a 1 to the SRFS bit of EBIU_SDGCTL 3 Execute the desired PLL programming sequence For details refer to Chapter 20 Dynamic Power Management 4 After the wakeup occurs that signifies the PLL has settled to the new VCO frequency reprogram the SDRAM registers EBIU_SDRRC EBIU_SDGCTL with values appropriate to the new SCLK frequency and assure that ...

Page 302: ...orts low level of SCKE pin even during core reset Setting the SCKELOW bit of VR_CTL keeps the SCKE signal low thus ensuring self refresh mode For details refer to Chapter 20 Dynamic Power Management Shared SDRAM Busmastership can be requested using BR and BG pins To grant busmaster ship to external SDC use the CDDBG bit of EBIU_SDGCTL This occurs asynchronously during self refresh mode because bot...

Page 303: ...s self refresh mode 8 Host deasserts BR pin answered with deassertion of BG pin 9 Programmable flag PFx driven from host will trigger an ISR which clears the SRFS bit of EBIU_SDGCTL and performs a dummy access to exit self refresh mode SDC Commands This section provides a description of each of the commands that the SDC uses to manage the SDRAM interface These commands are initiated automatically ...

Page 304: ... Low High Low Valid address bit Valid Read High High Low High Low High Low CMD Valid Single precharge High High Low Low High Low Don t care Valid Precharge all High High Low Low High Low Low Don t care Write High High Low High Low Low Low CMD Valid Auto refresh High High Low Low Low High Don t care Don t care Self refresh entry High Low Low Low Low High Don t care Don t care Self refresh Low Low D...

Page 305: ...mmand initializes these parameters Burst length 1 bits A 2 0 always 0 Burst type sequential bit A 3 always 0 CAS latency bits A 6 4 programmable in the EBIU_SDGCTL register Bits A 12 7 always 0 After powerup and before executing a read or write to the SDRAM mem ory space the application must trigger the SDC to write the SDRAM s mode register The write of the SDRAM s mode register is triggered by w...

Page 306: ...he extended mode register is a subset of the mode register The EBIU enables programming of the extended mode register during powerup via the EMREN bit in the EBIU_SDGCTL register The extended mode register is initialized with these parameters Partial array self refresh bits A 2 0 bit A 2 always 0 bits A 1 0 programmable in EBIU_SDGCTL Temperature compensated self refresh bits A 4 3 bit A 3 always ...

Page 307: ...te command is executed if the next read write access is in the present active page During the read command the SDRAM latches the column address The delay between activate and read commands is deter mined by the tRCD parameter Data is available from the SDRAM after the CAS latency has been met In the write command the SDRAM latches the column address The write data is also valid in the same cycle T...

Page 308: ...d Precharge All Command The precharge all command is given to precharge all internal banks at the same time before executing an auto refresh All open banks will be auto matically closed This is possible since the SDC uses a separate SA10 pin which is asserted high during this command This command is preceding the auto refresh command Auto Refresh Command The SDRAM internally increments the refresh...

Page 309: ...self refresh exit commands The SDC must issue a series of commands including the self refresh entry command to put the SDRAM into this low power operation and it must issue another series of commands including the self refresh exit command to re access the SDRAM Self Refresh Entry Command The self refresh entry command causes refresh operations to be performed internally by the SDRAM without any e...

Page 310: ...ime to exit self refresh 2 x tRAS tRP L The minimum time between a subsequent self refresh entry and the self refresh exit command is at least tRAS cycles If a self refresh entry command is issued during any MemDMA transfer the SDC satisfies this core request with the minimum self refresh period tRAS The application software should ensure that all applicable clock timing specifications are met bef...

Page 311: ...e precharge command it is used to indicate a precharge all During a bank activate command it outputs the row address bit During read and write commands it is used to disable auto precharge Therefore the SDC uses a separate SA10 pin with these rules L Connect the SA10 pin with the SDRAM s A 10 pin Because the ADSP BF537 uses byte addressing it starts with A 1 The A 11 pin is left unconnected for SD...

Page 312: ... control register EBIU_SDGCTL 5 Perform SDRAM access The SDRS bit of the SDRAM control status register can be checked to determine the current state of the SDC If this bit is set the SDRAM powerup sequence has not been initiated The RDIV field of the EBIU_SDRRC register should be written to set the SDRAM refresh rate The EBIU_SDBCTL register should be written to describe the sizes and SDRAM memory...

Page 313: ...f SCTLE is disabled any access to SDRAM address space generates an internal bus error and the access does not occur externally For more infor mation see Error Detection on page 6 7 Once the PSSE bit in the EBIU_SDGCTL register is set to 1 and a transfer occurs to enabled SDRAM address space the SDC initiates the SDRAM powerup sequence The exact sequence is determined by the PSM bit in the EBIU_SDG...

Page 314: ...ne external bank of 128Mbit 16Mbyte of memory The system s page size is 1024 bytes The same address and control bus feeds both SDRAM devices Figure 6 12 SDRAM System Block Diagram Example 1 SCKE ADSP BF537 A 18 A 19 SA10 ADDR 12 10 1 SDRAM 2 8Mx8 BA0 A 10 SCLK SDQM 0 DATA 15 0 BA1 A 11 9 0 CKE CLK DQM DQ 7 0 SDRAM 1 8Mx8 BA0 A 10 BA1 A 11 9 0 CKE CLK DQM DQ 7 0 DATA 7 0 DATA 15 8 SDQM 1 SWE SCAS S...

Page 315: ...hen buffered SDRAM modules or discrete register buff ers are used to drive the SDRAM control inputs EBUFE should be set to 1 Using this setting adds a cycle of data buffering to read and write accesses Figure 6 13 SDRAM System Block Diagram Example 2 SCKE ADSP BF537 A 18 A 19 SA10 ADDR 12 10 1 SDRAM 3 16Mx4 CLKOUT SDQM 0 DATA 15 0 DQ 3 0 SDRAM 1 16Mx4 DQM DQ 3 0 D 3 0 D 11 8 SDQM 1 SWE SCAS SRAS S...

Page 316: ...h the SDRAM device s required refresh rate The desired delay in number of SDRAM clock cycles between consecu tive refresh counter time outs must be written to the RDIV field A refresh counter time out triggers an auto refresh command to all external SDRAM devices Write the RDIV value to the EBIU_SDRRC register before the SDRAM powerup sequence is triggered Change this value only when the SDC is id...

Page 317: ...obal control register in number of clock cycles This equation calculates the number of clock cycles between required refreshes and subtracts the required delay between bank activate com mands to the same internal bank tRC tRAS tRP The tRC value is subtracted so that in the case where a refresh time out occurs while an SDRAM cycle is active the SDRAM refresh rate specification is guaran teed to be ...

Page 318: ...mable parameters It allows software to control some parameters of the SDRAM The external bank can be configured for a different size of SDRAM It uses the access timing parameters defined in the SDRAM memory global control register EBIU_SDGCTL The EBIU_SDBCTL register should be programmed before powerup and should be changed only when the SDC is idle External bank enable EBE The EBE bit is used to ...

Page 319: ...internal address IA 31 0 as seen from the core or DMA into the row bank column and byte address The bank width in all cases is 16 bits The column address and the byte address together make up the address inside the page Figure 6 15 SDRAM Memory Bank Control Register SDRAM Memory Bank Control Register EBIU_SDBCTL EBSZ 2 0 EBCAW 1 0 EBE SDRAM external bank enable 0 Disabled 1 Enabled SDRAM external ...

Page 320: ...ddress Byte Address 512 11 4 IA 28 27 IA 26 12 IA 11 1 IA 0 512 10 2 IA 28 27 IA 26 11 IA 10 1 IA 0 256 11 4 IA 27 26 IA 25 12 IA 11 1 IA 0 256 10 2 IA 27 26 IA 25 11 IA 0 IA 10 1 256 9 1 IA 27 26 IA 25 10 IA 9 1 IA 0 128 11 4 IA 26 25 IA 24 12 IA 11 1 IA 0 128 10 2 IA 26 25 IA 24 11 IA 10 1 IA 0 128 9 1 1A 26 25 IA 24 10 IA 9 1 IA 0 128 8 5 IA 26 25 IA 24 9 IA 8 1 IA 0 64 11 4 IA 25 24 IA 23 12 I...

Page 321: ...bank Referring to Table 6 4 on page 6 26 the lowest available bank size 16M byte for a device with 8 column addresses has 2 bank address lines IA 23 22 and 13 row address lines IA 21 9 Therefore 1 processor bank address line and 2 row address lines are unused when hooking up to the SDRAM in the example This causes aliasing in the processor s external memory map which results in the SDRAM being map...

Page 322: ...y mapping in the left side of the figure Figure 6 16 Using Small SDRAMs BANK ADDRESS ROW ADDRESS IA22 IA23 IA21 IA20 IA19 0 1 1 UNAVAILABLE COMBINATIONS ARE SHADED 1 X X X 1 X 1 IA23 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 1M BYTE 1M BYTE BLACKFIN MEMORY MAP 0x0000 0000 IA23 1 EXAMPLE 2M...

Page 323: ...tive states and the SDRAM clock is not running The SCTLE bit must be enabled for SDC operation and is enabled by default at reset The CAS latency CL SDRAM tRAS timing TRAS SDRAM tRP timing TRP SDRAM tRCD timing TRCD and SDRAM tWR timing TWR bits should be programmed based on the system clock frequency and the timing specifications of the SDRAM used The SCTLE bit allows software to disable all SDRA...

Page 324: ...esh cycles SDRAM powerup sequence start enable Always reads 0 0 No effect 1 Enables SDRAM powerup sequence on next SDRAM access Reset 0xE008 8849 CL 1 0 PASR 1 0 SCTLE TRAS 3 0 TRP 2 0 TRCD 0 SDRAM tRCD in SCLK cycles 000 Reserved 001 111 1 to 7 cycles Enable CLKOUT SRAS SCAS SWE SDQM 1 0 0 Disabled 1 Enabled SDRAM tRP in SCLK cycles 000 No effect 001 111 1 to 7 cycles SDRAM tRAS in SCLK cycles 00...

Page 325: ...tion on page 6 7 L With careful software control the SCTLE bit can be used in con junction with the SRFS bit to further lower power consumption by freezing the CLKOUT pin However SCTLE must remain enabled at all times when the SDC is needed to generate auto refresh com mands to SDRAM CAS latency CL The CL bits in the SDRAM memory global control register EBIU_SDGCTL select the CAS latency value CL ...

Page 326: ...y internal bank 0 refreshed PASR 11 reserved Internal banks are decoded with the A 19 18 pins L The PASR feature requires careful software control with regard to the internal bank used Bank activate command delay TRAS The TRAS bits in the SDRAM memory global control register EBIU_SDGCTL select the tRAS value Any value between 1 and 15 clock cycles can be selected For example TRAS 0000 No effect TR...

Page 327: ... 1 and 7 clock cycles may be selected For example TRP 000 No effect TRP 001 1 clock cycle TRP 010 2 clock cycles TRP 111 7 clock cycles RAS to CAS delay TRCD The TRCD bits in the SDRAM memory global control register EBIU_SDGCTL select the tRCD value Any value between 1 and 7 clock cycles may be selected For example TRCD 000 Reserved no effect TRCD 001 1 clock cycle TRCD 010 2 clock cycles TRCD 111...

Page 328: ...lly delays the powerup start sequence for 15 SCLK cycles This is useful for multiprocessor systems sharing an external SDRAM If the bus has been previously granted to the other processor before powerup and self refresh mode is used when switching bus ownership then the PUPSD bit can be used to guarantee a sufficient period of inactivity from self refresh to the first Precharge command in the power...

Page 329: ...e the SDRAM pow erup sequence A read or write access must be done to enabled SDRAM address space in order to have the external bus granted to the SDC so that the SDRAM powerup sequence may occur The SDRAM powerup sequence occurs and is followed immedi ately by the read or write transfer to SDRAM that was used to trigger the SDRAM powerup sequence Note there is a latency for this first access to SD...

Page 330: ...en SRFS is set to 1 once the SDC enters an idle state it issues a precharge all command and then issues a self refresh entry com mand If an internal access is pending the SDC delays issuing the self refresh entry command until it completes the pending SDRAM access and any subsequent pending access requests Once the SDRAM device enters into self refresh mode the SDRAM controller asserts the SDSRA b...

Page 331: ...sh mode and returns to auto refresh mode Before exiting self refresh mode with the SRFS bit be sure to enable the CLKOUT pin SCTLE bit If this is not done the SDRAM is unclocked and will not work properly External buffering enabled EBUFE With the total I O width of 16 bits a maximum of 4x4 bits can be connected in parallel in order to increase the system s overall page size To meet overall system ...

Page 332: ...ther than 1 x 16 bits increases the page size by a factor of 4 thus resulting in fewer off page penalties Fast back to back read to write FBBRW The FBBRW bit enables an SDRAM read followed by write to occur on consecutive cycles In many systems this is not possible because the turn off time of the SDRAM data pins is too long leading to bus contention with the succeeding write from the processor Wh...

Page 333: ...rnal memory interface is granted to an external controller If this bit is set to a 1 then the control signals are three stated when bus grant is active Otherwise these signals con tinue to be driven during grant If the bit is set and the external bus is granted all SDRAM internal banks are assumed to have been changed by the external controller This means a precharge is required on each bank prior...

Page 334: ... is 1 the SDC performs self refresh mode SCKE pin 1 Figure 6 18 SDRAM Control Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 SDRAM Control Status Register EBIU_SDSTAT SDSRA SDPUA SDCI SDRS SDEASE W1C SDRAM EAB sticky error status Write 1 to this bit to clear it 0 No error detected 1 EAB access generated an error 0 Will not power up on next SDRAM access SDRAM ...

Page 335: ...cted on the EAB core bus If the SDEASE bit is 1 there were errors detected on the EAB core bus The SDEASE bit is sticky Once it has been set soft ware must explicitly write a 1 to the bit to clear it Writes have no effect on the other status bits which are updated by the SDC only Bus grant status BGSTAT If the BGSTAT bit is 0 the bus is not granted If the BGSTAT bit is 1 the bus is granted SDC Pro...

Page 336: ...lp lp lc0 p5 lp R0 L w I0 w I1 R0 L w I1 R0 L Listing 6 4 8 Bit Core Transfers to SDRAM Using Byte Mask SDQM 1 0 Pins section L1_data_b byte source N 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 section SDRAM byte dest N p0 L lo source p0 H hi source p1 L lo dest p1 H hi dest p5 N lsetup start end lc0 p5 start R0 b p0 z end b p1 R0 byte data masking ...

Page 337: ...CTL R1 P0 bitset R1 bitpos SRFS enter self refresh P0 R1 ssync P0 L lo EBIU_SDSTAT P0 H hi EBIU_SDSTAT R0 P0 ssync self_refresh_status cc bittst R0 bitpos SDSRA poll self refresh status if cc jump self_refresh_status P0 L lo EBIU_SDGCTL P0 H hi EBIU_SDGCTL R1 P0 bitclr R1 bitpos SCTLE disable CLKOUT after approx 20 cycles P0 R1 ssync P5 30000 LSETUP lp lp LC0 P5 lp nop dummy loop R1 P0 bitset R1 b...

Page 338: ...xSDRAM 32Mx16 64Mbytes EBSZ 010 populated SDRAM addresses 0x00000000 0x01FFFFFF internal SDRAM bank A 0x00000000 0x007FFFFF internal SDRAM bank B 0x00800000 0x00FFFFFF internal SDRAM bank C 0x01000000 0x017FFFFF internal SDRAM bank D 0x01800000 0x01FFFFFF powerup PRE REF MRS PSM 0 SCLK 133 MHz tCK 7 5ns min CL 3 CL 3 tRAS 44ns min TRAS 6 tRP 20ns min TRP 3 tRCD 20ns min TRCD 3 tWR 15ns min TWR 2 t...

Page 339: ...0 bitpos SDRS if cc jump skip init_sdram SDRAM Refresh Rate Control Register P0 L lo EBIU_SDRRC P0 H hi EBIU_SDRRC R0 L 0x0406 W P0 R0 L SDRAM Memory Bank Control Register P0 L lo EBIU_SDBCTL P0 H hi EBIU_SDBCTL R0 L 0x0025 W P0 R0 L SDRAM Memory Global Control Register P0 L lo EBIU_SDGCTL P0 H hi EBIU_SDGCTL R0 L 0x998d R0 H 0x8491 P0 R0 ssync wait until executed ...

Page 340: ...SDC Programming Examples 6 84 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 341: ...w The PPI is a half duplex bidirectional port accommodating up to 16 bits of data It has a dedicated clock pin and three multiplexed frame sync pins The highest system throughput is achieved with 8 bit data since two 8 bit data samples can be packed as a single 16 bit word In such a case the earlier sample is placed in the 8 least significant bits LSBs Features The PPI includes these features Half...

Page 342: ...PI port A D converters D A converters LCD panels CMOS sensors Video encoders Video decoders Interface Overview Figure 7 1 shows a block diagram of the PPI Figure 7 1 PPI Block Diagram DATA BUS PPI_CLK 16 BITS 16 DEEP FIFO FS1 PPI_CONTROL PACK UNPACK PPI_COUNT PPI_STATUS PPI_DELAY PPI_FRAME GATE SYNC FS2 FS3 DMA CONTROLLER PAB DAB ...

Page 343: ...condary data signals of SPORT0 If 13 or fewer data lines are required for PPI operation the transmit channel of SPORT0 remains fully functional The three control bits PGSE PGRE and PGTE in the PORT_MUX register control this granularity of signal multiplexing The PPI clock and the three PPI frame sync signals are found on port F The PPI_CLK not only supplies the PPI module itself it also can clock ...

Page 344: ...UX PORTF_FER PORTG_FER PPI D0 PPI data 0 Set bit 0 PG0 PPI D1 PPI data 1 Set bit 1 PG1 PPI D2 PPI data 2 Set bit 2 PG2 PPI D3 PPI data 3 Set bit 3 PG3 PPI D4 PPI data 4 Set bit 4 PG4 PPI D5 PPI data 5 Set bit 5 PG5 PPI D6 PPI data 6 Set bit 6 PG6 PPI D7 PPI data 7 Set bit 7 PG7 PPI D8 PPI data 8 Clear bit 9 PGSE Set bit 8 PG8 PPI D9 PPI data 9 Clear bit 9 PGSE Set bit 9 PG9 PPI D10 PPI data 10 Cle...

Page 345: ...0 RX mode 0 frame syncs internal trigger 0 0 11 11 0 or 1 0 or 1 1 RX mode 1 external frame sync 1 0 00 11 0 or 1 0 or 1 0 RX mode 2 or 3 external frame syncs 3 0 10 11 0 or 1 0 or 1 0 RX mode 2 or 3 internal frame syncs 3 0 01 11 0 or 1 0 or 1 0 RX mode ITU R 656 active field only embed ded 0 00 00 0 or 1 0 0 or 1 RX mode ITU R 656 ver tical blanking only embed ded 0 00 10 0 or 1 0 0 RX mode ITU ...

Page 346: ...ics shown in Figure 7 2 and Figure 7 3 for 525 60 NTSC and 625 50 PAL sys tems The processor supports only the bit parallel mode of ITU R 656 Both 8 and 10 bit video element widths are supported In this mode the Horizontal H Vertical V and Field F signals are sent as an embedded part of the video datastream in a series of bytes that form a control word The Start of Active Video SAV and End of Acti...

Page 347: ...transition of the F bit The odd field is denoted by a value of F 0 whereas F 1 denotes an even field Progressive video makes no distinction between field 1 and field 2 whereas interlaced video requires each field to be handled uniquely because alternate rows of each field combine to create the actual video image Figure 7 2 ITU R 656 8 Bit Parallel Data Stream for NTSC PAL Systems 4 268 280 FOR PAL...

Page 348: ...efinitions are as follows F 0 for field 1 F 1 for field 2 Figure 7 3 Typical Video Frame Partitioning for NTSC PAL Systems for ITU R BT 656 4 LINE 4 FIELD 1 ACTIVE VIDEO FIELD 1 ACTIVE VIDEO FIELD 2 ACTIVE VIDEO FIELD 2 ACTIVE VIDEO FIELD 1 FIELD 2 LINE 266 LINE 313 LINE 625 LINE 3 LINE 1 EAV SAV EAV SAV 1 20 264 283 525 1 23 311 336 624 625 LINE NUMBER LINE NUMBER F H SAV H EAV H SAV H EAV F V V ...

Page 349: ...ble enough to accommodate different row and field lengths In general as long as the incoming video has the proper EAV SAV codes the PPI can read it in In other words a CIF image could be formatted to be 656 compliant where EAV and SAV values define the range of the image for each line and the V and F codes can be used to delimit fields and frames Table 7 3 Control Byte Sequences for 8 bit and 10 b...

Page 350: ...d In this mode the entire incoming bitstream is read in through the PPI This includes active video as well as control byte sequences and ancillary data that may be embedded in horizontal and vertical blanking intervals Figure 7 4 ITU R 656 Input Modes Figure 7 5 ITU R 656 Input Submodes PPIx PPI_CLK PPI CLK 656 COMPATIBLE VIDEOSOURCE ITU R 656 INPUT MODE 8 OR 10 BIT DATA WITH EMBEDDED CONTROL BLAN...

Page 351: ...o portion of a field is of inter est and not any of the blanking intervals The PPI ignores does not read in all data between EAV and SAV as well as all data present when V 1 In this mode the control byte sequences are not stored to memory they are filtered out by the PPI After synchronizing to the start of Field 1 the PPI ignores incoming samples until it sees an SAV L In this mode the user specif...

Page 352: ...ith 0 frame syncs this process can be supported manually Essentially this mode provides a streaming operation from memory out through the PPI Data and control codes can be set up in memory prior to sending out the video stream With the 2D DMA engine this could be performed in a number of ways For instance one line of blanking H V could be stored in a buffer and sent out N times by the DMA controll...

Page 353: ...s missed the current field will only have NUM_ROWS 1 rows but resynchronization will reoccur at the start of the next frame Upon completing reception of an entire field the field status bit is toggled in the PPI_STATUS register This way an interrupt service routine ISR can discern which field was just read in General Purpose PPI Modes The General Purpose GP PPI modes are intended to suit a wide va...

Page 354: ... up to PPI_COUNT again This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process The bottom of Figure 7 6 shows an example of TX mode 1 internal frame sync After PPI_FS1 is asserted there is a latency of 1 PPI_CLK cycle and then there is a delay for the number of PPI_CLK cycles programmed into RX mode 2 or 3 external frame syncs Input Input Input ...

Page 355: ...rity and starts a new line transfer sequence This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process Data Input RX Modes The PPI supports several modes for data input These modes differ chiefly by the way the data is framed Refer to Table 7 2 on page 7 5 for informa tion on how to configure the PPI for each mode Figure 7 6 General Flow for GP Mo...

Page 356: ...that another DMA operation is clearing the first memory buffer for reuse L Due to clock domain synchronization in RX modes with no frame syncs there may be a delay of at least 2 PPI_CLK cycles between when the mode is enabled and when valid data is received There fore detection of the start of valid data should be managed by software 1 2 or 3 External Frame Syncs The frame syncs are level sensitiv...

Page 357: ...ing PPI_FS1 and PPI_FS2 and then reading data into the PPI The PPI_FS3 frame sync provides an indication of which field is currently being transferred but since it is an output it can simply be left floating if not used Figure 7 8 shows a sample application for this mode Figure 7 7 RX Mode External Frame Syncs Figure 7 8 RX Mode Internal Frame Syncs PPI VIDEO SOURCE A D CONVERTER PPIx PPIx PPI_CLK...

Page 358: ...ta transfers will take place immediately synchronized to PPI_CLK See Figure 7 9 for an illustration of this mode L In this mode there is a delay of up to 16 SCLK cycles for 8 bit data or 32 SCLK cycles for 8 bit data between enabling the PPI and transmission of valid data Furthermore DMA must be config ured to transmit at least 16 samples for 8 bit data or 32 samples for 8 bit data 1 or 2 External...

Page 359: ... to Digital to Analog Con verters DACs with a single frame sync The top part of Figure 7 11 shows an example of this type of connection The 3 sync mode is useful for connecting to video and graphics displays as shown in the bottom part of Figure 7 11 A 2 sync mode is implicitly supported by leaving PPI_FS3 unconnected in this case Figure 7 10 TX Mode 1 or 2 External Frame Syncs DATA RECEIVER DATA ...

Page 360: ...o grammed for these signals using the existing TIMERx registers This capability accommodates a wide range of timing needs Note these PWM circuits are clocked by PPI_CLK not by SCLK as during conventional timer PWM operation If PPI_FS2 is not used in the configured PPI mode timer 1 operates as it normally would unrestricted in functionality The state of PPI_FS3 depends completely on the state of PP...

Page 361: ... or timer 1 L It is important to guarantee proper frame sync polarity between the PPI and timer peripherals To do this make sure that if PPI_CONTROL 15 14 b 10 or b 11 the PULSE_HI bit is cleared in TIMER0_CONFIG and TIMER1_CONFIG Likewise if PPI_CONTROL 15 14 b 00 or b 01 the PULSE_HI bit should be set in TIMER0_CONFIG and TIMER1_CONFIG To switch to another PPI mode not involving internal frame s...

Page 362: ...he start of the very first frame after the PPI is enabled It is subsequently ignored In TX modes with external frame syncs the PPI_FS1 and PPI_FS2 pins are treated as edge sensitive inputs In this mode it is not necessary to config ure the timer s associated with the frame sync s as input s or to enable them via the TIMER_ENABLE register Additionally the actual timers them selves are available for...

Page 363: ...er PPI_CLK cycle and this results in reduced bandwidth since no packing is possible The highest throughput is achieved with 8 bit data and PACK_EN 1 packing mode enabled Note for 16 bit packing mode there must be an even number of data elements Configuring the PPI s DMA channel is a necessary step toward using the PPI interface It is the DMA engine that generates interrupts upon com pletion of a r...

Page 364: ...L 1 causes an interrupt when half of the frame has been transferred and again when the whole frame has been transferred Following is the general procedure for setting up DMA operation with the PPI For details regarding configuration of DMA please refer to Chapter 5 Direct Memory Access 1 Configure DMA registers as appropriate for desired DMA operat ing mode 2 Enable the DMA channel for operation 3...

Page 365: ...RAM Y_COUNT AND Y_MODIFY N START WRITE PORTF_FER AND PORTG_FER GP Y N Y WRITE PORT_MUX PROGRAM PPI_FRAME FS N PROGRAM PPI_DELAY EXTERNAL TRIGGER N Y PROGRAM PPI_COUNT INTERNAL FS N Y PROGRAM TIMER S LINKED WITH FS Y WRITE DMAx_CONFIG TO ENABLE DMA WRITE PPI_CONTROL TO ENABLE PPI INTERNAL FS N Y WRITE TIMER_ENABLE TO ENABLE TIMERS END ...

Page 366: ...respectively This provides a mechanism to connect to data sources and receivers with a wide array of control signal polarities Often the remote data source receiver also offers configurable signal polarities so the POLC and POLS bits simply add increased flexibility The DLEN 2 0 field is programmed to specify the width of the PPI port in any mode Note any width from 8 to 16 bits is supported with ...

Page 367: ...ields 1 and 2 In RX mode with external frame sync when PORT_CFG 11 0 External trigger 1 Internal trigger 0 PPI_FS1 and PPI_FS2 are treated as rising edge asserted 1 PPI_FS1 and PPI_FS2 are treated as falling edge asserted SKIP_EN Skip Enable SKIP_EO Skip Even Odd In ITU R 656 and GP Input modes 0 Skip odd numbered elements 1 Skip even numbered elements In ITU R 656 and GP Input modes 0 Skipping di...

Page 368: ... RX modes with external frame syncs The PACK_EN bit only has meaning when the PPI port width selected by DLEN 2 0 is 8 bits Every PPI_CLK initiated event on the DMA bus that is an input or output operation handles 16 bit entities In other words an input port width of 10 bits still results in a 16 bit input word for every PPI_CLK the upper 6 bits are 0s Likewise a port width of 8 bits also results ...

Page 369: ... data in memory to be transported out through the PPI via DMA 0xFACE CAFE 0xFA and 0xCA are the two Most Significant Bits MSBs of their respective 16 bit words With PACK_EN set This is DMAed to the PPI 0xFACE 0xCAFE This is transferred out through the PPI configured for an 8 bit port width note LSBs are transferred first 0xCE 0xFA 0xFE 0xCA With PACK_EN cleared This is DMAed to the PPI 0xFACE 0xCA...

Page 370: ... 1 0 interacts with other bits in PPI_CONTROL to determine the PPI operating mode The PORT_EN bit when set enables the PPI for operation L Note that when configured as an input port the PPI does not start data transfer after being enabled until the appropriate synchroniza tion signals are received If configured as an output port transfer including the appropriate synchronization signals begins as ...

Page 371: ...F in ITU R 656 modes or PPI_FS3 in other RX modes It is valid for input modes only The state of FLD reflects the current state of the F or PPI_FS3 signals In other words the FLD bit always reflects the current video field being processed by the PPI The OVR bit is sticky and indicates when set that the PPI FIFO has over flowed and can accept no more data A FIFO overflow error generates a PPI error ...

Page 372: ...gnifies that a horizontal tracking overflow has occurred where the value in PPI_COUNT was reached before a new SAV code was received This flag does not apply for non ITU R 656 modes in this case once the value in PPI_COUNT is reached the PPI simply stops counting until receiving the next PPI_FS1 frame sync The LT_ERR_UNDR flag signifies that a horizontal tracking underflow has occurred where a new...

Page 373: ...o interrupt 1 Frame Track Error interrupt occurred Reset 0x0000 Used only in ITU R 656 modes 0 No uncorrected preamble error has occurred 1 Preamble error detected but not corrected 0 No interrupt 1 FIFO Overflow Error interrupt occurred UNDR FIFO Underrun W1C 0 No interrupt 1 FIFO Underrun Error interrupt occurred 0xFFC0 1004 0 No horizontal tracking underflow error 1 PPI_FS1 or SAV code received...

Page 374: ...ster holds the number of samples to read into the PPI per line minus one For TX modes it holds the number of samples to write out through the PPI per line minus one The register itself does not actually decrement with each transfer Thus at the begin ning of a new line of data there is no need to rewrite the value of this register For example to receive or transmit 100 samples through the PPI set P...

Page 375: ...ly to determine the original frame start each time the PPI is enabled It is ignored on every subsequent field and frame and its state high or low is not important except during the original frame start If the start of a new frame or field for ITU R 656 mode is detected before the number of lines specified by PPI_FRAME have been transferred a frame track error results and the FT_ERR bit in PPI_STAT...

Page 376: ...first frame after the PPI is enabled It is subsequently ignored When using RX mode with 3 external frame syncs and only 2 syncs are needed configure the PPI for three frame sync operation and provide an external pull down to GND for the PPI_FS3 pin Programming Examples As shown in the data transfer scenario in Figure 7 18 on page 7 40 the PPI can be configured to receive data from a video source i...

Page 377: ...ADDR R0 L rx_buffer R0 H rx_buffer P0 L lo DMA0_START_ADDR P0 H hi DMA0_START_ADDR P0 R0 DMA0_CONFIG R0 L DI_EN WNR P0 L lo DMA0_CONFIG P0 H hi DMA0_CONFIG W P0 R0 L DMA0_X_COUNT R0 L 256 P0 L lo DMA0_X_COUNT P0 H hi DMA0_X_COUNT W P0 R0 L DMA0_X_MODIFY R0 L 0x0001 P0 L lo DMA0_X_MODIFY P0 H hi DMA0_X_MODIFY W P0 R0 L ssync config_dma END RTS ...

Page 378: ...PPI_CONTROL P0 L lo PPI_CONTROL P0 H hi PPI_CONTROL R0 L 0x0004 W P0 R0 L ssync config_ppi END RTS Listing 7 3 Enable DMA DMA0_CONFIG P0 L lo DMA0_CONFIG P0 H hi DMA0_CONFIG R0 L W P0 bitset R0 0 W P0 R0 L ssync Listing 7 4 Enable PPI PPI_CONTROL P0 L lo PPI_CONTROL P0 H hi PPI_CONTROL R0 L W P0 bitset R0 0 W P0 R0 L ssync ...

Page 379: ...he exact PPI mode and settings for example transfer field 1 only transfer odd and even elements The top part of the diagram shows a situation appropriate for as an exam ple JPEG compression The first N rows of video are DMAed into L1 memory via the PPI Once in L1 the compression algorithm operates on the data and sends the compressed result out from the processor via the SPORT Note that no SDRAM a...

Page 380: ...s between SDRAM and L1 memory for intermediate processing stages Finally the compressed video exits the processor via the SPORT Figure 7 18 PPI Possible Data Transfer Scenarios PPI SDRAM L1 MEMORY L1 MEMORY SPORT DMA DMA DMA DMA DMA PPI VIDEO SOURCE VIDEO SOURCE SPORT COMPRESSED VIDEO VIDEO DATA AND CONTROL ...

Page 381: ...concludes with a programming model consolidated register definitions and programming examples Overview The Ethernet MAC provides a 10 100Mbit s Ethernet interface compli ant to IEEE Std 802 3 2002 between an MII Media Independent Interface and the Blackfin peripheral subsystem Features The Ethernet MAC includes these features Independent DMA driven RX and TX channels MII RMII interface 10Mbit s an...

Page 382: ...ace SIF block contains FIFOs for RX and TX data and handles the synchronization of data between the MAC RX and TX data streams and the Blackfin DMA controller The System Interface Registers SIF_REG block is an interface from the Blackfin Peripheral Access Bus PAB to the internal registers in the MAC This block also generates the Ethernet event interrupt and supports the PHYINT pin by which the PHY...

Page 383: ...tes chapter of the ADSP BF53x BF56x Blackfin Processor Programming Reference The Address Check ACH block checks the destination address field of all incoming packets Based on the type of address filtering selected this indicates the result of the address checking to the MAC block Figure 8 1 Ethernet MAC Block Diagram EXTERNAL PHY DMA PAB RX FIFO DAB MII RMII PADS MII MANAGEMENT MIM POWER MANAGEMEN...

Page 384: ...BUF pin See Figure 8 2 The CLKBUF signal is not generated by a PLL and supports jitter and stabil ity functions comparable to XTAL The CLKBUF pin is enabled by the PHYCLKOE bit in the VR_CTL register See Chapter 20 Dynamic Power Management for more information A 25 MHz clock whether driven with the CLKBUF pin or an external crys tal should be used with an MII PHY A 50 MHz clock source is required ...

Page 385: ...net MAC Pins Pin Name MII Multiplexed Name MII Input Output RMII Multiplexed Name RMII Input Output Description PH0 MII TXD0 O RMII TXD0 O Ethernet MII or RMII transmit D0 PH1 MII TXD1 O RMII TXD1 O Ethernet MII or RMII transmit D1 PH2 MII TXD2 O Ethernet MII transmit D2 PH3 MII TXD3 O Ethernet MII transmit D3 PH4 MII TXEN O RMII TXEN O Ethernet MII or RMII transmit enable PH5 MII TXCLK I RMII REF...

Page 386: ...eral s control and status registers All data transfers to and from the peripheral are handled by the Blackfin DMA controller and take place via the DAB PH10 MII RXD2 I Ethernet MII receive D2 PH11 MII RXD3 I Ethernet MII receive D3 PH12 MII RXDV I Ethernet MII receive data valid PH13 MII RXCLK I Ethernet MII receive clock PH14 MII RXER I RMII RXER I Ethernet MII or RMII receive error PH15 MII CRS ...

Page 387: ...te 1 Either the receiver or transmitter is enabled RE or TE 1 2 During an MII Management transfer on MDC MDIO 3 During a core access to an MAC control status register 4 While PHY interrupts are enabled in the MAC PHYIE in the EMAC_SYSCTL register is set Description of Operation The following sections describe the operation of the MAC Protocol The Ethernet MAC complies with IEEE Std 802 3 2002 The ...

Page 388: ...rotocol for 16 bit read and write accesses to PHY registers via the MDC and MDIO signals under control of the MAC PHY devices may not directly initiate MDIO transfers Standard PHY control and status registers provide device capability status bits for example auto negotiation duplex modes 10 100 speeds and protocols device status bits for example auto negotiation complete link status remote fault a...

Page 389: ... of device capabilities in PHY status registers Figure 8 3 Station Management Read Figure 8 4 Station Management Write IDLE MDC TA REGAD IDLE ST PHYAD DATA PREAMBLE OP MDIO DRIVER MAC PHY D D D D D D D D D D D D D D D D 15 0 Z A A A A A R R R R R 4 3 2 1 0 4 3 2 1 0 IDLE MDC TA REGAD IDLE ST PHYAD DATA PREAMBLE OP MDIO DRIVER MAC D D D D D D D D D D D D D D D D 15 0 A A A A A R R R R R 4 3 2 1 0 4...

Page 390: ...s The EMAC_STADAT register holds the 16 bit data for read or write transfers The EMAC_STAADD register supports several functions It commands the access writes to it may initiate station management transfers provided the STABUSY bit is set and provided that the interface is not already busy It selects the addressed device register and direction of the access It provides mode controls for MDIO pream...

Page 391: ...takes place via bidirectional descriptor based DMA The element size for any DMA transfer to and from the Ethernet MAC is restricted to 32 bits In the receive case a queue or ring of DMA descriptor pairs are used as illus trated in Figure 8 5 In the figure data descriptors are labeled with an A and status descriptors are labeled with a B Figure 8 5 Ethernet MAC Receive DMA Operation XXXX Active DMA...

Page 392: ...eck sum words Status words written by the MAC after frame reception have the same format as the current RX frame status register and always have the receive complete bit set to 1 If the driver software initial izes the length status words to 0 it can reliably interrogate poll an RX frame s length status word to determine if the DMA transfer of the data buffer is complete Alternatively status descr...

Page 393: ...tination MAC address source MAC address and length type field the Ethernet payload and the Frame Check Sequence FCS checksum but not the preamble If the RXDWA bit in EMAC_SYSCTL is 1 then the first 16 bit word is all zero to pad the frame The data written includes all complete bytes for which the received data valid ERxDV pin on the MII interface was asserted after but not including the start of f...

Page 394: ...If the HM bit is 1 and if the DA is a multi cast address which matches the hash table the address filter is set to true 4 PAM pass all multicast If the PAM bit is 1 and the DA is any multicast address the address filter is set to true 5 PR promiscuous If the PR bit is 1 the address filter is set to true regardless of the frame DA 6 FLCE flow control enable If the FLCE bit in the flow control regis...

Page 395: ...BF bit is 0 and the frame has any type of error except a frame fragment error the frame filter is set to false This rejects any frame for which any of these status bits are set frame too long alignment error frame CRC error length error or unsupported control frame The frame filter does not reject frames on the basis of the out of range length field status bit Note that this step may reject MAC co...

Page 396: ...o memory Instead the current DMA data and status buffers are recycled for the next RX frame For all frames that pass both the address and frame filters both data and status are written to memory via DMA Control Frames If the FLCE flow control enable bit is set MAC control frames with the control type 88 08 whose DAs match either the station MAC address with inverse filtering disabled or the global...

Page 397: ...ses set IFE and DBF and clear HU HM PAM and PR in the operating mode register RX Automatic Pad Stripping If the ASTP bit in the MAC operating mode register is set the pad bytes and FCS are stripped from any IEEE type frame which was lengthened padded to reach the minimum Ethernet frame length of 64 bytes This applies to frames where the Ethernet length type field is less than 46 bytes since the Et...

Page 398: ... data with value 0x0000 resulting in a frame payload aligned on an even 16 bit boundary See Figure 8 6 RX DMA Buffer Structure The length of each RX DMA buffer must be at least 1556 0x614 bytes This is the maximum number of bytes that the MAC can deliver by DMA on any receive frame Frames longer than the 1556 byte hardware limit Figure 8 6 RX DMA Data Alignment 1 0 DATA BYTE D EVEN WORD ALIGNMENT ...

Page 399: ...s contains a frame status word and may also contain two 16 bit IP checksum words if the RXCKS bit in the MAC system control register is set To synchronize RX DMA and software the RX_COMP semaphore bit may be used in the RX frame status word This word is always the last word written via DMA in both status buffer formats so a transition from 0 to 1 as seen by the processor always means that both the...

Page 400: ...es not pass the frame filter neither the frame data nor the status are delivered by DMA into the RX frame status buffer The priority order for determination of the receive status code is shown in Table 8 4 2 16 IP payload checksum 4 32 RX frame status Same format as the current RX frame status register Table 8 4 RX Receive Status Priority Priority Bit Bit Name IEEE receive status Condition 1 20 DM...

Page 401: ... zero is stored in the least significant byte One s complement addition can be done in ordinary unsigned integer arithmetic by adding the two numbers followed by adding the carry out bit value in at the least significant bit This gives one s complement 4 14 Frame too long Frame too long The frame size was more than the maxi mum allowable frame size 1518 1522 or 1538 bytes for normal VLAN1 or VLAN2...

Page 402: ...o the raw hardware generated checksum Similarly the Ethernet FCS at the end of the frame should be deducted These adjustments must be made before the IP checksum can be validated RX DMA Direction Errors The RX DMA channel halts immediately after any transfer that sets the RXDMAERR bit in the EMAC_SYSTAT register This bit is set if an RX data or RX status DMA request is granted by the RX DMA channe...

Page 403: ...eared Since the MAC may have lost synchronization with the DMA descriptor queue the RX channel must be disabled in order to clear the error condition To clear the error and resume operation perform these steps 1 Disable the MAC RX channel clear the RE bit in the EMAC_OPCODE register 2 Disable the DMA channel 3 Clear the RXDMAERR bit in the EMAC_SYSSTAT register by writing 1 to it 4 Reconfigure the...

Page 404: ... buffer which is written via DMA at the end of the frame The descriptor XCOUNT field should be set to 0 because the MAC controls the ter mination of the status buffer DMA The driver software should initialize the status words to zero in advance Status words written by the MAC after frame reception have the same format as the current TX frame status register and always have the transmit complete bi...

Page 405: ...in the first 64 bytes of MII transmission however the MAC does not discard any of the data in its 96 byte TX FIFO until the first 64 bytes have been successfully transmitted If a collision occurs during this colli sion window and if retry is enabled DRTY 0 the MAC rewinds its FIFO pointer back to the start of the frame data and begins transmission again No redundant DMA transfers are performed in ...

Page 406: ...ansfer is trun cated Only 1543 0x607 are transmitted on the MII Status The MAC transfers the frame status into the status buffer Interrupt Upon completion the DMA may issue an interrupt if the descriptor was programmed to do so The DMA then advances to the next data descriptor if any Figure 8 8 shows an alternative descriptor structure The frame length value and Ethernet MAC header are separated f...

Page 407: ...and the XCOUNT field of the status descriptor should be set to 0 The data after the first 88 bytes must all be contained in the data buffer of the last descriptor in the packet Multi descriptor data formatting is not supported if retry is enabled upon late collisions LCRTE 1 in the MAC operating mode register The LCRTE bit must be 0 in order to use multiple DMA descriptors for transmit TX DMA Data...

Page 408: ...lly retry the frame or to discard the frame If the LCRTE bit in the MAC operating mode register is set the MAC issues a restart command to the TX DMA channel and resets the DMA current address pointer to the start of the current DMA descriptor This requires the frame data to be entirely contained in a single DMA descriptor Figure 8 9 TX DMA Data Alignment 1 0 PAD BYTE EVEN WORD ALIGNMENT TXDWA 1 P...

Page 409: ... register and is arranged so that exactly one status bit is asserted for each of the possible transmit status codes defined in IEEE 802 3 section 4 3 2 The priority order for determination of the transmit status code is shown in Table 8 6 Table 8 6 TX Transmit Status Priority Priority Bit Bit Name IEEE transmit status Condition 1 4 DMA underrun Undefined The frame was not completely delivered by D...

Page 410: ...re debugging the TX DMA channel guaran tees that the last transfer to occur is the one with the direction error On an error usually the current frame is corrupted Any later frames in the descriptor queue are not sent until the error is cleared Since the MAC may have lost synchronization with the DMA descriptor queue the TX channel must be disabled in order to clear the error condition To clear the...

Page 411: ... to an INT output of the external PHY if applicable Many PHY devices provide such a pin sometimes called MDINT or INTR PHYs with interrupt capability may be pro grammed in advance via the MII management interface MDC MDIO to assert the INT pin asynchronously upon detect ing various conditions Examples of INT conditions include link up remote fault link status change auto negotiation complete and d...

Page 412: ...e Remote Wake up Filters on page 8 35 Magic Packet detected see Magic Packet Detection on page 8 34 Any of the RX or TX frame status interrupts Examples of these interrupts include frame received any frame Broad cast frame received VLAN1 frame received and good frame received which includes passing the address filters For example the MAC could be programmed to wake the system upon receiving a fram...

Page 413: ...er the MPKE magic packet wake enable or RWKE remote wakeup frame enable bits in the MAC wakeup frame control and status register EMAC_WKUP_CTL 3 Clearing the capture wakeup frame CAPWKFRM bit in EMAC_WKUP_CTL When in the wake detect only state the MAC receiver disables its DMA interface and does not request any DMA transfers whether data or status Instead the MAC receiver processes good incoming f...

Page 414: ...criptors allocated by the processor prior to entering the sleep state Once the last receive frame has been filled the DMA channel pauses and if any further frames are received beyond the capacity of the MAC RX FIFO a DMA overrun occurs Note that if the last RX DMA descriptor was programmed to signal an interrupt the ADSP BF536 ADSP BF537 wakes from sleep after that frame was received Magic Packet ...

Page 415: ...re 8 11 These filters are enabled by setting the RWKE remote wakeup enable bit in the EMAC_WKUP_CTL register Each filter works in parallel simultaneously examining each incoming frame for a specific byte pattern Each pattern is described by a byte offset to the start of the pattern within the frame a 32 bit byte mask selecting bytes at that offset to include in the pattern and a CRC 16 hash value ...

Page 416: ...ables all four filters 2 The enable wakeup filter N bit in the EMAC_WKUP_FFCMD register must be set to 1 to enable filter N 3 The wakeup filter N address type bit in the EMAC_WKUP_FFCMD register selects whether the target frame is unicast if 0 or multi cast if 1 4 The 8 bit pattern offset N field in the wakeup frame filter offsets register EMAC_WKUP_FFOFF selects the starting byte offset for the t...

Page 417: ...offset and mask registers Good frames whose CRC 16 value matches the specified value at the end of the selected pattern window will cause a wake up event at the end of the frame Good wake up frames exclude frame too short error frame too long error alignment error FCS error PHY error and length error conditions Figure 8 11 Remote Wakeup Filters SELECTED BYTES SELECT IF 1 CRC 16 0 EMAC_WKUP_FFOFF O...

Page 418: ...pecified the single byte 0x12 or 0100_1000 LSB first the calculation of the wakeup CRC_16 is per formed as shown in Table 8 7 G polynomial 1000 0000 0000 0101 Ethernet Event Interrupts The Ethernet event interrupt is signalled to indicate that any or all of the conditions listed below are pending Figure 8 12 shows the Ethernet event interrupts In the ADSP BF536 and ADSP BF537 the Ethernet event Ta...

Page 419: ...MA6 SPORT1 RX DMA7 SPI DMA8 UART0 RX DMA9 UART0 TX DMA10 UART1 RX DMA11 UART1 TX 1 2 3 4 5 6 7 PLL WAKEUP RTC DMA0 PPI WAKE U 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SIC_ISR SIC_IWR SIC_IMASK TWI CAN RX CAN TX TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 PORTF IRQ B MDMA0 MDMA1 PORTF IRQ A PORTG IRQ A WATCHDOG PORTG IRQ B DMA1 MAC RX PORTH IRQ A DMA2 MAC TX...

Page 420: ...s maximum value that is transitions from 0x7FFF FFFF to 0x8000 0000 the corresponding bit in the MMC RX interrupt status register is set An MMC interrupt is asserted whenever either the logical AND of the MMC RX interrupt status register and the MMC RX interrupt enable register is nonzero or the logical AND of the MMC TX interrupt status register and the MMC TX interrupt enable register is nonzero...

Page 421: ...MA channel but the DMA is programmed to transfer in the wrong memory read direction This could indicate a software problem in managing the RX DMA descriptor queue This interrupt is non maskable in the MAC and must always be handled This condition is cleared by writing a 1 to the RXDMAERR bit in the MAC system status register TX DMA direction error detected This bit is set if a TX data or status DM...

Page 422: ...ister is set if the corresponding bit in the RX current frame status register is set oth erwise the bit in the RX sticky frame status register keeps its prior value The RX frame status interrupt enable register is continuously bitwise ANDed with the contents of the RX sticky frame status register and then all of the resulting bits are ORed together to produce the RX frame status interrupt conditio...

Page 423: ...up and Shutdown After the TE bit in the EMAC_OPMODE register is cleared the TX current frame status register the TX sticky frame status register and the TX frame status interrupt enable register hold their last state Of course the two writable registers can still be written In order to not confuse status from old and new frames the TX current frame status register and the TX sticky frame status re...

Page 424: ...iven MMC counter is frozen it is suggested not to intentionally place MMC counter read instructions in positions that result in frequent speculative reads which are not ultimately executed For example MMC counter reads should not be placed in the shadow of fre quently mispredicted flow of control operations a Continuous polling of any MMC register is not recommended The MMC update process requires...

Page 425: ...each bit that is set read the corresponding MMC counter using CCOR clear counter on read mode and add the result to the software main tained counter As an option if the CROLL bit is set to 1 the ISR can check the count value to see if it is less than 0x8000 0000 This would indi cate that the counter has somehow incremented beyond the maximum value 0xFFFF FFFF and wrapped around to zero while the i...

Page 426: ...ing Model The following sections describe the Ethernet MAC programming model for a typical system The initialization sequence can be summarized as follows 1 Configure MAC MII pins Multiplexing scheme CLKBUF 2 Configure interrupts 3 Configure MAC registers MAC address MII station management 4 Configure PHY 5 Receive and transmit data through the DMA engine Configure MAC Pins The first step is to co...

Page 427: ... PLL programming sequence Configure Interrupts Next the MAC interrupts and MAC DMA interrupts need to be config ured to properly Interrupt service routines should be installed to handle all applicable events Refer to Figure 8 12 on page 8 39 for a graphical representation of how event signals are propagated through the interrupt controller The status of the MAC interrupts can be sensed with the EM...

Page 428: ... for the channels corresponding to the Ethernet MAC transfers should be unmasked and a corresponding ISR should be installed if a polling tech nique is not used Configure MAC Registers After the interrupts are set up correctly the MAC address registers and the MII protocol must be initialized MAC Address Set the MAC address by writing to the EMAC_ADDRHI and EMAC_ADDRLO reg isters Since the MAC add...

Page 429: ...eamble enable and interrupt enable 4 Do not initiate another read or write access until STABUSY reads 0 or until the station management done interrupt if enabled has been received Accesses attempted while STABUSY 1 are discarded To perform a station management read transfer 1 Initialize MDCDIV 2 Write EMAC_STAADD with the PHY address register address STAOP 0 STABUSY 1 and desired selections for pr...

Page 430: ...y also be set up to assert an interrupt on certain conditions such as a change of the link status Receive and Transmit Data Data transferred over the MAC DMA must be handled with a descrip tor based DMA queue Refer to Figure 8 5 on page 8 11 and Figure 8 7 on page 8 24 for a graphical representation of a receive queue and trans mit queue respectively An Ethernet frame header is placed in front of ...

Page 431: ...DE Completion can be signaled by inter rupts or by polling the DMA status registers Transmitting Data To transmit data memory buffers must be allocated to construct a queue of DMA data and status descriptors The first 16 bit word of the data buffers is written to signify the number of bytes in the frame The DMA engine is then configured through the DMA_CONFIG register After the DMA is set up the M...

Page 432: ...PMODE MAC operating mode Enables the Ethernet MAC transmit ter EMAC_ADDRLO MAC address low Used with EMAC_ADDRHI to set the MAC address EMAC_ADDRHI MAC address high Used with EMAC_ADDRLO to set the MAC address EMAC_HASHLO MAC multicast hash table low Used with EMAC_HASHHI to hold the multicast hash table EMAC_HASHHI MAC multicast hash table high Used with EMAC_HASHLO to hold the multicast hash tab...

Page 433: ...filter CRC0 1 EMAC_WKUP_FFCRC1 MAC wakeup frame filter CRC2 3 System Interface Register Group EMAC_SYSCTL MAC system control EMAC_SYSTAT MAC system status EMAC_RX_STAT Ethernet MAC RX current frame status EMAC_RX_STKY Ethernet MAC RX sticky frame status EMAC_RX_IRQE Ethernet MAC RX frame status interrupt enable EMAC_TX_STAT Ethernet MAC TX current frame status EMAC_TX_STKY Ethernet MAC TX sticky f...

Page 434: ...t Counter Registers MMR Address Register Name IEEE Name IEEE 802 3 Reference Description 0xFFC0 3100 EMAC_RXC_OK FramesReceivedOK 30 3 1 1 5 Holds a count of frames that are suc cessfully received This does not include frames received with frame too long FCS length or align ment errors or frames lost due to inter nal MAC sublayer DMA FIFO errors This also excludes frames with frame too short error...

Page 435: ...do not pass the address filter 0xFFC0 310C EMAC_RXC_OCTET OctetsReceivedOK 30 3 1 1 14 Holds a count of data and padding octets in frames that are successfully received This does not include octets in frames received with frame too long FCS length or alignment errors or frames lost due to internal MAC sub layer errors This also excludes frames with frame too short errors or which do not pass the a...

Page 436: ...h frame too long FCS length or alignment errors or frames lost due to internal MAC sublayer error This also excludes frames with frame too short errors or that do not pass the address filter 0xFFC0 311C EMAC_RXC_BROAD BroadcastFramesReceivedOK 30 3 1 1 22 Holds a count of frames that are suc cessfully received and are directed to the broadcast group address This does not include frames received wi...

Page 437: ...s frames with frame too short errors less than the minimum unpadded MAC client data size or that do not pass the address fil ter 0xFFC0 3124 EMAC_RXC_LNERRO OutOfRangeLengthField 30 3 1 1 24 Holds a count of frames with a Length field value greater than the maximum allowed LLC data size This also excludes frames with frame too short errors or that do not pass the address filter 0xFFC0 3128 EMAC_RX...

Page 438: ...he device This counter is incremented when a receive frame function call returns a valid frame with a length type field value equal to the reserved type and with an opcode for a function that is not sup ported by the device Only opcode 00 01 pause is supported by the Ethernet MAC 0xFFC0 3134 EMAC_RXC_PAUSE PAUSEMACCtrlFramesReceived 30 3 4 3 Holds a count of MAC control frames passed by the MAC su...

Page 439: ...ign ment errors frames lost due to internal MAC sublayer error or that do not pass the address filter 0xFFC0 3144 EMAC_RXC_SHORT FramesLenLt64Received No IEEE reference Holds a count of all frame fragments detected with frame too short errors length 64 bytes regardless of address filtering or of any other errors in the frame 0xFFC0 3148 EMAC_RXC_EQ64 FramesLenEq64Received No IEEE reference Holds a...

Page 440: ...amesTransmittedOK 30 3 1 1 2 Holds a count of frames that are suc cessfully transmitted This counter is incremented when the transmit status is reported as transmit OK 0xFFC0 3184 EMAC_TXC_1COL SingleCollisionFrames 30 3 1 1 3 Holds a count of frames that are involved in a single collision and are subsequently transmitted successfully This counter is incremented when the result of a transmission i...

Page 441: ...194 EMAC_TXC_LATECL LateCollisions 30 3 1 1 10 Holds a count of times that a collision has been detected later than one slot time from the start of the frame trans mission A late collision is counted twice both as a collision and as a late collision This counter is incremented when the number of late collisions detected in transmission of any one frame is nonzero 0xFFC0 3198 EMAC_TXC_XS_COL Frames...

Page 442: ...rame without collision 0xFFC0 31A4 EMAC_TXC_UNICST UnicastFramesXmittedOK No IEEE reference Holds a count of frames counted by the EMAC_TXC_OK register that are not counted by the EMAC_TXC_MULTI or the EMAC_TXC_BROAD register 0xFFC0 31A8 EMAC_TXC_MULTI MulticastFramesXmittedOK 30 3 1 1 18 Holds a count of frames that are suc cessfully transmitted to a group desti nation address other than broadcas...

Page 443: ...count of all frames whose transmission has been attempted regardless of success Each frame is counted only once regardless of the number of retry attempts 0xFFC0 31BC EMAC_TXC_ALLOCT OctetsTransmittedAll No IEEE reference Holds a count of all octets in all frames whose transmission has been attempted regardless of success Each frame s length is counted only once regardless of the number of retry a...

Page 444: ...1 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC Operating Mode Register EMAC_OPMODE RE Receiver Enable Reset 0x0000 0000 ASTP Enable Automatic Pad Stripping HU Hash Filter Unicast Addresses PAM Pass All Multicast Mode PSF Pass Short Frames PBF Pass Bad Frames DBF Disable Broadcast Frame Reception IFE Inverse Filtering PR Promiscuous Mode DC Deferred Check BOLMT 1 0 TX Back Off Limit L...

Page 445: ...l loopback not enabled Full duplex mode FDMODE 1 Full duplex mode selected 0 Half duplex mode selected RMII port speed selector RMII_10 When the interface is configured for RMII operation software must query the PHY after any automatic negotiation to determine the link speed and set the RMII port speed selector accordingly This is because in RMII mode the REFCLK input is always a con stant speed r...

Page 446: ...ed 0 TX retry on late collision not enabled Disable TX retry on collision DRTY 1 TX retry on collision disabled 0 TX retry on collision not disabled TX back off limit BOLMT 1 0 This field sets an upper bound on the random back off interval time before the MAC resends a packet in the event of a collision The bound can be set to 1 15 255 or 1023 slot times 1 slot time 128 MII clock cycles Thus varyi...

Page 447: ...II clocks See IEEE 802 3 section 5 2 4 1 for more information 1 Enables the MAC to abort transmission of frames that encoun ter excessive deferral 0 The MAC cannot abort transmission of frames due to excessive deferral Disable automatic TX CRC generation DTXCRC 1 Automatic TX CRC generation is disabled 0 Automatic TX CRC generation is enabled Four CRC bytes are appended to the frame data Disable a...

Page 448: ...rame filters and causes all frames or frame fragments to be transferred to memory by DMA 0 Does not override filters Pass short frame PSF 1 Short frames are not rejected by the frame filter 0 The frame filter rejects frames with frame too short errors runt frames or frames with total length less than 64 bytes not including preamble Pass bad frames PBF 1 Pass bad frames enabled 0 The frame filter r...

Page 449: ...verse filtering not enabled Promiscuous mode PR 1 Promiscuous mode enabled the address filter accepts all addresses 0 Promiscuous mode not enabled Pass all multicast mode PAM 1 All multicast frames are added to the set of addresses passed by the address filter 0 Do not pass all multicast frames Hash filter multicast addresses HM 1 Adds multicast addresses that match the hash table to the set of ad...

Page 450: ...an 64 bytes If ASTP 1 both the pad and the FCS bytes are removed from the received data 1 Automatic pad stripping is enabled 0 Automatic pad stripping is not enabled Receiver enable RE The MAC transmitter is reset when RE is 0 A rising 0 to 1 transi tion on RE causes the RX current frame status register and the RX sticky frame status register to be reset EMAC_ADDRLO Register The EMAC_ADDRLO regist...

Page 451: ...w Register Figure 8 15 MAC Address High Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MAC Address Low Register EMAC_ADDRLO R W except cannot be written if RX or TX is enabled in the EMAC_OPMODE register Reset 0xFFFF FFFF MAC Address Low 31 16 0xFFC0 3004 MAC Address Low 15 0 15 14 13 12...

Page 452: ...ash table registers and extract the corresponding hash bin enable bit The most significant bit of this value determines the regis ter to be used high low while the other five bits determine the bit position within the register A CRC value of 000000 selects bit 0 of the MAC multicast hash table low register and a CRC value of 111111 selects bit 31 of the MAC multicast hash table high register If th...

Page 453: ...ee Table 8 11 The resulting six MSBs are 101001 0x29 41 decimal The hash bin enable bit for this address is then bit 41 32 9 of the EMAC_HASHHI register Table 8 11 CRC 32 Calculation Bit Number Input Bit MSB Bit Feedback Bit Next CRC Shift Register Start 1111 1111 1111 1111 1111 1111 1111 1111 0 1 1 0 1111 1111 1111 1111 1111 1111 1111 1110 1 0 1 1 1111 1011 0011 1110 1110 0010 0100 1011 2 0 1 1 1...

Page 454: ...0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC Multicast Hash Table Low Register EMAC_HASHLO Reset 0x0000 0000 0xFFC0 300C Bin 16 Bin 28 Bin 29 Bin 30 Bin 31 Bin 17 Bin 18 Bin 19 Bin 20 Bin 21 Bin 22 Bin 23 Bin 27 Bin 26 Bin 25 Bin 24 Bin 0 Bin 12 Bin 13 Bin 14 Bin 15 Bin 1 Bin 2 Bin 3 Bin 4 Bin 5 Bin 6 Bin 7 Bin 11 Bin 10 Bin 9 Bin 8 ...

Page 455: ... 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC Multicast Hash Table High Register EMAC_HASHHI Reset 0x0000 0000 0xFFC0 3010 Bin 48 Bin 60 Bin 61 Bin 62 Bin 63 Bin 49 Bin 50 Bin 51 Bin 52 Bin 53 Bin 54 Bin 55 Bin 59 Bin 58 Bin 57 Bin 56 Bin 32 Bin 44 Bin 45 Bin 46 Bin 47 Bin 33 Bin 34 Bin 35 Bin 36 Bin 37 Bin 38 Bin 39 Bin 43 Bin 42 Bin 41 Bin 40 ...

Page 456: ...STAIE 1 Enables an Ethernet event interrupt at the completion of a sta tion management register access when STABUSY changes from 1 to 0 0 Interrupt not enabled Figure 8 18 MAC Station Management Address Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC Station Management Address Register EMAC_STAADD STABUSY STA Busy Status RO Reset 0x0000 0000 STAOP Station Manage ...

Page 457: ...t operation code STAOP 1 Write 0 Read STA busy status STABUSY This bit should be set by the application software in order to ini tiate a station management register access This bit is automatically cleared when the access is complete The MAC ignores new trans fer requests made while the serial interface is busy Writes to the STA address or data registers are discarded if STABUSY is 1 1 Initiate a ...

Page 458: ...led the MAC acts upon MAC control pause frames received without errors When an error free MAC control pause frame is received with length type MacControl 88 08 and with opcode pause 00 01 the transmitter defers starting new frames for the number of slot times specified by the pause time field in the control frame The MAC can also generate and transmit a MAC control pause frame when the EMAC_FLC re...

Page 459: ...ive function is normal Pass control frames PCF When cleared the PCF bit causes the frame filter to reject all con trol frames frames with length type field equal to 88 08 When cleared error free pause control frames are still interpreted if enabled by FLCE but are not delivered via DMA Figure 8 20 MAC Flow Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30...

Page 460: ...arded if FLCBUSY is 1 1 Initiate sending flow control frame 0 No operation EMAC_VLAN1 and EMAC_VLAN2 Registers The EMAC_VLAN1 register shown in Figure 8 21 and the EMAC_VLAN2 regis ter shown in Figure 8 22 contain the tag fields used to identify VLAN frames The MAC compares the 13th and 14th bytes of the incoming frame field to the values contained in these registers so that the 13th frame byte is...

Page 461: ...d that the wakeup filters be programmed by writing all of the other registers first and writing the EMAC_WKUP_CTL register last Figure 8 21 MAC VLAN1 Tag Register Figure 8 22 MAC VLAN2 Tag Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC VLAN1 Tag Register EMAC_VLAN1 Reset 0x0000 FFFF ...

Page 462: ...l The MAC then resumes operation in the nor mal powered up mode 1 Magic packet received 0 Magic packet not received Figure 8 23 MAC Wakeup Frame Control and Status Register MAC Wakeup Frame Control and Status Register EMAC_WKUP_CTL CAPWKFRM Capture Wakeup Frames Reset 0x0000 0000 MPKE Magic Packet Wakeup Enable RWKE Remote Wakeup Frame Enable GUWKE Global Uni cast Wakeup Enable RWKS 3 0 Wakeup Fra...

Page 463: ...nabled Remote wakeup frame enable RWKE When set this bit enables the remote wakeup frame power down mode 1 Remote wakeup frame enabled 0 Remote wakeup frame not enabled Magic packet wakeup enable MPKE When set this bit enables the magic packet wakeup power down mode 1 Magic packet wakeup enabled 0 Magic packet wakeup not enabled Capture wakeup frames CAPWKFRM 1 RX frames are delivered via DMA whil...

Page 464: ...select which bytes in a received frame are used for CRC computation Each bit in these registers functions as a byte enable If a bit i is set then the byte offset i is used for CRC computa tion where offset is contained in the EMAC_WKUP_FFOFF register For example to identify a wakeup packet containing the byte sequence 0x80 0x81 0x82 in bytes 14 15 and 17 the filter offset register should be set to...

Page 465: ...KUP_FFMSK0 Reset 0x0000 0000 0xFFC0 3030 Byte Enable 16 Byte Enable 28 Byte Enable 29 Byte Enable 30 Byte Enable 31 Byte Enable 17 Byte Enable 18 Byte Enable 19 Byte Enable 20 Byte Enable 21 Byte Enable 22 Byte Enable 23 Byte Enable 27 Byte Enable 26 Byte Enable 25 Byte Enable 24 Byte Enable 0 Byte Enable 12 Byte Enable 13 Byte Enable 14 Byte Enable 15 Byte Enable 1 Byte Enable 2 Byte Enable 3 Byt...

Page 466: ...ster EMAC_WKUP_FFMSK1 Reset 0x0000 0000 0xFFC0 3034 Byte Enable 16 Byte Enable 28 Byte Enable 29 Byte Enable 30 Byte Enable 31 Byte Enable 17 Byte Enable 18 Byte Enable 19 Byte Enable 20 Byte Enable 21 Byte Enable 22 Byte Enable 23 Byte Enable 27 Byte Enable 26 Byte Enable 25 Byte Enable 24 Byte Enable 0 Byte Enable 12 Byte Enable 13 Byte Enable 14 Byte Enable 15 Byte Enable 1 Byte Enable 2 Byte E...

Page 467: ...KUP_FFMSK2 Reset 0x0000 0000 0xFFC0 3038 Byte Enable 16 Byte Enable 28 Byte Enable 29 Byte Enable 30 Byte Enable 31 Byte Enable 17 Byte Enable 18 Byte Enable 19 Byte Enable 20 Byte Enable 21 Byte Enable 22 Byte Enable 23 Byte Enable 27 Byte Enable 26 Byte Enable 25 Byte Enable 24 Byte Enable 0 Byte Enable 12 Byte Enable 13 Byte Enable 14 Byte Enable 15 Byte Enable 1 Byte Enable 2 Byte Enable 3 Byt...

Page 468: ...ster EMAC_WKUP_FFMSK3 Reset 0x0000 0000 0xFFC0 303C Byte Enable 16 Byte Enable 28 Byte Enable 29 Byte Enable 30 Byte Enable 31 Byte Enable 17 Byte Enable 18 Byte Enable 19 Byte Enable 20 Byte Enable 21 Byte Enable 22 Byte Enable 23 Byte Enable 27 Byte Enable 26 Byte Enable 25 Byte Enable 24 Byte Enable 0 Byte Enable 12 Byte Enable 13 Byte Enable 14 Byte Enable 15 Byte Enable 1 Byte Enable 2 Byte E...

Page 469: ...icast 0 Unicast Enable wakeup filter 3 1 Wakeup filter 3 enabled 0 Wakeup filter 3 not enabled Figure 8 28 MAC Wakeup Frame Filter Commands Register MAC Wakeup Frame Filter Commands Register EMAC_WKUP_FFCMD Enable Wakeup Filter 0 Reset 0x0000 0000 Wakeup Filter 0 Address Type Wakeup Filter 1 Address Type Enable Wakeup Filter 1 0xFFC0 3040 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0...

Page 470: ... Enable wakeup filter 2 1 Wakeup filter 2 enabled 0 Wakeup filter 2 not enabled Wakeup filter 1 address type 1 Multicast 0 Unicast Enable wakeup filter 1 1 Wakeup filter 1 enabled 0 Wakeup filter 1 not enabled Wakeup filter 0 address type 1 Multicast 0 Unicast Enable wakeup filter 0 1 Wakeup filter 0 enabled 0 Wakeup filter 0 not enabled ...

Page 471: ...8 29 Ethernet MAC Wakeup Frame Filter Offsets Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ethernet MAC Wakeup Frame Filter Offsets Register EMAC_WKUP_FFOFF Wakeup Filter 0 Pattern Offset 7 0 Reset 0x0000 0000 Wakeup Filter 1 Pattern Offset 7 0 0xFFC0 3044 Wakeup Filter 2 Pattern Offse...

Page 472: ...C Wakeup Frame Filter CRC2 3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC Wakeup Frame Filter CRC0 1 Register EMAC_WKUP_FFCRC0 Wakeup Filter 0 Pattern CRC 15 0 Reset 0x0000 0000 0xFFC0 3048 Wakeup Filter 1 Pattern CRC 15 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0...

Page 473: ...age 8 97 EMAC_SYSCTL Register The EMAC_SYSCTL register shown in Figure 8 32 is used to set up MAC controls Figure 8 32 MAC System Control Register MAC System Control Register EMAC_SYSCTL PHYIE PHYINT Interrupt Enable Reset 0x0000 3F00 RXDWA Receive Frame DMA Word Alignment MDCDIV 5 0 SCLK MDC Clock Divisor TXDWA Transmit Frame DMA Word Alignment 0xFFC0 3060 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 474: ...rd alignment TXDWA This bit determines whether outgoing frame data is aligned on odd or even 16 bit boundaries in memory 1 Even word alignment 0 Odd word alignment Enable receive frame TCP UDP checksum computation RXCKS 1 TCP UDP checksum computation on received frames enabled 0 Receive frame TCP UDP checksum computation not enabled Receive frame DMA word alignment RXDWA This bit determines whethe...

Page 475: ...anagement transfer on MDC MDIO has completed provided the STAIE interrupt enable control bit is set in the EMAC_STAADD register Figure 8 33 MAC System Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC System Status Register EMAC_SYSTAT PHYINT PHYINT Interrupt Status W1C Reset 0x0000 0000 MMCINT MMC Counter Interrupt Status RO STMDONE Station Management Trans...

Page 476: ...t is granted by the DMA channel with transfer in the wrong memory read direc tion This interrupt is non maskable in the Ethernet MAC Wakeup detected status WAKEDET To clear this bit write 1 to the wakeup control status register 1 Wakeup detected 0 Wakeup not detected TX frame status interrupt status TXFSINT To clear this bit write 1s to the EMAC_RX_STKY register bits 1 TX frame status interrupt ha...

Page 477: ...s the status of MMC interrupts EMAC_RX_STAT Register The EMAC_RX_STAT register shown in Figure 8 34 tells the status of the most recently completed receive frame including type of error for cases where an error occurs When the receive complete bit is set exactly one of bits 13 through 20 is 1 Bits 13 through 20 indicate the receive status as defined in IEEE 802 3 section 4 3 2 In case of multiple ...

Page 478: ...he RA Figure 8 34 Ethernet MAC RX Current Frame Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ethernet MAC RX Current Frame Status Register EMAC_RX_STAT All bits in this register are RO RX_FRLEN 10 0 Frame Length Reset 0x0000 0000 RX_COMP Receive Complete RX_ALIGN Alignment Error...

Page 479: ... frame is a valid tagged frame with a length type field matching the VLAN1 tag register and with status of receiveOK 0 The frame does not meet those conditions Frame type RX_TYPE 1 The frame is a valid typed frame with status of receiveOK and with a length type field greater than or equal to 0x600 0 The frame is not of that type Unsupported control frame RX_UCTL 1 The frame is a valid MAC control ...

Page 480: ...BROAD RX_MULTI 1 1 Illegal 1 0 Broadcast address 0 1 Group address 0 0 Unicast address Out of range length field RX_RANGE 1 The frame s length type field was consistent with the length interpretation 1536 0x600 but was greater than the maximum allowable frame size in bytes as indicated by the frame too long bit 0 The frame s length was not out of range Late collision seen RX_LATE 1 A collision was...

Page 481: ...es register 0 Address did not fail Frame fragment RX_FRAG 1 Frame length was less than the minimum frame size 64 bytes 0 Frame length was at least 64 bytes Length error RX_LEN 1 The frame s length type field does not match the length of received data and is consistent with the length interpretation 0x600 although the frame had no frame too long errors and had a valid FCS 0 No frame length error Fr...

Page 482: ...register or 1518 for all other frames The frame data delivered by DMA is truncated to 1556 0x614 bytes in all cases 0 Frame is not too long Receive OK RX_OK 1 There was no receive error 0 A receive error occurred Receive complete RX_COMP This bit is cleared on reset and when the MAC RX is enabled RE changes from 0 to 1 Frames that fail the address filter or the frame filter are not delivered by DM...

Page 483: ... Frame Status Register EMAC_RX_STKY All bits in this register are W1C Reset 0x0000 0000 RX_COMP Frames Received RX_ALIGN Alignment Errors Detected RX_LONG Frame Too Long Errors Detected RX_OK Frames Received OK 0xFFC0 306C RX_CRC Frame CRC Errors Detected RX_TYPE Typed Frames Detected RX_VLAN1 VLAN1 Frames Detected RX_VLAN2 VLAN2 Frames Detected RX_ACCEPT Receive Frames Passed Frame Filter RX_LEN ...

Page 484: ...s were detected VLAN1 frames detected RX_VLAN1 1 At least one VLAN1 frame was detected 0 No VLAN1 frames were detected Typed frames detected RX_TYPE 1 At least one typed frame was detected 0 No typed frames were detected Unsupported control frames detected RX_UCTL 1 At least one unsupported control frame was detected 0 No unsupported control frames were detected Control frames detected RX_CTL 1 At...

Page 485: ...ATE 1 At least one collision was detected after the first 64 bytes of the packet 0 No late collisions were detected PHY errors detected RX_PHY 1 At least one PHY error was detected 0 No PHY errors were detected DMA overruns detected RX_DMAO 1 At least one DMA overrun was detected 0 No DMA overruns were detected Address filter failures detected RX_ADDR 1 At least one address filter failure was dete...

Page 486: ...nment errors detected RX_ALIGN 1 At least one alignment error was detected 0 No alignment errors were detected Frame too long errors detected RX_LONG 1 At least one frame too long error was detected 0 No frame too long errors were detected Frames received OK RX_OK This bit can be used to generate an interrupt on the next RX frame 1 At least one frame has been received OK 0 No good frames have been...

Page 487: ...nt Error Interrupt Enable RX_LONG Frame Too Long Error Interrupt Enable RX_OK Good Received Frame Interrupt Enable 0xFFC0 3070 RX_CRC Frame CRC Error Interrupt Enable RX_TYPE Typed Frame Interrupt Enable RX_VLAN1 VLAN1 Frame Interrupt Enable RX_VLAN2 VLAN2 Frame Interrupt Enable RX_ACCEPT Received Filtered Frame Interrupt Enable RX_LEN Length Error Interrupt Enable RX_FRAG Frame Fragment Interrupt...

Page 488: ...s field contains the length of the transmit frame in bytes Figure 8 37 Ethernet MAC TX Current Frame Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ethernet MAC TX Current Frame Status Register EMAC_TX_STAT All bits in this register are RO Reset 0x0000 0000 TX_DEFER Deferred TX_RE...

Page 489: ... duplex only 0 CRS was asserted Deferred TX_DEFER 1 The transmission was deferred in half duplex mode because the medium was initially occupied CRS was asserted at the time the frame was ready to transmit after the initial frame data was trans ferred by DMA to the MAC Note the deferred status bit should be expected to be 1 on frames that have been retried after early col lisions since the MAC can ...

Page 490: ... transmission was deferred for more than 24 288 bit times or 6072 TX clocks MaxDeferTime 2 x MaxUntaggedFrameSize x 8 bits If the deferral check DC bit in the EMAC_OPMODE register is 1 frame transmission is aborted upon excessive deferral and both the exces sive deferral and excessive collision error status bits are set 0 Excessive deferral did not occur DMA underrun TX_DMAU 1 The frame transmissi...

Page 491: ...or because the frame was deferred for more than the maximum deferral time while the deferral check DC control bit was set 0 No excessive collision error Transmit OK TX_OK 1 There was no transmit error 0 A transmit error occurred Transmit complete TX_COMP This bit is cleared on reset and when the MAC TX is enabled TE changes from 0 to 1 In the TX DMA status buffer this bit is always set to 1 on eve...

Page 492: ...were detected Figure 8 38 Ethernet MAC TX Sticky Frame Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ethernet MAC TX Sticky Frame Status Register EMAC_TX_STKY All bits in this register are W1C Reset 0x0000 0000 TX_DEFER Frame Deferrals Detected TX_RETRY Late Collisions Detected T...

Page 493: ...dcast frames detected TX_BROAD 1 At least one broadcast frame was detected 0 No broadcast frames were detected Excessive deferrals detected TX_EDEFER 1 At least one excessive deferral was detected 0 No excessive deferrals were detected Internal MAC errors detected TX_MACE 1 At least one internal MAC error was detected 0 No internal MAC errors were detected Late collision errors detected TX_LATE 1 ...

Page 494: ... 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Ethernet MAC TX Frame Status Interrupt Enable Register EMAC_TX_IRQE For all bits 1 Interrupt enabled 0 Interrupt not enabled Reset 0x0000 0000 TX_DEFER Frame Deferral Interrupt Enable TX_RETRY Late Collision Interrupt Enable TX_LOSS Loss of Carrier Interrupt Enable TX_CRS No Car...

Page 495: ...ncremented past one half of maximum range Each bit is set from 0 to 1 when the corresponding counter increments from a value less than 0x8000 0000 to a value greater than or equal to 0x8000 0000 regardless of the state of the EMAC_MMC_RIRQE interrupt enable register Bits in this register are cleared by writing a 1 writing zero has no effect For more information see MAC Management Counters on page ...

Page 496: ...nterrupt RX_EQ64_CNT Frames Length Equal to 64 Received Counter Interrupt RX_LT128_CNT Frames Length 65 127 Received Counter Interrupt RX_OK_CNT Frames Received OK Counter Interrupt RX_FCS_CNT Frame Check Sequence Errors Counter Interrupt RX_ALIGN_CNT Align ment Errors Counter Interrupt RX_OCTET_CNT Octets Received OK Counter Interrupt RX_LOST_CNT Frames Lost Due to Int MAC Receive Error Counter I...

Page 497: ...led to signal an MMCINT interrupt when they increment past one half of maximum range If a given counter s interrupt is not enabled and that counter passes 0x8000 0000 then the counter s interrupt status bit is set to 1 but this does not cause the MMCINT interrupt to be signalled If the corresponding interrupt enable bit is later written to 1 the MMCINT Ethernet event inter rupt is signalled immedi...

Page 498: ...ed Counter Interrupt Enable RX_LT128_CNT Frames Length 65 127 Received Counter Interrupt Enable RX_OK_CNT Frames Received OK Counter Interrupt Enable RX_FCS_CNT Frame Check Sequence Errors Counter Interrupt Enable RX_ALIGN_CNT Alignment Errors Counter Interrupt Enable RX_OCTET_CNT Octets Received OK Counter Interrupt Enable RX_LOST_CNT Frames Lost Due to Int MAC Receive Error Counter Interrupt Ena...

Page 499: ...ncremented past one half of maximum range Each bit is set from 0 to 1 when the corresponding counter increments from a value less than 0x8000 0000 to a value greater than or equal to 0x8000 0000 regardless of the state of the EMAC_MMC_TIRQE interrupt enable register Bits in this register are cleared by writing a 1 writing zero has no effect For more information see MAC Management Counters on page ...

Page 500: ... Transmitted Counter Interrupt TX_OK_CNT Frames Transmitted OK Counter Interrupt TX_SCOLL_CNT Single Collision Frames Counter Interrupt TX_MCOLL_CNT Multi ple Collision Frames Counter Interrupt TX_OCTET_CNT Octets Transmitted OK Counter Interrupt TX_DEFER_CNT Frames With Deferred Transmis sion Counter Interrupt TX_LATE_CNT Late Colli sions Counter Interrupt TX_ABORTC_CNT Frames Aborted Due to Exce...

Page 501: ...bled to signal an MMCINT interrupt when they increment past one half of maximum range If a given counter s interrupt is not enabled and that counter passes 0x8000 0000 then the counter s interrupt status bit is set to 1 but this does not cause the MMCINT interrupt to be signalled If the corresponding interrupt enable bit is later written to 1 the MMCINT Ethernet event inter rupt is signalled immed...

Page 502: ...ission Aborted Frames Counter Interrupt Enable TX_OK_CNT Frames Transmitted OK Counter Interrupt Enable TX_SCOLL_CNT Single Collision Frames Counter Interrupt Enable TX_MCOLL_CNT Multi ple Collision Frames Counter Interrupt Enable TX_OCTET_CNT Octets Transmitted OK Counter Interrupt Enable TX_DEFER_CNT Frames With Deferred Transmis sion Counter Interrupt Enable TX_LATE_CNT Late Colli sions Counter...

Page 503: ...et Counters contain a 32 bit unsigned value and may be configured to satu rate at 0xFFFF FFFF CROLL 0 or to wrap around to zero CROLL 1 Counters cannot be written directly but can be collectively reset to zero by writing 1 to the RSTC bit or they can be programmed for clear on read behavior by setting CCOR to 1 The reset value for all MMC registers is 0x0000 0000 See Table 8 10 on page 8 54 for mo...

Page 504: ...ch update on every frame transmission or reception 1 MMC counters are enabled 0 MMC counters are not enabled Counters retain their values but are not updated Figure 8 44 MAC Management Counters Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 MAC Management Counters Control Registe...

Page 505: ... FFFF Reset all counters RSTC Writing a 1 to this bit at any time globally resets all MMC counters 1 Globally clear all MMC counters 0 Do not reset all counters Programming Examples This section gives a general overview of the functionality of an Ethernet MAC driver All necessary steps for reproducing and understanding this interface are explained with code listings and accompanying text These cod...

Page 506: ... many counter registers which are accessible by polling of the appropri ate register or using interrupt service routines The EMAC_SYSCTL and EMAC_SYSTAT register should be used to configure the Ethernet MAC inter rupts capabilities See Figure 8 12 on page 8 39 for a detailed description of the MAC interrupts Ethernet Structures Listing 8 1 Type Definition type definitions typedef unsigned long int...

Page 507: ... Figure 8 7 on page 8 24 the structure ADI_DMA_CONFIG_REG immediately loads to the DMA register before start ing its DMA transfer Listing 8 3 DMA Descriptor typedef struct dma_descriptor struct dma_descriptor NEXT_DESC_PTR u32 START_ADDR ADI_DMA_CONFIG_REG CONFIG DMA_DESCRIPTOR The structure shown in Listing 8 3 shows how it is possible to create a linked list of DMAs The START_ADDR points to the ...

Page 508: ... only in transmit mode in receive mode the driver will not touch this NoBytes variable To ease programming by keeping the transmit and receive structures the same the MAC can pad the first 16 bit word that is the data corresponding to the NoBytes structure member with zeros if the RXDWA bit in EMAC_SYSCTL is 1 The pNext and pPrev pointers are necessary for creating a linked list The IPHdrChksum an...

Page 509: ..._ETHER_BUFFER MAC Address Setup Write EMAC_ADDRLO and EMAC_ADDRHI in the initialization routine of the Ethernet MAC as shown in Listing 8 6 The Ethernet MAC address is a unique number and may not be used twice See the IEEE Std 802 3 2002 specification for further information Listing 8 6 MAC Address Setup MAC address u8 SrcAddr 6 0x5A 0xD4 0x9A 0x48 0xDE 0xAC function void SetupMacAddr u8 MACaddr p...

Page 510: ...IO transaction has completed void PollMdcDone void poll the STABUSY bit while pEMAC_STAADD STABUSY Shown in Listing 8 8 the SET_PHYAD and SET_REGAD macros shift the PHY Addr and RegAddr values to the appropriate field within the EMAC_STAADD register The other macros STAOP STAIE and STABUSY also set bits in the STAADD register Use of the STAOP macro controls the read and write trans fer of the MIM ...

Page 511: ...st the STABUSY bit of the EMAC_STAADD will be polled until no other function is using the MIM block The PHY address and register address is sent over the MIM block Then the STABUSY bit is polled again before the data is finally read through the EMAC_STADAT register Listing 8 9 Read Access to the PHY Read an off chip register in a PHY through the MDC MDIO port u16 RdPHYReg u16 PHYAddr u16 RegAddr u...

Page 512: ... initialization of the station management clock which is described in detail in the section MII Sta tion Management on page 8 48 The three PHY functions included in this section write read and poll and the initialization routine of the sta tion management clock are the minimum requirements for setup and control of any PHYs ...

Page 513: ...an dard is assumed Refer to Version 2 0 of CAN Specification from Robert Bosch GmbH Overview Key features of the CAN module are Conforms to the CAN 2 0B active standard Supports both standard 11 bit and extended 29 bit identifiers Supports data rates of up to 1Mbit s 32 mailboxes 8 transmit 8 receive 16 configurable Dedicated acceptance mask for each mailbox Data filtering first 2 bytes can be use...

Page 514: ...s are connected to an external CAN transceiver s TX and RX pins respectively The CANTX and CANRX pins operate with TTL levels and are appropriate for operation with CAN bus transceivers according to ISO DIS 11898 The CANRX and CANTX signals are multiplexed with the secondary data sig nals of SPORT0 To enable CAN functionality on the PJ4 and PJ5 pins the PJCE bit field in the PORT_MUX register must...

Page 515: ...AGE IDENTIFICATION DATA LENGTH MAILBOX 2 MAILBOX 1 MAILBOX CONTROL 1 TRANSMIT MAILBOX INTERRUPT TRANSMIT 1 MAILBOX INTERRUPT MASK 1 RECEIVE MESSAGE LOST 1 REMOTE FRAME HANDLING 1 OVERWRITE PROTECTION SINGLE SHOT 1 MAILBOX INTERRUPT RECEIVE 1 TRANSMIT REQUEST RESET 1 RECEIVE MESSAGE PENDING 1 MAILBOX DIRECTION 1 TRANSMIT ACKNOWLEDGE 1 ABORT ACKNOWLEDGE 1 TRANSMIT REQUEST SET 1 MAILBOX ENABLE 1 INTE...

Page 516: ...l 16 bit acceptance mask registers all of which must be configured before the mailbox itself is enabled Since the mailbox area is implemented as RAM the reset values of these registers are undefined The data is divided into fields which includes a message identifier a time stamp a byte count up to 8 bytes of data and several control bits See Figure 9 3 Figure 9 3 CAN Mailbox Area FDF EXTID_HI DFC ...

Page 517: ... should always be set to 0 If DLC is programmed to a value greater than eight the internal logic will set it to eight Up to eight bytes for the data field sent MSB first from the CAN_MBxx_DATA3 2 1 0 registers respectively based on the number of bytes defined in the DLC For example if only one byte is trans mitted or received DLC 1 then it is stored in the most significant byte of the CAN_MBxx_DAT...

Page 518: ...red monitored in registers with a suffix of 1 Similarly mailboxes 16 31 use the same named register with a suffix of 2 For exam ple the CAN mailbox direction registers CAN_MDx would control mailboxes as shown in Figure 9 4 The mailbox control register area consists of these register pairs CAN_MC1 and CAN_MC2 mailbox enable registers CAN_MD1 and CAN_MD2 mailbox direction registers CAN_TA1 and CAN_T...

Page 519: ...ilboxes the lower eight bits in the 1 registers and the upper eight bits in the 2 registers are sometimes reserved or are restricted in their usage CAN Protocol Basics Although the CANRX and CANTX pins are TTL compliant signals the CAN signals beyond the transceiver see Figure 9 1 on page 9 2 have asymmet ric drivers A low state on the CANTX pin activates strong drivers while a high state is drive...

Page 520: ... frame structure Figure 9 5 is a basic 11 bit identifier frame After the SOF and identifier is the RTR bit which indicates whether the frame contains data data frame or is a request for data associated with the message identifier in the frame being sent remote frame L Due to the inherent nature of the CAN protocol a dominant bit in the RTR field wins arbitration against a remote frame request RTR ...

Page 521: ... always sent as dominant and the checksum CRC are generated automatically by the internal logic CAN Operation The CAN controller is in configuration mode when coming out of proces sor reset or hibernate It is only when the CAN is in configuration mode that hardware behavior can be altered Before initializing the mailboxes themselves the CAN bit timing must be set up to work on the CAN bus that the...

Page 522: ...nization segment is fixed to one TQ It is required to syn chronize the nodes on the bus All signal edges are expected to occur within this segment The TSEG1 and TSEG2 fields of CAN_TIMING control how many TQs the CAN bits consist of resulting in the CAN bit rate The nominal bit time is given by the formula tBIT TQ x 1 1 TSEG1 1 TSEG2 For safe receive operation on given physical networks the sample...

Page 523: ...d by the logic to sample CANRX input On the Blackfin CAN mod ule this is 3 SCLK cycles Because of this restrictions apply to the minimal value of TSEG2 if the clock prescaler BRP is lower than 2 If BRP is set to 0 the TSEG2 field must be greater than or equal to 2 If the prescaler is set to 1 the minimum TSEG2 is 1 L All nodes on a CAN bus should use the same nominal bit rate With all the timing p...

Page 524: ...it timing parameter or initiating the software reset SRS 1 in CAN_CONTROL Transmit Operation Figure 9 8 shows the CAN transmit operation Mailboxes 24 31 are dedi cated transmitters Mailboxes 8 23 can be configured as transmitters by writing 0 to the corresponding bit in the CAN_MDx register After writing the data and the identifier into the mailbox area the message is sent after mailbox n is enabl...

Page 525: ... management when a TRSn bit is set Write access to the mailbox is permissible with TRSn set but chang ing data in such a mailbox may lead to unexpected data during transmission Enabling and disabling mailboxes has an impact on transmit requests Set ting the TRSn bit associated with a disabled mailbox may result in erroneous behavior Similarly disabling a mailbox before the associated TRSn bit is r...

Page 526: ...mit request for the CAN core module is set The message in the buffer is not replaced until it is sent successfully the arbitration on the CAN bus line is lost or there is an error frame on the CAN bus line Figure 9 8 CAN Transmit Operation Flow Chart AT LEAST 1 BIT SET IN CAN_TRSx REGISTERS STARTING WITH MAILBOX 31 FIND HIGHEST SET TRSn BIT MESSAGE ABORTED YES NO CLEAR TRSn AND REPORT ABORT ERROR ...

Page 527: ...ue is written to the CAN_UCRC register When enabled in this mode set UCCNF 3 0 0x3 in CAN_UCCNF the counter CAN_UCCNT is loaded with the value in the CAN_UCRC register The counter decrements at the CAN bit clock rate down to 0 and is then reloaded from CAN_UCRC Each time the counter reaches a value of 0 the TRS11 bit is automatically set by internal logic and the corresponding message from mailbox...

Page 528: ...etermine which of the identifier IDE and RTR bits need to match This way a mailbox can accept a group of messages If the acceptance filter finds a matching identifier the content of the received data frame is stored in that mailbox A received message is stored only once even if multiple receive mailboxes match its identifier If the current identifier does not match any mailbox the message is not s...

Page 529: ...ve message lost bit RMLn in CAN_RMLx is set and the stored message is overwritten This results in the receive message lost interrupt being raised in the global Figure 9 9 CAN Receive Operation Flow Chart MAILBOX ENABLED AME Y FROM MESSAGE RECEIVER PREVIOUS MAILBOX 0 COMPARE ALL BITS MATCH Y N EXIT NEXT MAILBOX N 1 COMPARE MASKED BITS ONLY NEXT MAILBOX MAILBOX DIRECTION RECEIVE MAILBOX READY TRANSM...

Page 530: ...or filtering on data field the filtering is done on the standard ID of the message and data fields The data field filtering can be programmed for either the first byte only or the first two bytes as shown in Table 9 2 If the FDF bit is set in the corresponding CAN_AMxxH register the CAN_AMxxL register holds the data field mask DFM 15 0 If the FDF bit is cleared in the corresponding CAN_AMxxH regis...

Page 531: ...te transmission request RTR bit Only configurable mailboxes 8 23 can process remote frames but all mes sage centers can receive and transmit remote frame requests When setup for automatic remote frame handling the CAN_OPSSx register has no effect All content of a mailbox is always overwritten by an incoming message L If a remote frame is received the DLC of the corresponding mailbox is overwritten...

Page 532: ...n the CAN_GIM register must also be set With the mask bit set when a watchdog interrupt occurs the UCEIF bit in the CAN_GIF register is also set The counter can be reloaded with the contents of CAN_UCRC or disabled by writing to the CAN_UCCNF register The time period it takes for the watchdog interrupt to occur is controlled by the value written into the CAN_UCRC register by the user Time Stamps T...

Page 533: ...s register UCEIS in the CAN_GIS register A global interrupt can optionally occur by unmasking the bit in the global interrupt mask register UCEIM in the CAN_GIM register If the interrupt source is unmasked a bit in the global interrupt flag register is also set UCEIF in the CAN_GIF register Temporarily Disabling Mailboxes If a mailbox is enabled and configured as transmit write accesses to the dat...

Page 534: ...d if the mailbox is temporarily disabled and the corresponding TRRn bit for this mailbox is set If a mailbox is configured as receive MDn 1 the temporary disable flag is set and the mailbox is not processed If there is an incoming message for the mailbox n being temporarily disabled the internal logic waits until the reception is complete or there is an error on the CAN bus to set TDA Once TDA is ...

Page 535: ...re is used the receive interrupt flag is set after the requested data frame is stored in the mailbox If any MBRIFn bits are set in CAN_MBRIFx the MBRIRQ interrupt output is raised in CAN_INTR In order to clear the MBRIRQ interrupt request all of the set MBRIFn bits must be cleared by software by writing a 1 to those set bit locations in CAN_MBRIFx If a mailbox is configured as a transmit mailbox t...

Page 536: ...status bits can be used for polling of interrupt events The global interrupt output GIRQ bit in the global interrupt status regis ter is only asserted if a bit in the CAN_GIF register is set The GIRQ bit remains set as long as at least one bit in the interrupt flag register CAN_GIF is set All bits in the interrupt status and in the interrupt flag registers remain set until cleared by software or a...

Page 537: ...N_AAx still set the bit in CAN_GIS and CAN_GIF is not set again The internal interrupt source signal is only active if a new bit in CAN_AAx is set The AAn bits maintain state even after the cor responding mailbox n is disabled MCn 0 Access to unimplemented address interrupt UIAIM UIAIS UIAIF There was a CPU access to an address which is not implemented in the controller module Wakeup interrupt WUI...

Page 538: ... mode is still active this bit is not set again If the module leaves the error warning mode the bit in CAN_GIS and CAN_GIF remains set Error warning transmit interrupt EWTIM EWTIS EWTIF The CAN transmit error counter TXECNT has reached the warning limit If the bit in CAN_GIS and CAN_GIF is reset and the error warning mode is still active this bit is not set again If the module leaves the error war...

Page 539: ...ed in a mailbox because there is no matching identifier found UCCNF 3 0 0xC Receive message lost Counter is incremented every time a message is received without detected errors but not stored in a mailbox because the mailbox contains unread data RMLn is set UCCNF 3 0 0xD Message received Counter is incremented every time a message is received without detected errors whether the received message is...

Page 540: ...his register remains unchanged CAN Error Handling Error management is an integral part of the CAN standard Five different kinds of bus errors may occur during transmissions Bit error A bit error can be detected by the transmitting node only When ever a node is transmitting it continuously monitors its receive pin CANRX and compares the received data with the transmitted data During the arbitration...

Page 541: ...er the 6th consecutive bit value is the same as the previous five bits Once the CAN module detects any of the above errors it updates the error status register CAN_ESR as well as the error counter register CAN_CEC In addition to the standard errors the CAN_ESR register features a flag that signals when the CANRX pin sticks at dominant level indicating that shorted wires are likely Error Frames It ...

Page 542: ...nt fields The first field is given by the superposition of error flags contributed from the different stations which is a sequence of 6 to 12 dominant bits The second field is the error delimiter and consists of 8 recessive bits indicating the end of frame For CRC errors the error frame is initiated at the end of the frame rather than immediately after the failing bit Figure 9 10 CAN Error Scenari...

Page 543: ...nd therefore have a limited right to signal errors These error passive nodes drive a passive error flag consisting of 6 recessive bits Thus an error passive transmitting node is still able to inform the other nodes about the abortion of a self transmitted frame but it is no longer able to destroy correctly received frames of other nodes Error Levels The CAN specification requires each node in the ...

Page 544: ... warning mechanism which is an enhancement to the CAN specification There are separate warnings for transmit and receive By default when one of the error counters exceeds 96 a warning is signaled and is represented in the CAN_STATUS register by either the CAN receive warning flag WR or CAN transmit warning flag WT bits The error warning level can be pro grammed using the error warning register CAN...

Page 545: ... L This behavior can be over ridden by setting the auto bus on ABO bit in the CAN_CONTROL register After exiting the bus off or configu ration modes the CAN error counters are reset Debug and Test Modes The CAN module contains test mode features that aid in the debugging of the CAN software and system Listing 9 1 provides an example of enabling CAN debug features L When these features are used the...

Page 546: ...ures which are not compliant with the CAN standard Bit timing registers can be changed anytime not only during con figuration mode This includes the CAN_CLOCK and CAN_TIMING registers Allows write access to the read only transmit receive error counter register CAN_CEC The mode read back bit MRB is used to enable the read back mode In this mode a message transmitted on the CAN bus or via an interna...

Page 547: ...in When this bit is set the CANTX pin continuously drives recessive bits The disable receive input bit DRI is used to disable the CANRX input When set the internal logic receives recessive bits or receives the internally generated transmit value in the case of the internal loop enabled DIL 0 In either case the value on the CANRX input pin is ignored The disable error counters bit DEC is used to di...

Page 548: ...on CAN bus line Read back No external acknowledge required Transmit message and acknowledge are transmitted on CAN bus line CANRX input is enabled 1 1 0 0 0 1 Normal transmission on CAN bus line Read back No external acknowledge required Transmit message and acknowledge are transmitted on CAN bus line CANRX input and internal loop are enabled internal OR of TX and RX 1 1 0 0 1 1 Normal transmissio...

Page 549: ...he cur rent operation of the CAN bus is finished at which point the internal logic sets the suspend mode acknowledge CSA bit in CAN_STATUS Once this mode is entered the module is no longer active on the CAN bus line slightly reducing power consumption When the CAN module is in sus pend mode the CANTX output pin remains recessive and the module does not receive transmit messages or error frames The...

Page 550: ...eads return the contents of CAN_INTR instead of the usual contents All register writes except to CAN_INTR are ignored in sleep mode A small part of the module is clocked continuously to allow for wakeup out of sleep mode A write to the CAN_INTR register ends sleep mode If the WBA bit in the CAN_CONTROL register is set before entering sleep mode a dominant bit on the CANRX pin also ends sleep mode ...

Page 551: ...t be programmed with the CAN wakeup enable bit set The typical sequence of events to use the CAN wakeup feature is 1 Use a general purpose I O pin to put the external transceiver into standby mode 2 Program VR_CTL with the CAN wakeup enable bit CANWE set and the FREQ field set to 00 Register Definitions The following sections describe the CAN register definitions Table 9 5 through Table 9 9 show t...

Page 552: ... 15 11 are reserved Table 9 6 CAN Mailbox Mask Register Mapping Register Name Function Notes CAN_AMxxH L Acceptance mask registers Change only when mailbox MBxx is disabled CAN_MBxx_ID1 0 Mailbox word 7 6 register Do not write when MBxx is enabled CAN_MBxx_ TIMESTAMP Mailbox word 5 register Holds timestamp information when timestamp mode is active CAN_MBxx_LENGTH Mailbox word 4 register Values gre...

Page 553: ...o not modify OPSSn bit if mailbox n is enabled CAN_TRSx Transmission request set registers May by set by internal logic under certain cir cumstances TRS 7 0 are read only CAN_TRRx Transmission request reset regis ters TRRn bits must not be set if mailbox n is dis abled or TRSn 0 CAN_AAx Abort acknowl edge registers AAn bit is reset if TRSn bit is set manually but not when TRSn is set by internal l...

Page 554: ...ister Mapping Register Name Function Notes CAN_UCCNF Universal counter mode register Bits 15 8 and bit 4 are reserved CAN_UCCNT Universal counter register Counts up or down based on universal counter mode CAN_UCRC Universal counter reload capture reg ister In timestamp mode holds time of last success ful transmit or receive Table 9 9 CAN Error Register Mapping Register Name Function Notes CAN_CEC ...

Page 555: ...xFFC0 2AA0 DNM DeviceNet Mode 0 Disable 1 Enable ABO Auto Bus On 0 Configuration mode 1 Enable CCR CAN Configuration Mode Request 0 Cancelled 1 Requested CSR CAN Suspend Mode Request 0 Cancelled 1 Requested SMR Sleep Mode Request 0 Not requested 1 Enters Sleep mode WBA Wake Up on CAN Bus Activity 0 Stays in Sleep mode 1 Can leave Sleep mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1...

Page 556: ...l Status Register CAN_STATUS RO WT CAN Transmit Warning Flag 0 TXECNT below limit 1 TXECNT at limit Reset 0x0000 0xFFC0 2A8C WR CAN Receive Warning Flag 0 RXECNT below limit 1 RXECNT at limit EP CAN Error Passive Mode 0 Both TXECNT and RXECNT 128 1 TXECNT or RXECNT error passive level EBO CAN Error Bus Off Mode 0 TXECNT 256 1 TXECNT bus off limit REC Receive Mode 0 Not in receive mode 1 In receive...

Page 557: ...nput Pin CANRX 0 Enable CANRX input pin 1 Disable CANRX input pin drive recessive internally DTO Disable Transmit Out put Pin CANTX 0 Enable CANTX output pin 1 Disable CANTX output pin drive recessive CDE CAN Debug Mode Enable 0 Debug mode disabled 1 Debug mode enabled MRB Mode Read Back 0 Read back mode disabled 1 Read back mode enabled MAA Mode Auto Acknowledge 0 Auto acknowledge mode disabled 1...

Page 558: ... receive flags set 1 One or more receive flags set Reset 0x00X0 X dependent on pin values 0xFFC0 2AA4 MBTIRQ Mailbox Transmit Interrupt Output 0 No transmit flags set 1 One or more transmit flags set GIRQ Global Interrupt Output 0 No global flags set 1 One or more global flags set CANRX Serial Input From Transceiver RO Serial input from CAN bus line from transceiver 0 Value is dominant 1 Value is ...

Page 559: ...Exceeded Interrupt Mask RMLIM Receive Message Lost Interrupt Mask AAIM Abort Acknowledge Interrupt Mask WUIM Wakeup Interrupt Mask UIAIM Unimplemented Address Interrupt Mask 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Global Interrupt Status Register CAN_GIS All bits are W1C EWTIS Error Warning Transmit Interrupt Status Reset 0x0000 0xFFC0 2A94 EWRIS Error Warning Receive...

Page 560: ...0 0 0 0 0 0 0 0 Global Interrupt Flag Register CAN_GIF EWTIF Error Warning Transmit Interrupt Flag Reset 0x0000 0xFFC0 2A9C EWRIF Error Warning Receive Interrupt Flag EPIF Error Passive Interrupt Flag BOIF Bus Off Interrupt Flag ADIF Access Denied Interrupt Flag EXTIF External Trigger Interrupt Flag UCEIF Universal Counter Exceeded Interrupt Flag RMLIF Receive Message Lost Interrupt Flag AAIF Abor...

Page 561: ...H 0xFFC0 2B1C CAN_AM04H 0xFFC0 2B24 CAN_AM05H 0xFFC0 2B2C CAN_AM06H 0xFFC0 2B34 CAN_AM07H 0xFFC0 2B3C CAN_AM08H 0xFFC0 2B44 CAN_AM09H 0xFFC0 2B4C CAN_AM10H 0xFFC0 2B54 CAN_AM11H 0xFFC0 2B5C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Acceptance Mask Register CAN_AMxxH EXTID 17 16 Extended Identifier Reset 0xXXXX BASEID 10 0 Base Identifier AMIDE Acceptance Mask Identifier...

Page 562: ...N_AM18H 0xFFC0 2B94 CAN_AM19H 0xFFC0 2B9C CAN_AM20H 0xFFC0 2BA4 CAN_AM21H 0xFFC0 2BAC CAN_AM22H 0xFFC0 2BB4 CAN_AM23H 0xFFC0 2BBC CAN_AM24H 0xFFC0 2BC4 CAN_AM25H 0xFFC0 2BCC CAN_AM26H 0xFFC0 2BD4 CAN_AM27H 0xFFC0 2BDC CAN_AM28H 0xFFC0 2BE4 CAN_AM29H 0xFFC0 2BEC CAN_AM30H 0xFFC0 2BF4 CAN_AM31H 0xFFC0 2BFC Table 9 10 Acceptance Mask Register H Memory mapped Addresses Cont d Register Name Memory mapp...

Page 563: ... 2B18 CAN_AM04L 0xFFC0 2B20 CAN_AM05L 0xFFC0 2B28 CAN_AM06L 0xFFC0 2B30 CAN_AM07L 0xFFC0 2B38 CAN_AM08L 0xFFC0 2B40 CAN_AM09L 0xFFC0 2B48 CAN_AM10L 0xFFC0 2B50 CAN_AM11L 0xFFC0 2B58 CAN_AM12L 0xFFC0 2B60 CAN_AM13L 0xFFC0 2B68 CAN_AM14L 0xFFC0 2B70 CAN_AM15L 0xFFC0 2B78 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Acceptance Mask Register CAN_AMxxL EXTID 15 0 DFM 15 0 Exten...

Page 564: ...N_AM20L 0xFFC0 2BA0 CAN_AM21L 0xFFC0 2BA8 CAN_AM22L 0xFFC0 2BB0 CAN_AM23L 0xFFC0 2BB8 CAN_AM24L 0xFFC0 2BC0 CAN_AM25L 0xFFC0 2BC8 CAN_AM26L 0xFFC0 2BD0 CAN_AM27L 0xFFC0 2BD8 CAN_AM28L 0xFFC0 2BE0 CAN_AM29L 0xFFC0 2BE8 CAN_AM30L 0xFFC0 2BF0 CAN_AM31L 0xFFC0 2BF8 Table 9 11 Acceptance Mask Register L Memory mapped Addresses Cont d Register Name Memory mapped Address ...

Page 565: ...B04_ID1 0xFFC0 2C9C CAN_MB05_ID1 0xFFC0 2CBC CAN_MB06_ID1 0xFFC0 2CDC CAN_MB07_ID1 0xFFC0 2CFC CAN_MB08_ID1 0xFFC0 2D1C CAN_MB09_ID1 0xFFC0 2D3C CAN_MB10_ID1 0xFFC0 2D5C CAN_MB11_ID1 0xFFC0 2D7C CAN_MB12_ID1 0xFFC0 2D9C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 7 Register CAN_MBxx_ID1 EXTID 17 16 Extended Identifier Reset 0xXXXX For Memory mapped addresses ...

Page 566: ...CAN_MB19_ID1 0xFFC0 2E7C CAN_MB20_ID1 0xFFC0 2E9C CAN_MB21_ID1 0xFFC0 2EBC CAN_MB22_ID1 0xFFC0 2EDC CAN_MB23_ID1 0xFFC0 2EFC CAN_MB24_ID1 0xFFC0 2F1C CAN_MB25_ID1 0xFFC0 2F3C CAN_MB26_ID1 0xFFC0 2F5C CAN_MB27_ID1 0xFFC0 2F7C CAN_MB28_ID1 0xFFC0 2F9C CAN_MB29_ID1 0xFFC0 2FBC CAN_MB30_ID1 0xFFC0 2FDC CAN_MB31_ID1 0xFFC0 2FFC Table 9 12 Mailbox Word 7 Register Memory mapped Addresses Cont d Register ...

Page 567: ...C0 2C78 CAN_MB04_ID0 0xFFC0 2C98 CAN_MB05_ID0 0xFFC0 2CB8 CAN_MB06_ID0 0xFFC0 2CD8 CAN_MB07_ID0 0xFFC0 2CF8 CAN_MB08_ID0 0xFFC0 2D18 CAN_MB09_ID0 0xFFC0 2D38 CAN_MB10_ID0 0xFFC0 2D58 CAN_MB11_ID0 0xFFC0 2D78 CAN_MB12_ID0 0xFFC0 2D98 CAN_MB13_ID0 0xFFC0 2DB8 CAN_MB14_ID0 0xFFC0 2DD8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 6 Register CAN_MBxx_ID0 EXTID 15 0...

Page 568: ...CAN_MB20_ID0 0xFFC0 2E98 CAN_MB21_ID0 0xFFC0 2EB8 CAN_MB22_ID0 0xFFC0 2ED8 CAN_MB23_ID0 0xFFC0 2EF8 CAN_MB24_ID0 0xFFC0 2F18 CAN_MB25_ID0 0xFFC0 2F38 CAN_MB26_ID0 0xFFC0 2F58 CAN_MB27_ID0 0xFFC0 2F78 CAN_MB28_ID0 0xFFC0 2F98 CAN_MB29_ID0 0xFFC0 2FB8 CAN_MB30_ID0 0xFFC0 2FD8 CAN_MB31_ID0 0xFFC0 2FF8 Table 9 13 Mailbox Word 6 Register Memory mapped Addresses Cont d Register Name Memory mapped Addres...

Page 569: ...C0 2C74 CAN_MB04_TIMESTAMP 0xFFC0 2C94 CAN_MB05_TIMESTAMP 0xFFC0 2CB4 CAN_MB06_TIMESTAMP 0xFFC0 2CD4 CAN_MB07_TIMESTAMP 0xFFC0 2CF4 CAN_MB08_TIMESTAMP 0xFFC0 2D14 CAN_MB09_TIMESTAMP 0xFFC0 2D34 CAN_MB10_TIMESTAMP 0xFFC0 2D54 CAN_MB11_TIMESTAMP 0xFFC0 2D74 CAN_MB12_TIMESTAMP 0xFFC0 2D94 CAN_MB13_TIMESTAMP 0xFFC0 2DB4 CAN_MB14_TIMESTAMP 0xFFC0 2DD4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X...

Page 570: ...FFC0 2E94 CAN_MB21_TIMESTAMP 0xFFC0 2EB4 CAN_MB22_TIMESTAMP 0xFFC0 2ED4 CAN_MB23_TIMESTAMP 0xFFC0 2EF4 CAN_MB24_TIMESTAMP 0xFFC0 2F14 CAN_MB25_TIMESTAMP 0xFFC0 2F34 CAN_MB26_TIMESTAMP 0xFFC0 2F54 CAN_MB27_TIMESTAMP 0xFFC0 2F74 CAN_MB28_TIMESTAMP 0xFFC0 2F94 CAN_MB29_TIMESTAMP 0xFFC0 2FB4 CAN_MB30_TIMESTAMP 0xFFC0 2FD4 CAN_MB31_TIMESTAMP 0xFFC0 2FF4 Table 9 14 Mailbox Word 5 Register Memory mapped ...

Page 571: ...LENGTH 0xFFC0 2C70 CAN_MB04_LENGTH 0xFFC0 2C90 CAN_MB05_LENGTH 0xFFC0 2CB0 CAN_MB06_LENGTH 0xFFC0 2CD0 CAN_MB07_LENGTH 0xFFC0 2CF0 CAN_MB08_LENGTH 0xFFC0 2D10 CAN_MB09_LENGTH 0xFFC0 2D30 CAN_MB10_LENGTH 0xFFC0 2D50 CAN_MB11_LENGTH 0xFFC0 2D70 CAN_MB12_LENGTH 0xFFC0 2D90 CAN_MB13_LENGTH 0xFFC0 2DB0 CAN_MB14_LENGTH 0xFFC0 2DD0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mai...

Page 572: ...ENGTH 0xFFC0 2E90 CAN_MB21_LENGTH 0xFFC0 2EB0 CAN_MB22_LENGTH 0xFFC0 2ED0 CAN_MB23_LENGTH 0xFFC0 2EF0 CAN_MB24_LENGTH 0xFFC0 2F10 CAN_MB25_LENGTH 0xFFC0 2F30 CAN_MB26_LENGTH 0xFFC0 2F50 CAN_MB27_LENGTH 0xFFC0 2F70 CAN_MB28_LENGTH 0xFFC0 2F90 CAN_MB29_LENGTH 0xFFC0 2FB0 CAN_MB30_LENGTH 0xFFC0 2FD0 CAN_MB31_LENGTH 0xFFC0 2FF0 Table 9 15 Mailbox Word 4 Register Memory mapped Addresses Cont d Register...

Page 573: ...AN_MB03_DATA3 0xFFC0 2C6C CAN_MB04_DATA3 0xFFC0 2C8C CAN_MB05_DATA3 0xFFC0 2CAC CAN_MB06_DATA3 0xFFC0 2CCC CAN_MB07_DATA3 0xFFC0 2CEC CAN_MB08_DATA3 0xFFC0 2D0C CAN_MB09_DATA3 0xFFC0 2D2C CAN_MB10_DATA3 0xFFC0 2D4C CAN_MB11_DATA3 0xFFC0 2D6C CAN_MB12_DATA3 0xFFC0 2D8C CAN_MB13_DATA3 0xFFC0 2DAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 3 Register CAN_MBxx_D...

Page 574: ...0 2E6C CAN_MB20_DATA3 0xFFC0 2E8C CAN_MB21_DATA3 0xFFC0 2EAC CAN_MB22_DATA3 0xFFC0 2ECC CAN_MB23_DATA3 0xFFC0 2EEC CAN_MB24_DATA3 0xFFC0 2F0C CAN_MB25_DATA3 0xFFC0 2F2C CAN_MB26_DATA3 0xFFC0 2F4C CAN_MB27_DATA3 0xFFC0 2F6C CAN_MB28_DATA3 0xFFC0 2F8C CAN_MB29_DATA3 0xFFC0 2FAC CAN_MB30_DATA3 0xFFC0 2FCC CAN_MB31_DATA3 0xFFC0 2FEC Table 9 16 Mailbox Word 3 Register Memory mapped Addresses Cont d Reg...

Page 575: ...2 0xFFC0 2C88 CAN_MB05_DATA2 0xFFC0 2CA8 CAN_MB06_DATA2 0xFFC0 2CC8 CAN_MB07_DATA2 0xFFC0 2CE8 CAN_MB08_DATA2 0xFFC0 2D08 CAN_MB09_DATA2 0xFFC0 2D28 CAN_MB10_DATA2 0xFFC0 2D48 CAN_MB11_DATA2 0xFFC0 2D68 CAN_MB12_DATA2 0xFFC0 2D88 CAN_MB13_DATA2 0xFFC0 2DA8 CAN_MB14_DATA2 0xFFC0 2DC8 CAN_MB15_DATA2 0xFFC0 2DE8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 2 Regi...

Page 576: ...0 2E88 CAN_MB21_DATA2 0xFFC0 2EA8 CAN_MB22_DATA2 0xFFC0 2EC8 CAN_MB23_DATA2 0xFFC0 2EE8 CAN_MB24_DATA2 0xFFC0 2F08 CAN_MB25_DATA2 0xFFC0 2F28 CAN_MB26_DATA2 0xFFC0 2F48 CAN_MB27_DATA2 0xFFC0 2F68 CAN_MB28_DATA2 0xFFC0 2F88 CAN_MB29_DATA2 0xFFC0 2FA8 CAN_MB30_DATA2 0xFFC0 2FC8 CAN_MB31_DATA2 0xFFC0 2FE8 Table 9 17 Mailbox Word 2 Register Memory mapped Addresses Cont d Register Name Memory mapped Ad...

Page 577: ...1 0xFFC0 2C84 CAN_MB05_DATA1 0xFFC0 2CA4 CAN_MB06_DATA1 0xFFC0 2CC4 CAN_MB07_DATA1 0xFFC0 2CE4 CAN_MB08_DATA1 0xFFC0 2D04 CAN_MB09_DATA1 0xFFC0 2D24 CAN_MB10_DATA1 0xFFC0 2D44 CAN_MB11_DATA1 0xFFC0 2D64 CAN_MB12_DATA1 0xFFC0 2D84 CAN_MB13_DATA1 0xFFC0 2DA4 CAN_MB14_DATA1 0xFFC0 2DC4 CAN_MB15_DATA1 0xFFC0 2DE4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 1 Regi...

Page 578: ...0 2E84 CAN_MB21_DATA1 0xFFC0 2EA4 CAN_MB22_DATA1 0xFFC0 2EC4 CAN_MB23_DATA1 0xFFC0 2EE4 CAN_MB24_DATA1 0xFFC0 2F04 CAN_MB25_DATA1 0xFFC0 2F24 CAN_MB26_DATA1 0xFFC0 2F44 CAN_MB27_DATA1 0xFFC0 2F64 CAN_MB28_DATA1 0xFFC0 2F84 CAN_MB29_DATA1 0xFFC0 2FA4 CAN_MB30_DATA1 0xFFC0 2FC4 CAN_MB31_DATA1 0xFFC0 2FE4 Table 9 18 Mailbox Word 1 Register Memory mapped Addresses Cont d Register Name Memory mapped Ad...

Page 579: ...0 0xFFC0 2C80 CAN_MB05_DATA0 0xFFC0 2CA0 CAN_MB06_DATA0 0xFFC0 2CC0 CAN_MB07_DATA0 0xFFC0 2CE0 CAN_MB08_DATA0 0xFFC0 2D00 CAN_MB09_DATA0 0xFFC0 2D20 CAN_MB10_DATA0 0xFFC0 2D40 CAN_MB11_DATA0 0xFFC0 2D60 CAN_MB12_DATA0 0xFFC0 2D80 CAN_MB13_DATA0 0xFFC0 2DA0 CAN_MB14_DATA0 0xFFC0 2DC0 CAN_MB15_DATA0 0xFFC0 2DE0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X Mailbox Word 0 Regi...

Page 580: ... 2E40 CAN_MB19_DATA0 0xFFC0 2E60 CAN_MB20_DATA0 0xFFC0 2E80 CAN_MB21_DATA0 0xFFC0 2EA0 CAN_MB22_DATA0 0xFFC0 2EC0 CAN_MB23_DATA0 0xFFC0 2EE0 CAN_MB24_DATA0 0xFFC0 2F00 CAN_MB25_DATA0 0xFFC0 2F20 CAN_MB26_DATA0 0xFFC0 2F40 CAN_MB27_DATA0 0xFFC0 2F60 CAN_MB28_DATA0 0xFFC0 2F80 CAN_MB29_DATA0 0xFFC0 2FA0 CAN_MB30_DATA0 0xFFC0 2FC0 CAN_MB31_DATA0 0xFFC0 2FE0 Table 9 19 Mailbox Word 0 Register Memory m...

Page 581: ...lbox Configuration Register 1 CAN_MC1 MC0 MC12 MC13 MC14 MC15 MC1 MC2 MC3 MC4 MC5 For all bits 0 Mailbox disabled 1 Mailbox enabled MC6 MC7 MC11 MC10 MC9 MC8 Reset 0x0000 0xFFC0 2A00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Configuration Register 2 CAN_MC2 MC16 MC28 MC29 MC30 MC31 MC17 MC18 MC19 MC20 MC21 For all bits 0 Mailbox disabled 1 Mailbox enabled MC22 M...

Page 582: ...D15 MD1 RO MD2 RO MD3 RO MD4 RO MD5 RO For all bits 0 Mailbox configured as transmit mode 1 Mailbox configured as receive mode MD6 RO MD7 RO MD11 MD10 MD9 MD8 Reset 0x00FF 0xFFC0 2A04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Direction Register 2 CAN_MD2 MD16 MD28 RO MD29 RO MD30 RO MD31 RO MD17 MD18 MD19 MD20 MD21 For all bits 0 Mailbox configured as transmit m...

Page 583: ... Receive Message Pending Register 1 CAN_RMP1 RMP0 RMP12 RMP13 RMP14 RMP15 RMP1 RMP2 RMP3 RMP4 RMP5 All bits are W1C RMP6 RMP7 RMP11 RMP10 RMP9 RMP8 Reset 0x0000 0xFFC0 2A18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Receive Message Pending Register 2 CAN_RMP2 RMP16 RMP28 RO RMP29 RO RMP30 RO RMP31 RO RMP17 RMP18 RMP19 RMP20 RMP21 All bits are W1C RMP22 RMP23 RMP27 RO RMP...

Page 584: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Receive Message Lost Register 1 CAN_RML1 RML0 RML12 RML13 RML14 RML15 RML1 RML2 RML3 RML4 RML5 RO RML6 RML7 RML11 RML10 RML9 RML8 Reset 0x0000 0xFFC0 2A1C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Receive Message Lost Register 2 CAN_RML2 RML16 RML28 RML29 RML30 RML31 RML17 RML18 RML19 RML20 RML21 RO RML22 RML23 RML27 RML26 RML25 RML24 Res...

Page 585: ... 0 0 0 0 0 0 Overwrite Protection Single Shot Transmission Register 1 CAN_OPSS1 OPSS0 OPSS12 OPSS13 OPSS14 OPSS15 OPSS1 OPSS2 OPSS3 OPSS4 OPSS5 OPSS6 OPSS7 OPSS11 OPSS10 OPSS9 OPSS8 Reset 0x0000 0xFFC0 2A30 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Overwrite Protection Single Shot Transmission Register 2 CAN_OPSS2 OPSS16 OPSS28 OPSS29 OPSS30 OPSS31 OPSS17 OPSS18 OPSS19 ...

Page 586: ... 0 0 0 0 0 0 0 0 0 0 0 Transmission Request Set Register 1 CAN_TRS1 TRS0 RO TRS12 TRS13 TRS14 TRS15 TRS1 RO TRS2 RO TRS3 RO TRS4 RO TRS5 RO TRS6 RO TRS7 RO TRS11 TRS10 TRS9 TRS8 Reset 0x0000 0xFFC0 2A08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Request Set Register 2 CAN_TRS2 TRS16 TRS28 TRS29 TRS30 TRS31 TRS17 TRS18 TRS19 TRS20 TRS21 TRS22 TRS23 TRS27 TRS2...

Page 587: ...0 0 0 0 0 0 0 0 0 Transmission Request Reset Register 1 CAN_TRR1 TRR0 RO TRR12 TRR13 TRR14 TRR15 TRR1 RO TRR2 RO TRR3 RO TRR4 RO TRR5 RO TRR6 RO TRR7 RO TRR11 TRR10 TRR9 TRR8 Reset 0x0000 0xFFC0 2A0C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Request Reset Register 2 CAN_TRR2 TRR16 TRR28 TRR29 TRR30 TRR31 TRR17 TRR18 TRR19 TRR20 TRR21 TRR22 TRR23 TRR27 TRR26...

Page 588: ...0 0 0 0 0 0 0 0 0 0 0 Abort Acknowledge Register 1 CAN_AA1 AA0 RO AA12 AA13 AA14 AA15 AA1 RO AA2 RO AA3 RO AA4 RO AA5 RO All bits are W1C AA6 RO AA7 RO AA11 AA10 AA9 AA8 Reset 0x0000 0xFFC0 2A14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Abort Acknowledge Register 2 CAN_AA2 AA16 AA28 AA29 AA30 AA31 AA17 AA18 AA19 AA20 AA21 All bits are W1C AA22 AA23 AA27 AA26 AA25 AA24 R...

Page 589: ... 0 0 0 0 0 0 0 0 Transmission Acknowledge Register 1 CAN_TA1 TA0 RO TA12 TA13 TA14 TA15 TA1 RO TA2 RO TA3 RO TA4 RO TA5 RO All bits are W1C TA6 RO TA7 RO TA11 TA10 TA9 TA8 Reset 0x0000 0xFFC0 2A10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transmission Acknowledge Register 2 CAN_TA2 TA16 TA28 TA29 TA30 TA31 TA17 TA18 TA19 TA20 TA21 All bits are W1C TA22 TA23 TA27 TA26 TA...

Page 590: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Temporary Mailbox Disable Feature Register CAN_MBTD TDPTR 4 0 Temporary Disable Pointer Reset 0x0000 0xFFC0 2AAC TDA Temporary Disable Acknowledge TDR Temporary Disable Request 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remote Frame Handling Register 1 CAN_RFH1 RFH0 RO RFH12 RFH13 RFH14 RFH15 RFH1 RO RFH2 RO RFH3 RO RFH4 RO RFH5 RO RFH6 RO RFH7 ...

Page 591: ...0 0 0 0 0 Remote Frame Handling Register 2 CAN_RFH2 RFH16 RFH28 RO RFH29 RO RFH30 RO RFH31 RO RFH17 RFH18 RFH19 RFH20 RFH21 RFH22 RFH23 RFH27 RO RFH26 RO RFH25 RO RFH24 RO Reset 0x0000 0xFFC0 2A6C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Interrupt Mask Register 1 CAN_MBIM1 MBIM0 MBIM12 MBIM13 MBIM14 MBIM15 MBIM1 MBIM2 MBIM3 MBIM4 MBIM5 MBIM6 MBIM7 MBIM11 MBIM10...

Page 592: ...terrupt Mask Register 2 CAN_MBIM2 MBIM16 MBIM28 MBIM29 MBIM30 MBIM31 MBIM17 MBIM18 MBIM19 MBIM20 MBIM21 MBIM22 MBIM23 MBIM27 MBIM26 MBIM25 MBIM24 Reset 0x0000 0xFFC0 2A68 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Transmit Interrupt Flag Register 1 CAN_MBTIF1 MBTIF0 RO MBTIF12 MBTIF13 MBTIF14 MBTIF15 MBTIF1 RO MBTIF2 RO MBTIF3 RO MBTIF4 RO MBTIF5 RO All bits are ...

Page 593: ...errupt Flag Register 2 CAN_MBTIF2 MBTIF16 MBTIF28 MBTIF29 MBTIF30 MBTIF31 MBTIF17 MBTIF18 MBTIF19 MBTIF20 MBTIF21 All bits are W1C MBTIF22 MBTIF23 MBTIF27 MBTIF26 MBTIF25 MBTIF24 Reset 0x0000 0xFFC0 2A60 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Receive Interrupt Flag Register 1 CAN_MBRIF1 MBRIF0 MBRIF12 MBRIF13 MBRIF14 MBRIF15 MBRIF1 MBRIF2 MBRIF3 MBRIF4 MBRIF5...

Page 594: ...s Figure 9 56 Mailbox Receive Interrupt Flag Register 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mailbox Receive Interrupt Flag Register 2 CAN_MBRIF2 MBRIF16 MBRIF28 RO MBRIF29 RO MBRIF30 RO MBRIF31 RO MBRIF17 MBRIF18 MBRIF19 MBRIF20 MBRIF21 All bits are W1C MBRIF22 MBRIF23 MBRIF27 RO MBRIF26 RO MBRIF25 RO MBRIF24 RO Reset 0x0000 0xFFC0 2A64 ...

Page 595: ... to reload counter in watchdog mode write 1 to clear counter in all other modes 0 No trigger 1 mailbox 4 reception reloads counter in watchdog mode mailbox 4 reception clears counter in time stamp mode no effect in other modes 0 Counter disabled 1 Counter enabled 0x0 Reserved 0x1 Time stamp mode 0x2 Watchdog mode 0x3 Auto transmit mode 0x4 Reserved 0x5 Reserved 0x6 Count error frames 0x7 Count ove...

Page 596: ...Figure 9 59 Universal Counter Reload Capture Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Universal Counter Register CAN_UCCNT UCCNT 15 0 Reset 0x0000 0xFFC0 2AC4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Universal Counter Reload Capture Register CAN_UCRC UCRC 15 0 Reset 0x0000 0xFFC0 2AC8 ...

Page 597: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN Error Counter Register CAN_CEC RXECNT 7 0 Receive Error Counter Reset 0x0000 0xFFC0 2A90 TXECNT 7 0 Transmit Error Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Error Status Register CAN_ESR All bits are W1C ACKE Acknowledge Error Reset 0x0020 0xFFC0 2AB4 SER Stuff Bit Error CRCE CRC Error FER ...

Page 598: ...Register Figure 9 62 CAN Error Counter Warning Level Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 CAN Error Counter Warning Level Register CAN_EWR EWLREC 7 0 Receive Error Warning Limit Reset 0x6060 0xFFC0 2AB0 EWLTEC 7 0 Transmit Error Warning Limit ...

Page 599: ... the appropriate header file is included in the source code that is include defBF537 h for ADSP BF537 projects CAN Setup Code The following code initializes the port pins to connect to the CAN con troller and configures the CAN timing parameters Listing 9 2 Initializing CAN Initialize_CAN P0 H HI PORT_MUX CAN pins muxed on Port J P0 L LO PORT_MUX R0 PJCE_CAN Z Enable CAN TX RX pins W P0 R0 SSYNC S...

Page 600: ...the CAN bus tBIT is 2us Using the tBIT formula from the HRM solve for TQ tBIT TQ x 1 TSEG1 1 TSEG2 1 2us TQ x 1 4 1 3 1 2e 6 TQ x 1 5 4 TQ 2e 6 10 TQ 2e 7 Once time quantum TQ is known BRP can be derived from the TQ formula in the HRM Assume the default PLL settings are used for the ADSP BF537 EZ KIT which implies that System Clock SCLK is 50MHz TQ BRP 1 SCLK 2e 7 BRP 1 50e6 BRP 1 10 BRP 9 P0 L LO...

Page 601: ...TPOS MD8 Set MB08 for Transmit BITSET R0 BITPOS MD9 Set MB09 for Receive W P0 R0 SSYNC Populate CAN Mailbox Area Mailbox 8 transmits ID 0x411 with 4 bytes of data Bytes 0 and 1 are a data pattern 0xAABB Bytes 2 and 3 will be a count value for the number of times that message is properly sent Mailbox 9 will receive message ID 0x007 Initialize Mailbox 8 For Transmit R0 0x411 2 Put Message ID in corr...

Page 602: ...B08 ID1 Register W P0 R0 Remote frame disabled 11 bit ID R0 0 P0 L LO CAN_MB_ID0 9 W P0 R0 Zero Out Lower ID Register SSYNC Enable the Configured Mailboxes P0 L LO CAN_MC1 R0 W P0 Z BITSET R0 BITPOS MC8 Enable MB08 BITSET R0 BITPOS MC9 Enable MB09 W P0 R0 SSYNC RTS Initiating CAN Transfers and Processing Interrupts After the mailboxes are properly set up transfers can be requested in the CAN contr...

Page 603: ...nd Interrupts CAN_SetupIRQs_and_Transfer P0 H HI CAN_MBIM1 P0 L LO CAN_MBIM1 R0 0 BITSET R0 BITPOS MBIM8 Enable Mailbox Interrupts BITSET R0 BITPOS MBIM9 for Mailboxes 8 and 9 W P0 R0 SSYNC Leave CAN Configuration Mode Clear CCR P0 L LO CAN_CONTROL R0 W P0 Z BITCLR R0 BITPOS CCR W P0 R0 P0 L LO CAN_STATUS Wait for CAN Configuration Acknowledge CCA WAIT_FOR_CCA_TO_CLEAR R1 W P0 Z CC BITTST R1 BITPO...

Page 604: ...7 Clear Interrupt Request Bit for MB08 P5 L LO CAN_MB_DATA2 8 R7 W P5 Z Retrieve Previously Sent Data R6 0xFF Mask Upper Byte to Check Lower R6 R6 R7 Byte for Wrap R5 0xFF Check Wrap Condition CC R6 R5 Check if Lower Byte Wraps IF CC JUMP HANDLE_COUNT_WRAP R7 1 If no wrap Increment Count JUMP PREPARE_TO_SEND HANDLE_COUNT_WRAP R6 0xFF00 Z Mask Off Lower Byte R7 R7 R6 Sets Lower Byte to 0 R6 0x0100 ...

Page 605: ... writes new data to be sent and requests to send again CAN_RX_HANDLER SP R7 7 P5 4 Save Clobbered Registers SP ASTAT P4 H CAN_RX_WORD Set Pointer to Storage Element P4 L CAN_RX_WORD P5 H HI CAN_MBRIF1 P5 L LO CAN_MBRIF1 R7 MBRIF9 W P5 R7 Clear Interrupt Request Bit for MB09 P5 L LO CAN_MB_DATA3 9 R7 W P5 Z Read data from mailbox W P4 R7 Store data to SDRAM ASTAT SP Restore Clobbered Registers R7 7...

Page 606: ...Programming Examples 9 94 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 607: ...heral devices With a range of configurable options the SPI port provides a glueless hardware interface with other SPI compatible devices SPI is a four wire interface consisting of two data signals a device select signal and a clock signal SPI is a full duplex synchronous serial interface supporting master modes slave modes and multimaster environments The SPI compatible peripheral implementation a...

Page 608: ...nput Programmable shift direction of MSB or LSB first Interrupt generation on mode fault overflow and underflow Shadow register to aid debugging Typical SPI compatible peripheral devices that can be used to interface to the SPI compatible interface include Other CPUs or microcontrollers Codecs A D converters D A converters Sample rate converters SP DIF or AES EBU digital audio transmitters and rec...

Page 609: ...time through the use of a shift register When an SPI transfer occurs data is simultaneously transmitted shifted serially out of the shift register as new data is received shifted serially into the other end of the same shift register The SCK synchronizes the shifting and sampling of the data on the two serial data pins Figure 10 1 SPI Block Diagram MOSI MISO SCK SPI INTERFACE LOGIC SHIFT REGISTER ...

Page 610: ...RT0 signals and require PJSE 1 or PJCE 10 Serial Peripheral Interface Clock Signal SCK The SCK signal is the serial clock signal This control signal is driven by the master and controls the rate at which data is transferred The master may transmit data at a variety of bit rates The SCK signal cycles once for each bit transmitted It is an output signal if the device is configured as a mas ter and a...

Page 611: ...n SPI interconnection the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input s of the slave s The SPI MOSI signal can connect to the PF11 pin which functions as a GPIO by default To enable this pin for use as the SPI MOSI signal be sure to first configure the PORTF_FER register to enable the PF11 pin for periph eral use see Function Enable Registers on page ...

Page 612: ...r L The processor can be booted via its SPI interface to allow user application code and data to be downloaded before runtime Serial Peripheral Interface Slave Select Input Signal The SPISS signal is the SPI serial peripheral slave select input signal This is an active low signal used to enable a processor when it is configured as a slave device This input only pin behaves like a chip select and i...

Page 613: ...iod See Figure 10 3 The minimum time between successive word transfers T4 is two SCK periods This is measured from the last active edge of SCK of one word to the first active edge of SCK of the next word This is independent of the configuration of the SPI CPHA MSTR and so on For a master device with CPHA 0 the slave select output is inactive high for at least one half the SCK period In this case T...

Page 614: ...tput pins the PFx and PJx pins must be enabled for use by SPI in the PORT_MUX register see Port Multiplexer Control Register on page 14 22 For PFx pins only the PORTF_FER register see Function Enable Registers on page 14 23 must also be modified to enable those PFx pins for peripheral use Refer to Table 10 2 for more details regarding which port pins must be configured prior to being modified via ...

Page 615: ...n page 10 42 shows the SPI_FLG register diagram Table 10 2 SPI_FLG Bit Mapping to Port Pins Bit Name Function Port Pin Default 0 Reserved 0 1 FLS1 SPISSEL1 Enable PF10 0 2 FLS2 SPISSEL2 Enable PJ11 0 3 FLS3 SPISSEL3 Enable PJ10 0 4 FLS4 SPISSEL4 Enable PF6 0 5 FLS5 SPISSEL5 Enable PF5 0 6 FLS6 SPISSEL6 Enable PF4 0 7 FLS7 SPISSEL7 Enable PJ5 0 8 Reserved 1 9 FLG1 SPISSEL1 Value PF10 1 10 FLG2 SPIS...

Page 616: ...this multislave environment For example assume that the SPI is the master The seven port pins that can be configured as SPI master mode slave select output pins can be con nected to each of the slave SPI device s SPISS pins In this configuration the FLSx bits in SPI_FLG can be used in three cases In cases 1 and 2 the processor is the master and the seven microcontrol lers peripherals with SPI inte...

Page 617: ...ansmit value is loaded into the shift regis ter The receive buffer becomes full at the end of a transfer when the shift register value is loaded into the receive buffer It becomes empty when the receive buffer is read L The SPIF bit is set when the SPI port is disabled Upon entering DMA mode the transmit buffer and the receive buffer become empty That is the TXS bit and the RXS bit are ini tially ...

Page 618: ...I resources into the system MMR space through the PAB bus For the PAB accesses to SPI MMRs the primary performance criteria is latency not throughput Transfer latencies for both read and write transfers on the PAB are 2 SCLK cycles The DAB bus provides a means for DMA SPI transfers to gain access to on chip and off chip memory with little or no degradation in core band width to memory The SPI peri...

Page 619: ...word FIFO is cleared when the SPI port is disabled SPI Transmit Data Buffer The SPI_TDBR register is a 16 bit read write register Data is loaded into this register before being transmitted Just prior to the beginning of a data transfer the data in SPI_TDBR is loaded into the SFDR register A read of SPI_TDBR can occur at any time and does not interfere with or initiate SPI transfers When the DMA is...

Page 620: ...DOW register has been provided for use in debugging software This register is at a different address than the receive data buffer SPI_RDBR but its contents are identical to that of SPI_RDBR When a soft ware read of SPI_RDBR occurs the RXS bit in SPI_STAT is cleared and an SPI transfer may be initiated if TIMOD 00 in SPI_CTL No such hard ware action occurs when the SPI_SHADOW register is read The S...

Page 621: ...16 bit transfer with the Least Significant Bit LSB first is another possible configuration The clock polarity and the clock phase should be identical for the master device and the slave device involved in the communication link The transfer format from the master may be changed between transfers to adjust to various requirements of a slave device When CPHA 0 the slave select line SPISS must be ina...

Page 622: ...I Transfer Protocol for CPHA 1 6 MSB SPISS TO SLAVE SCK CPOL 0 SCK CPOL 1 MOSI FROM MASTER MISO FROM SLAVE 1 2 3 4 8 5 6 7 5 4 3 2 1 LSB 6 MSB 5 4 3 2 1 LSB CLOCK CYCLE NUMBER UNDEFINED 6 MSB 1 2 3 4 8 5 6 7 5 4 3 2 1 LSB 6 MSB 5 4 3 2 1 LSB UNDEFINED SCK CPOL 0 SCK CPOL 1 MOSI FROM MASTER MISO FROM SLAVE CLOCK CYCLE NUMBER SPISS TO SLAVE ...

Page 623: ...nk con sists of a single master and a single slave CPHA 1 and the slave select input of the slave is always tied low In this case the slave is always selected and data corruption can be avoided by enabling the slave only after both the master and slave devices are configured In a multimaster or multislave SPI system the data output pins MOSI and MISO can be configured to behave as open drain outpu...

Page 624: ...re connected together For a multislave environment the processor can make use of seven pro grammable flags that are dedicated SPI slave select signals for the SPI slave devices See Table 10 2 on page 10 9 L At reset the SPI is disabled and configured as a slave SPI Control The SPI_CTL register is used to configure and enable the SPI system This register is used to enable the SPI interface select t...

Page 625: ...the SPI_STAT register is set See Mode Fault Error MODF on page 10 21 Figure 10 12 on page 10 41 provides the bit descriptions for SPI_CTL Clock Signals The SCK signal is a gated clock that is only active during data transfers for the duration of the transferred word The number of active edges is equal to the number of bits driven on the data lines The clock rate can be as high as one fourth of the...

Page 626: ... several possible baud rate values for SPI_BAUD Error Signals and Flags The SPI_STAT register is used to detect when an SPI transfer is complete or if transmission reception errors occur The SPI_STAT register can be read at any time Some of the bits in SPI_STAT are read only and other bits are sticky Bits that provide information only about the SPI are read only These bits are set and cleared by t...

Page 627: ...e the master To enable this feature the PSSE bit in SPI_CTL must be set This contention between two drivers can potentially damage the driving pins As soon as this error is detected these actions occur The MSTR control bit in SPI_CTL is cleared configuring the SPI interface as a slave The SPE control bit in SPI_CTL is cleared disabling the SPI system The MODF status bit in SPI_STAT is set An SPI e...

Page 628: ...s ensures that once the MODF error occurs and the slave selects are auto matically reconfigured as port pins the slave select output drivers are disabled Transmission Error TXE The TXE bit is set in SPI_STAT when all the conditions of transmission are met and there is no new data in SPI_TDBR SPI_TDBR is empty In this case the contents of the transmission depend on the state of the SZ bit in SPI_CT...

Page 629: ... 11 or read from TIMOD 10 In non DMA mode TIMOD 0X a data interrupt is generated when the SPI_TDBR is ready to be written to TIMOD 01 or when the SPI_RDBR is ready to be read from TIMOD 00 An SPI error interrupt is generated in a master when a mode fault error occurs in both DMA and non DMA modes An error interrupt can also be generated in DMA mode when there is an underflow TXE when TIMOD 11 or a...

Page 630: ...ng the appropriate word length transfer format baud rate and other nec essary information 4 If CPHA 1 the core activates the desired slaves by clearing one or more of the SPI flag bits FLGx of SPI_FLG 5 The TIMOD bits in SPI_CTL determine the SPI transfer initiate mode The transfer on the SPI link begins upon either a data write by the core to the transmit data buffer SPI_TDBR or a data read of th...

Page 631: ... and SPI_RDBR is not updated Transfer Initiation From Master Transfer Modes When a device is enabled as a master the initiation of a transfer is defined by the two TIMOD bits of SPI_CTL Based on those two bits and the status of the interface a new transfer is started upon either a read of SPI_RDBR or a write to SPI_TDBR This is summarized in Table 10 4 L If the SPI port is enabled with TIMOD 01 or...

Page 632: ...s the mode setup in the SPI master 3 To prepare for the data transfer the core writes data to be trans mitted into SPI_TDBR 4 Once the SPISS falling edge is detected the slave starts sending data on active SCK edges and sampling data on inactive SCK edges 10 Receive with DMA Initiate new multiword trans fer upon enabling SPI for DMA mode Individual word transfers begin with a DMA read of SPI_RDBR ...

Page 633: ... transmits the last word it transmitted before the transmit buffer became empty If GM 1 and the receive buffer is full the device continues to receive new data from the MOSI pin overwriting the older data in SPI_RDBR If GM 0 and the receive buffer is full the incoming data is dis carded and SPI_RDBR is not updated Slave Ready for a Transfer When a device is enabled as a slave the actions shown in ...

Page 634: ...ter it sends the last data and simultaneously receives the last data bit A transfer for a slave device ends after the last sampling edge of SCK The RXS bit defines when the receive buffer can be read The TXS bit defines when the transmit buffer can be filled The end of a single word transfer occurs when the RXS bit is set indicating that a new word has just been received and latched into the recei...

Page 635: ...transmit operation frequently then the TIMOD 00 mode may be the best operation option In this mode software performs a dummy read from the SPI_RDBR register to initiate the first transfer If the first transfer is used for data transmission software should write the value to be transmitted into the SPI_TDBR register before per forming the dummy read If the transmitted value is arbitrary it is good ...

Page 636: ...he necessary work units access direction word count and so on For more informa tion see Chapter 5 Direct Memory Access 3 The processor core writes to the SPI_FLG register setting one or more of the SPI flag select bits FLSx 4 The processor core writes to the SPI_BAUD and SPI_CTL registers enabling the device as a master and configuring the SPI system by specifying the appropriate word length trans...

Page 637: ...tinues to read a word from the SPI DMA FIFO and writes to memory until the SPI DMA word count register transitions from 1 to 0 The SPI continues receiving words until SPI DMA mode is disabled In transmit mode as long as there is room in the SPI DMA FIFO the FIFO is not full the SPI continues to request a DMA read from memory The DMA engine continues to read a word from memory and write to the SPI ...

Page 638: ...de because the master SPI will not initiate a transfer if there is no data in the DMA FIFO Writes to the SPI_TDBR register during an active SPI transmit DMA opera tion should not occur because the DMA data will be overwritten Writes to the SPI_TDBR register during an active SPI receive DMA operation are allowed Reads from the SPI_RDBR register are allowed at any time DMA requests are generated whe...

Page 639: ... 10 or transmit with DMA TIMOD 11 mode 4 If configured for receive once the slave select input is active the slave starts receiving and transmitting data on active SCK edges The value in the shift register is loaded into the SPI_RDBR register at the end of the transfer As the SPI reads data from the SPI_RDBR regis ter and writes to the SPI DMA FIFO it requests a DMA write to memory Upon a DMA gran...

Page 640: ...ve DMA operations if the DMA engine is unable to keep up with the receive datastream the receive buffer operates according to the state of the GM bit If GM 1 and the DMA FIFO is full the device continues to receive new data from the MOSI pin overwriting the older data in the SPI_RDBR register If GM 0 and the DMA FIFO is full the incoming data is discarded and the SPI_RDBR register is not updated W...

Page 641: ...uring an active SPI transmit DMA opera tion should not occur because the DMA data will be overwritten Writes to the SPI_TDBR register during an active SPI receive DMA operation are allowed Reads from the SPI_RDBR register are allowed at any time DMA requests are generated when the DMA FIFO is not empty when TIMOD 10 or when the DMA FIFO is not full when TIMOD 11 Error interrupts are generated when...

Page 642: ...SLAVE SUPPORT Y WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR 1 WRITE SPI_CTL TO CONFIGURE SPI HARDWARE AND ENABLE SPI PORT Y N WRITE SPI_FLG TO SELECT SLAVE S VIA FLGx BITS WRITE SPI_TBDR WITH DATA TO SEND OVER SPI Y N READ SPI_RDBR TO START TRANSFER WAIT FOR TRANSFER COMPLETE LAST TRANSFER Y N TIMOD 01 Y N READ NEW DATA FROM SPI_RDBR CPHA 1 AND MSTR 1...

Page 643: ...DMA7 REGISTER NAMES IN THIS FLOW CHART WITH CHOSEN DMAx PREFIX WRITE DMA7_CONFIG TO CONFIGURE DMA ENGINE 0x4 ARRAY 0x6 SMALL LIST 0x7 LARGE LIST 0x0 STOP 0x1 AUTOBUFFER POPULATE DESCRIPTORS IN MEMORY WRITE DMA REGISTERS DMA7_START_ADDR DMA7_X_COUNT DMA7_X_MODIFY DMA7_CONFIG S NDSIZE FIELD DETERMINES WHICH DMA REGISTERS TO INITIALIZE STATICALLY DMA7_CONFIG FLOW 0x6 SMALL LIST 0x7 LARGE LIST 0x4 ARR...

Page 644: ... DMA7_Y_MODIFY MASTER MULTI SLAVE SUPPORT N A SLAVE MSTR 0 Y WRITE PORT_MUX TO ENABLE PORT J SLAVES AND OR MORE PORT F SLAVES WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR 1 WRITE SPI_CTL TO CONFIGURE SPI PORT CPHA 1 AND MSTR 1 Y N WRITE SPI_FLG TO SELECT SLAVE S VIA FLGx BITS WRITE DMA7_CONFIG TO ENABLE DMA WRITE SPI_CTL TO ENABLE SPI B ...

Page 645: ...RRUPT BY WRITING THE DMA_DONE BIT IN DMA7_IRQ_STATUS N TX OR RX DMA TX B Y N WRITE DMA7_CONFIG TO ENABLE DMA AGAIN WAIT FOR DMA_RUN 0 IN DMA7_IRQ_STATUS WAIT FOR TWO STRAIGHT READS OF TXS 0 IN SPI_STAT WAIT FOR SPIF 1 IN SPI_STAT CPHA 1 AND MSTR 1 Y N WRITE SPI_FLG TO DESELECT SLAVE S VIA FLGx BITS WRITE SPI_CTL TO DISABLE SPI PORT WRITE DMA7_CONFIG TO DISABLE DMA FLOW STOP Y RX ...

Page 646: ... registers are used to signal errors and other conditions Table 10 6 shows the functions of the SPI registers Figure 10 11 through Figure 10 17 on page 10 44 provide details Table 10 6 SPI Register Mapping Register Name Function Notes SPI_BAUD SPI port baud control Value of 0 or 1 disables the serial clock SPI_CTL SPI port control SPE and MSTR bits can also be modified by hardware when MODF is set...

Page 647: ...g as SPI DMA FIFO is not full SZ Send Zero Send zero or last word when SPI_TDBR is empty 0 Send last word 1 Send zeros GM Get More Data When SPI_RDBR is full get data or discard incoming data 0 Discard incoming data 1 Get more data overwrite previous data PSSE Slave Select Enable 0 Disable 1 Enable EMISO Enable MISO 0 MISO disabled 1 MISO enabled Reset 0x0400 SPE SPI Enable 0 Disabled 1 Enabled WO...

Page 648: ...t 0xFF00 FLS1 Slave Select Enable 1 0 SPISSEL1 disabled 1 SPISSEL1 enabled FLS2 Slave Select Enable 2 0 SPISSEL2 disabled 1 SPISSEL2 enabled FLS3 Slave Select Enable 3 0 SPISSEL3 disabled 1 SPISSEL3 enabled FLS4 Slave Select Enable 4 0 SPISSEL4 disabled 1 SPISSEL4 enabled FLS5 Slave Select Enable 5 0 SPISSEL5 disabled 1 SPISSEL5 enabled FLS6 Slave Select Enable 6 0 SPISSEL6 disabled 1 SPISSEL6 ena...

Page 649: ...e and the FLGx bits are ignored The SPI protocol requires that the slave select be deasserted between transferred words In this case the SPI hard ware controls the pins For example to use PJ10 as a slave select pin it is only necessary to set the FLS3 bit in SPI_FLG It is not nec essary to write to the FLG3 bit because the SPI hardware automatically drives the PJ10 pin Figure 10 14 SPI Status Regi...

Page 650: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 Transmit Data Buffer 15 0 SPI Transmit Data Buffer Register SPI_TDBR 0xFFC0 050C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 Receive Data Buffer 15 0 SPI Receive Data Buffer Register SPI_RDBR RO 0xFFC0 0510 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 SPI_RDBR Shadow 15 0 SPI RDBR...

Page 651: ...PI example shows how to initial ize the hardware signal the start of a transfer handle the interrupt and issue the next transfer and generate a stop condition Initialization Sequence Before the SPI can transfer data the registers must be configured as follows Listing 10 1 SPI Register Initialization SPI_Register_Initialization P0 H hi SPI_FLG P0 L lo SPI_FLG R0 W P0 Z BITSET R0 0x7 FLS7 W P0 R0 En...

Page 652: ...vice Is Master WOM 13 0 Normal MOSI MISO Data Output No Open Drain SPE 14 1 SPI Module Is Enabled 15 0 RESERVED P0 H hi SPI_CTL P0 L lo SPI_CTL R0 0x5908 W P0 R0 L ssync Enable SPI as MASTER Starting a Transfer After the initialization procedure in the given master mode a transfer begins following a dummy read of SPI_RDBR Typically known data which is desired to be transmitted to the slave is prel...

Page 653: ...te to SPI_TDBR P0 H hi SPI_RDBR P0 L lo SPI_RDBR R0 W P0 z Dummy read of SPI_RDBR kicks off transfer Post Transfer and Next Transfer Following the transfer of data the SPI generates an interrupt which is ser viced if the interrupt is enabled during initialization In the interrupt routine software must write the next value to be transmitted prior to reading the byte received This is because a read ...

Page 654: ...pping In order for a data transfer to end after the user has transferred all data the following code can be used to stop the SPI Note that this is typically done in the interrupt handler to ensure the final data has been sent in its entirety Listing 10 4 Stopping SPI Stopping_SPI P0 H hi SPI_CTL P0 L lo SPI_CTL R0 W P0 BITCLR R0 14 Clear SPI enable bit W P0 R0 L ssync Disable SPI DMA Transfer The ...

Page 655: ...ed macro indicating the number of elements being sent Listing 10 5 DMA Initialization Initialize_DMA DMA7 default channel for SPI DMA P0 H hi DMA7_CONFIG P0 L lo DMA7_CONFIG R0 0x1084 z Autobuffer mode IRQ on complete linear 16 bit mem read w P0 R0 P0 H hi DMA7_START_ADDR P0 L lo DMA7_START_ADDR p0 p1 Start address of TX buffer P0 H hi DMA7_X_COUNT P0 L lo DMA7_X_COUNT R0 NUM_SAMPLES w p0 R0 Numbe...

Page 656: ...0x208E Write to SPI baud rate register W P0 R0 L ssync If SCLK 133MHz SPI clock 8kHz Setup SPI Control Register TIMOD 1 0 11 Transfer on DMA TDBR write SZ 2 0 Send last word when TDBR0 is empty GM 3 1 Discard incoming data if RDBR0 is full PSSE 4 0 Disables slave select as input master EMISO 5 0 MISO disabled for output master 7 and 6 0 RESERVED SIZE 8 1 16 Bit word length select LSBF 9 0 Transmit...

Page 657: ... must be enabled before enabling the SPI Listing 10 7 Starting a Transfer Initiate_Transfer P0 H hi DMA7_CONFIG P0 L lo DMA7_CONFIG R2 w P0 z BITSET R2 0 Set DMA enable bit w p0 R2 L Enable TX DMA P4 H hi SPI_CTL P4 L lo SPI_CTL R2 w p4 z BITSET R2 14 Set SPI enable bit w p4 R2 Enable SPI Stopping a Transfer In order for a data transfer to end after the DMA has transferred all required data the fo...

Page 658: ...SPIF bit determines when the last bit of the last word has been shifted out At that point it is safe to shut down the SPI port and the DMA engine Listing 10 8 Stopping a Transfer SPI_DMA_INTERRUPT_HANDLER P0 L lo DMA7_IRQ_STATUS P0 H hi DMA7_IRQ_STATUS R0 1 W P0 R0 Clear DMA interrupt Wait for DMA to complete P0 L lo DMA7_IRQ_STATUS P0 H hi DMA7_IRQ_STATUS R0 DMA_RUN 0x08 CHECK_DMA_COMPLETE Poll f...

Page 659: ...C R0 0 IF CC JUMP Check_TXS Wait for final word to transmit from SPI Final_Word R0 W P0 Z R2 SPIF 0x01 R0 R0 R2 CC R0 0 IF CC JUMP Final_Word Disable_SPI P0 L lo SPI_CTL P0 H hi SPI_CTL R0 W P0 Z BITCLR R0 0xe Clear SPI enable bit W P0 R0 Disable SPI Disable_DMA P0 L lo DMA7_CONFIG P0 H hi DMA7_CONFIG R0 W P0 Z BITCLR R0 0x0 Clear DMA enable bit W P0 R0 Disable DMA RTI Exit Handler ...

Page 660: ...Programming Examples 10 54 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 661: ...2000 This feature applies to the ADSP BF534 ADSP BF536 and ADSP BF537 processors The TWI is fully compatible with the widely used I2 C bus standard It was designed with a high level of functionality and is compatible with multi master multi slave bus configurations To preserve processor band width the TWI controller can be set up with transfer initiated interrupts only to service FIFO buffer data ...

Page 662: ... clock lines in the event of bus lock up Input filter for spike suppression Serial camera control bus support as specified in the OmniVision Serial Camera Control Bus SCCB Functional Specification version 2 1 Interface Overview Figure 11 1 provides a block diagram of the TWI controller The interface is essentially a shift register that serially transmits and receives data bits one bit at a time at...

Page 663: ...hese signals SDA serial data and SCL serial clock are open drain and as such require pull up resistors Serial Clock signal SCL In slave mode this signal is an input and an external master is responsible for providing the clock Figure 11 1 TWI Block Diagram PAB 16 TWI INTERFACE LOGIC CLOCK GENERATION Tx REG 2 DEEP FIFO 2 DEEP FIFO Rx REG Tx SHIFT REG Rx SHIFT REG ARBITRATION PRESCALER ADDRESS COMPA...

Page 664: ...LE value is the number of system clock SCLK periods used in the generation of one internal time reference The value of PRESCALE must be set to create an internal time reference with a period of 10 MHz It is represented as a 7 bit binary value Serial data signal SDA This is a bidirectional signal on which serial data is transmitted or received depending on the direction of the transfer TWI Pins Tab...

Page 665: ... generation of acknowledgements or it can be manually overwritten The receive shift register receives its data serially from off chip The receive shift register is 1 byte wide and data received can either be trans ferred to the FIFO buffer or used in an address comparison The address compare block supports address comparison in the event the TWI controller module is accessed as a slave The prescal...

Page 666: ...same transfer as above noting the corresponding TWI controller bit names In this illustration the TWI controller successfully transmits one byte of data The slave has acknowl edged both address and data Clock Generation and Synchronization The TWI controller implementation only issues a clock during master mode operation and only at the time a transfer has been initiated If arbi tration for the bu...

Page 667: ...he clock low CLKLOW count begins Once the clock low count is complete the serial clock line is three stated and the clock synchronization logic enters into a delay mode shaded area until the SCL line is detected at a logic 1 level At this time the clock high count begins Bus Arbitration The TWI controller initiates a master mode transmission MEN only when the bus is idle If the bus is idle and two...

Page 668: ...dges but also during the entire time SCL is high Start and Stop Conditions Start and stop conditions involve serial data transitions while the serial clock is a logic 1 level The TWI controller generates and recognizes these transitions Typically start and stop conditions occur at the beginning and at the conclusion of a transmission with the exception repeated start combined transfers as shown in...

Page 669: ...mitter or master receiver If the stop bit is set during an active master transfer the TWI con troller issues a stop condition as soon as possible avoiding any error conditions as if data transfer count had been reached General Call Support The TWI controller always decodes and acknowledges a general call address if it is enabled as a slave SEN and if general call is enabled GEN general call addres...

Page 670: ...n of the TWI TWI Control The TWI control register TWI_CONTROL is used to enable the TWI mod ule as well as to establish a relationship between the system clock SCLK and the TWI controller s internally timed events The internal time refer ence is derived from SCLK using a prescaled value PRESCALE fSCLK 10MHz SCCB compatibility is an optional feature and should not be used in an I2 C bus system This...

Page 671: ...al The clock signal SCL is an output in master mode and an input in slave mode During master mode operation the SCL clock divider register TWI_CLKDIV values are used to create the high and low durations of the serial clock SCL Serial clock frequencies can vary from 400 KHz to less than 20 KHz The resolution of the clock generated is 1 10 MHz or 100 ns CLKDIV TWI SCL period 10 MHz time reference Fo...

Page 672: ...rent transfer Slave mode oper ation does not affect master mode status bits Bus busy BUSBUSY Indicates whether the bus is currently busy or free This indication is not limited to only this device but is for all devices Upon a start condition the setting of the register value is delayed due to the input filtering Upon a stop condition the clearing of the register value occurs after tBUF 1 The bus i...

Page 673: ...ive zero is currently being sensed on the serial data line The source of the active driver is not known and can be internal or external 0 An inactive one is currently being sensed on the serial data line Buffer write error BUFWRERR 1 The current master transfer was aborted due to a receive buffer write error The receive buffer and receive shift register were both full at the same time This bit is ...

Page 674: ...orted due to the detection of a NAK during the address phase of the transfer This bit is W1C 0 The current master transmit has not detected NAK during addressing Lost arbitration LOSTARB 1 The current transfer was aborted due to the loss of arbitration with another master This bit is W1C 0 The current transfer has not lost arbitration with another master Master transfer in progress MPROG 1 A maste...

Page 675: ...er mode operation does not affect slave mode status bits General call GCALL This bit self clears if slave mode is disabled SEN 0 1 At the time of addressing the address was determined to be a general call 0 At the time of addressing the address was not determined to be a general call Slave transfer direction SDIR This bit self clears if slave mode is disabled SEN 0 1 At the time of addressing the ...

Page 676: ...ultaneous master and slave operation Receive FIFO status RCVSTAT 1 0 The RCVSTAT field is read only It indicates the number of valid data bytes in the receive FIFO buffer The status is updated with each FIFO buffer read using the peripheral data bus or write access by the receive shift register Simultaneous accesses are allowed 11 The FIFO is full and contains two bytes of data Either a sin gle or...

Page 677: ...peripheral write of the FIFO is allowed TWI Interrupt Status The TWI interrupt status register TWI_INT_STAT contains information about functional areas requiring servicing Many of the bits serve as an indicator to further read and service various status registers After servicing the interrupt source associated with a bit the user must clear that inter rupt source bit by writing a 1 to it Receive F...

Page 678: ...ed since this bit was last cleared Master transfer error MERR 1 A master error has occurred The conditions surrounding the error are indicated by the master status register TWI_MASTER_STAT 0 No errors have been detected Master transfer complete MCOMP 1 The initiated master transfer has completed In the absence of a repeat start the bus has been released 0 The completion of a transfer has not been ...

Page 679: ...of a transfer 0 No errors have been detected Slave transfer complete SCOMP 1 The transfer is complete and either a stop or a restart was detected 0 The completion of a transfer has not been detected Slave transfer initiated SINIT 1 The slave has detected an address match and a transfer has been initiated 0 A transfer is not in progress An address match has not occurred since the last time this bit...

Page 680: ...s enabled a bus busy condition may be detected This condition should clear after tBUF has expired assuming no additional bus activity has been detected Slave Mode When enabled slave mode operation supports both receive and transmit data transfers It is not possible to enable only one data transfer direction and not acknowledge NAK the other This is reflected in the following setup 1 Program TWI_SL...

Page 681: ...and enables slave mode operation As an example programming the value 0x0005 enables slave mode operation requires 7 bit addressing and indi cates that data in the transmit FIFO buffer is intended for slave mode transmission Table 11 2 shows what the interaction between the TWI controller and the processor might look like using this example Table 11 2 Slave Mode Setup Interaction TWI Controller Mas...

Page 682: ...the initial data transmitted It is considered an error to complete the address phase of the transfer and not have data available in the transmit FIFO buffer 3 Program TWI_FIFO_CTL Indicate if transmit FIFO buffer interrupts should occur with each byte transmitted 8 bits or with each 2 bytes transmitted 16 bits 4 Program TWI_INT_MASK Enable bits associated with the desired interrupt sources As an e...

Page 683: ...e value 0x0030 results in an interrupt output to the processor in the event that the master transfer completes and the master transfer has an error 4 Program TWI_MASTER_CTL Ultimately this prepares and enables master mode operation As an example programming the value 0x0205 enables master mode operation generates a 7 bit address sets the direction to master receive uses standard mode timing and re...

Page 684: ...he programmer in their service routine development Transmit Receive Repeated Start Sequence Figure 11 7 illustrates a repeated start data transmit followed by a data receive sequence Table 11 4 Master Mode Receive Setup Interaction TWI Controller Master Processor Interrupt RCVFULL Receive buffer is full Read receive FIFO buffer Acknowledge Clear interrupt source bits Interrupt MCOMP Master transfe...

Page 685: ...cate a repeated start should be issued and MDIR should be set to indicate the subsequent transfer should be a data receive MCOMP interrupt This interrupt was generated since all data has been transferred DCNT 0 If no errors were generated a start condition is initi ated At this time RSTART should be cleared and DCNT should be programmed with the desired number of bytes to receive RCVSERV interrupt...

Page 686: ...a data byte into the receive FIFO The RSTART bit should be set at this time or earlier and MDIR should be cleared to reflect the change in direction of the next transfer The MDIR bit must be cleared before the addressing phase of the subsequent transfer begins MCOMP interrupt This interrupt has occurred due to the completion of the data receive transfer At this time the data transmit transfer has ...

Page 687: ...n Processor Hardware Reference 11 27 Two Wire Interface Controller XMTSERV interrupt This interrupt is generated due to a FIFO access Simple data han dling is all that is required MCOMP interrupt The transfer is complete ...

Page 688: ...TA INTO TWI_XMT_DATA REGISTER INTERRUPT SOURCE SCOMP XMTSERV WRITE TO TWI_XMT_DATA REGISTER TO PRE LOAD THE TX FIFO WRITE TO TWI_FIFO_CTL TO SELECT WHETHER 1 OR 2 BYTES GENERATE INTERRUPTS WRITE TO TWI_INT_MASK TO UNMASK TWI EVENTS TO GENERATE INTERRUPTS WRITE TO TWI_SLAVE_CTL TO ENABLE SLAVE FUNCTIONALITY WAIT FOR INTERRUPTS WRITE TWI_INT_STAT TO CLEAR INTERRUPT READ DATA FROM TWI_RCV_DATA REGIST...

Page 689: ...NTERRUPTS WRITE TO TWI_SLAVE_CTL TO ENABLE SLAVE FUNCTIONALITY WAIT FOR INTERRUPTS WRITE TWI_MASTER_CTL WITH COUNT MDIR CLEARED AND MEN SET THIS STARTS THE TRANSFER RECEIVE WRITE TWI_INT_STAT TO CLEAR INTERRUPT INTERRUPT SOURCE XMTSERV MCOMP WRITE TWI_MASTER_CTL WITH COUNT MDIR SET AND MEN SET THIS STARTS THE TRANSFER WAIT FOR INTERRUPTS INTERRUPT SOURCE MCOMP RCVSERV WRITE TWI_INT_STAT TO CLEAR I...

Page 690: ...e registers TWI_CONTROL Register TWI_CLKDIV Register Figure 11 11 TWI Control Register Figure 11 12 SCL Clock Divider Register TWI Control Register TWI_CONTROL Reset 0x0000 0xFFC0 1404 PRESCALE 6 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCCB TWI_ENA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCL Clock Divider Register TWI_CLKDIV CLKLOW 7 0 ...

Page 691: ...r bits includes General call enable GEN General call address detection is available only when slave mode is enabled 1 General call address matching is enabled A general call slave receive transfer is accepted All status and interrupt source bits associated with transfers are updated 0 General call address matching is not enabled Figure 11 13 TWI Slave Mode Control Register 15 14 13 12 11 10 9 8 7 ...

Page 692: ...1 Data in the transmit FIFO is available for a slave transmission 0 Data in the transmit FIFO is for master mode transmits and is not allowed to be used during a slave transmit and the transmit FIFO is treated as if it is empty Slave enable SEN 1 The slave is enabled Enabling slave and master modes of oper ation concurrently is allowed 0 The slave is not enabled No attempt is made to identify a va...

Page 693: ...atus register TWI_SLAVE_STAT holds information on the current trans fer Generally slave mode status bits are not associated with the generation of interrupts Master mode operation does not affect slave mode status bits Figure 11 14 TWI Slave Mode Address Register Figure 11 15 TWI Slave Mode Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI Slave Mode Address...

Page 694: ...rmal master and slave mode operation should not require override operation 1 Serial clock output is driven to an active 0 level overriding all other logic This state is held until this bit is cleared 0 Normal serial clock operation under the control of master mode clock generation and slave mode clock stretching logic Figure 11 16 TWI Master Mode Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 695: ...CNT 7 0 Indicates the number of data bytes to transfer As each data word is transferred DCNT is decremented When DCNT is 0 a stop condition is generated Setting DCNT to 0xFF disables the counter In this transfer mode data continues to be transferred until it is concluded by setting the STOP bit Repeat start RSTART 1 Issue a repeat start condition at the conclusion of the current transfer DCNT 0 an...

Page 696: ... up to 100K bits s timing specifications in use Master transfer direction MDIR 1 The initiated transfer is master receive 0 The initiated transfer is master transmit Master mode enable MEN This bit self clears at the completion of a transfer This includes transfers terminated due to errors 1 Master mode functionality is enabled A start condition is gen erated if the bus is idle 0 Master mode funct...

Page 697: ...dress should be written to this register For example if the slave address is b 1010000X where X is the read write bit then TWI_MASTER_ADDR is pro grammed with b 1010000 which corresponds to 0x50 When sending out the address on the bus the TWI controller appends the read write bit as appropriate based on the state of the MDIR bit in the master mode control register Figure 11 17 TWI Master Mode Addr...

Page 698: ...WI Master Mode Status Register TWI_MASTER_STAT Reset 0x0000 0xFFC0 1418 MPROG Master Transfer in Progress RO LOSTARB Lost Arbitration W1C SCLSEN Serial Clock Sense RO BUSBUSY Bus Busy RO SDASEN Serial Data Sense RO ANAK Address Not Acknowledged W1C DNAK Data Not Acknowledged W1C BUFWRERR Buffer Write Error W1C BUFRDERR Buffer Read Error W1C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0...

Page 699: ...nsmit buffer interrupt length XMTINTLEN This bit determines the rate at which transmit buffer interrupts are to be generated Interrupts may be generated with each byte trans mitted or after two bytes are transmitted 1 An interrupt XMTSERV is set when the XMTSTAT field in the TWI_FIFO_STAT register indicates two bytes in the FIFO are empty 00 0 An interrupt XMTSERV is set when XMTSTAT indicates one...

Page 700: ...its TWI_FIFO_STAT Register TWI_INT_MASK Register The TWI interrupt mask register TWI_INT_MASK enables interrupt sources to assert the interrupt output Each mask bit corresponds with one interrupt source bit in the TWI interrupt status TWI_INT_STAT register Reading and writing the TWI interrupt mask register does not affect the contents of the TWI interrupt status register Figure 11 20 TWI FIFO Sta...

Page 701: ...utput 0 A contents of 1 in the corresponding interrupt source results in asserting the interrupt output Figure 11 21 TWI Interrupt Mask Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI Interrupt Mask Register TWI_INT_MASK For all bits 0 Interrupt generation disabled 1 Interrupt generation enabled SINITM Slave Transfer Initiated Interrupt Mask Reset 0x0000 SCOMPM S...

Page 702: ...s prevented from asserting the interrupt output 0 A contents of 1 in the corresponding interrupt source results in asserting the interrupt output Slave overflow interrupt mask SOVFM 1 The corresponding interrupt source is prevented from asserting the interrupt output 0 A contents of 1 in the corresponding interrupt source results in asserting the interrupt output Slave transfer error interrupt mas...

Page 703: ...sserting the interrupt output TWI_INT_STAT Register TWI_XMT_DATA8 Register The TWI FIFO transmit data single byte register TWI_XMT_DATA8 holds an 8 bit data value written into the FIFO buffer Transmit data is entered into the corresponding transmit buffer in a first in first out order Figure 11 22 TWI Interrupt Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T...

Page 704: ...lue written into the FIFO buffer To reduce inter rupt output rates and peripheral bus access times a double byte transfer data access can be performed Two data bytes can be written effectively filling the transmit FIFO buffer with a single access The data is written in little endian byte order as shown in Figure 11 24 where byte 0 is the first byte to be transferred and byte 1 is the second byte t...

Page 705: ...ata is read from the corresponding receive buffer in a first in first out order Although periph eral bus reads are 16 bits a read access to TWI_RCV_DATA8 will access only one transmit data byte from the FIFO buffer With each access the Figure 11 24 Little Endian Byte Order Figure 11 25 TWI FIFO Transmit Data Double Byte Register B1 B0 DATA IN REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 ...

Page 706: ...g the receive FIFO buffer with a single access The data is read in little endian byte order as shown in Figure 11 27 where byte 0 is the first byte received and byte 1 is the second byte received With each access the receive status RCVSTAT field in the TWI_FIFO_STAT register is updated to indicate it is empty If an access is performed while the FIFO buffer is not full the read data is unknown and ...

Page 707: ...ode Listing 11 1 Master Mode Receive Transmit Transfer macro for the Count field of the TWI_MASTER_CTL register x can be any value between 0 and 0xFE 254 a value of 0xFF disables the counter define TWICount x DCNT x 6 section L1_data_b byte TX_file file_size DATA hex BYTE RX_CHECK file_size Figure 11 28 TWI FIFO Receive Data Double Byte Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ...

Page 708: ...K 100 MHz CLKIN 50MHz Prescale SCLK 10 MHz P1 points to the base of the system MMRs R1 TWI_ENA 0xA z W P1 LO TWI_CONTROL R1 Set CLKDIV For example for an SCL of 400 KHz period 1 400 KHz 2500 ns and an internal time reference of 10 MHz period 100 ns CLKDIV 2500 ns 100 ns 25 For an SCL with a 30 duty cycle then CLKLOW 17 0x11 and CLKHI 8 R5 CLKHI 0x8 CLKLOW 0x11 z W P1 LO TWI_CLKDIV R5 enable these ...

Page 709: ...r reads R6 0xBF R6 R6 1 TWI_INIT END W P1 LO TWI_MASTER_ADDR R6 END OF TWI INIT Starting the Read transfer Program the Master Control register with 1 the number of bytes to transfer TWICount x 2 Repeated Start RESTART optional 3 speed mode FAST or SLOW 4 direction of transfer MDIR 1 for reads MDIR 0 for writes 5 Master Enable MEN This will kick off the master transfer R1 TWICount 0x2 FAST MDIR MEN...

Page 710: ...ches zero M_COMP R1 W P1 LO TWI_INT_STAT z CC BITTST R1 bitpos MCOMP if CC jump M_COMP M_COMP END W P1 LO TWI_INT_STAT R1 load the pointer with the address of the transmit buffer P2 H TX_file P2 L TX_file Pre load the tx FIFO with the first two bytes this is necessary to avoid the generation of the Buffer Read Error BUFRDERR which occurs whenever a transmit transfer is initiated while the transmit...

Page 711: ...Master Enable MEN Setting this bit will kick off the transfer R1 TWICount 0xFE FAST MEN W P1 LO TWI_MASTER_CTL R1 SSYNC loop to write data to a TWI slave device P3 times P3 length TX_file LSETUP Loop_Start Loop_End LC0 P3 Loop_Start check that there s at least one byte location empty in the tx fifo XMTSERV_Status R1 W P1 LO TWI_INT_STAT z CC BITTST R1 bitpos XMTSERV test XMTSERV bit if CC jump XMT...

Page 712: ..._COMP END W P1 LO TWI_INT_STAT R1 idle _main end Slave Mode Setup Listing 11 2 shows how to configure the slave for interrupt based trans fers The interrupts are serviced in the subroutine _TWI_ISR shown in Listing 11 3 Listing 11 2 Slave Mode Setup include defBF537 h include startup h define file_size 254 define SYSMMR_BASE 0xFFC00000 define COREMMR_BASE 0xFFE00000 GLOBAL _main EXTERN _TWI_ISR se...

Page 713: ... 10 0xA for an SCLK 100 MHz CLKIN 50MHz Prescale SCLK 10 MHz P1 points to the base of the system MMRs P0 points to the base of the core MMRs R1 TWI_ENA 0xA z W P1 LO TWI_CONTROL R1 Slave address program the address to which this slave will respond to this is an arbitrary 7 bit value R1 0x5F W P1 LO TWI_SLAVE_ADDR R1 Pre load the TX FIFO with the first two bytes to be transmitted in the event the s...

Page 714: ... W P1 LO TWI_FIFO_CTL R1 enable these signals to generate a TWI interrupt R1 RCVSERV XMTSERV SOVF SERR SCOMP SINIT z W P1 LO TWI_INT_MASK R1 Enable the TWI Slave Program the Slave Control register with 1 Slave transmit data valid STDVAL set so that the contents of the TX FIFO can be used by this slave when a master requests data from it 2 Slave Enable SEN to enable Slave functionality R1 STDVAL SE...

Page 715: ...vice routine R1 H HI _TWI_ISR R1 L LO _TWI_ISR P0 LO EVT10 R1 note that P0 points to the base of the core MMR registers ENABLE TWI generate to interrupts at the system level R1 P1 LO SIC_IMASK BITSET R1 BITPOS IRQ_TWI P1 LO SIC_IMASK R1 ENABLE TWI to generate interrupts at the core level R1 P0 LO IMASK BITSET R1 BITPOS EVT_IVG10 P0 LO IMASK R1 wait for interrupts idle _main END ...

Page 716: ... interrupt is ser viced its corresponding bit is cleared in the TWI_INT_STAT register This done by writing a 1 to the particular bit posi tion All bits are write 1 to clear include defBF537 h GLOBAL _TWI_ISR section L1_code _TWI_ISR read the source of the interrupt R1 W P1 LO TWI_INT_STAT z Slave Transfer Initiated CC BITTST R1 BITPOS SINIT if CC JUMP RECEIVE R0 SINIT Z W P1 LO TWI_INT_STAT R0 cle...

Page 717: ...1 LO TWI_INT_STAT R0 clear interrupt source bit ssync JUMP _TWI_ISR END exit Transmit service TRANSMIT CC BITTST R1 BITPOS XMTSERV if CC JUMP SlaveError R0 B P4 Z W P1 LO TWI_XMT_DATA8 R0 R0 XMTSERV Z W P1 LO TWI_INT_STAT R0 clear interrupt source bit ssync JUMP _TWI_ISR END exit slave transfer error SlaveError CC BITTST R1 BITPOS SERR if CC SlaveOverflow R0 SERR Z W P1 LO TWI_INT_STAT R0 clear in...

Page 718: ...er complete SlaveTransferComplete CC BITTST R1 BITPOS SCOMP if CC JUMP _TWI_ISR END R0 SCOMP Z W P1 LO TWI_INT_STAT R0 clear interrupt source bit ssync Transfer complete read receive FIFO buffer and set clear sema phores etc R0 W P1 LO TWI_FIFO_STAT z CC BITTST R0 BITPOS RCV_HALF BIT 2 indicates whether there s a byte in the FIFO or not if CC JUMP _TWI_ISR END R0 W P1 LO TWI_RCV_DATA8 Z read data ...

Page 719: ... Processor Hardware Reference 11 59 Two Wire Interface Controller Electrical Specifications All logic complies with the Electrical Specification outlined in the Philips I2C Bus Specification version 2 1 dated January 2000 ...

Page 720: ...Electrical Specifications 11 60 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 721: ...like the SPI interface which has been designed for SPI compatible communication only the SPORT modules support a variety of serial data communication protocols for example A law or µ law companding according to G 711 specification Multichannel or Time Division Multiplexed TDM modes Stereo Audio I2S Mode H 100 Telephony standard support In addition to these standard protocols the SPORT modules prov...

Page 722: ...bility for serial communications Each of the SPORTs offers these features and capabilities Provides independent transmit and receive functions Transfers serial data words from 3 to 32 bits in length either MSB first or LSB first Provides alternate framing and control for interfacing to I2S serial devices as well as other audio formats for example left justified stereo serial data Has FIFO plus dou...

Page 723: ...ng DMA parameters Has a multichannel mode for TDM interfaces Each SPORT can receive and transmit data selectively from a time division multi plexed serial bitstream on 128 contiguous channels from a stream of up to 1024 total channels This mode can be useful as a network communication scheme for multiple processors The 128 channels available to the processor can be selected to start at any channel...

Page 724: ...tion However all pins default to the SPORT0 module settings after reset The secondary data pins of SPORT0 are multiplexed with the CAN inter face Unless the PJCE bit in the PORT_MUX register is set the CAN signals are disabled and the secondary data signals control the associated pins by default Similarly the PJSE bit can disconnect some of the transmit signals and redirect the respective pins to ...

Page 725: ...he hardware and automatically transferred to the TX shift register The bits in the shift register are shifted out on the SPORT s DTx PRI DTxSEC pin MSB first or LSB first synchronous to the serial clock on the TSCLKx pin The receive portion of the SPORT accepts data from the DRxPRI DRxSEC pin synchronous to the serial clock on the RSCLKx pin When an entire word is received the data is optionally e...

Page 726: ...zation signals RFSx and TFSx are used to indicate the start of a serial data word or stream of serial words Figure 12 1 SPORT Block Diagram COMPANDING HARDWARE COMPANDING HARDWARE NOTE 1 ALL WIDE ARROW DATA PATHS ARE 16 OR 32 BITS WIDE DEPENDING ON SLEN FOR SLEN 2 TO 15 A 16 BIT DATA PATH WITH 8 DEEP FIFO IS USED FOR SLEN 16 TO 31 A 32 BIT DATA PATH WITH 4 DEEP FIFO IS USED NOTE 2 Tx REGISTER IS T...

Page 727: ...nformation about DAGs see the Data Address Generators chapter in the Blackfin Processor Programming Reference Similarly for TX data should be written to the TX register in an alternating manner first primary then secondary then primary then secondary and so on This is easily accomplished with the processor s powerful DAGs In addition to the serial clock signal data must be signalled by a frame syn...

Page 728: ...K0 TSCLK0 TFS0 RFS0 SPORT0 DT0SEC DR0SEC DR0PRI DT0PRI RSCLK1 TSCLK1 TFS1 RFS1 DT1SEC DR1SEC DR1PRI DT1PRI BLACKFIN SPORT1 SERIAL DEVICE D SECONDARY SERIAL DEVICE C PRIMARY SERIAL DEVICE B SECONDARY SERIAL DEVICE A PRIMARY PJ4 PJ5 PJ8 PJ11 PJ7 PJ6 PJ10 PJ9 PORT J PG8 PG9 PG12 PG15 PG11 PG10 PG14 PG13 PORT G ...

Page 729: ...or frame sync lines are longer than six inches consider using a series termination for strip lines on point to point connections This may be necessary even when using low speed serial clocks because of the edge rates Figure 12 3 Stereo Serial Connection DBCLK DLRCLK DSDATA1 ALRCLK ABCLK DSDATA3 DSDATA2 ASDATA1 ASDATA2 AD1836 STEREO SERIAL DEVICE BLACKFIN RSCLK0 TSCLK0 TFS0 RFS0 PORT J DT0SEC PJ4 D...

Page 730: ...is shifted out on the driving edge of TSCLKx The driving edge of TSCLKx can be configured to be rising or fall ing The SPORT generates the transmit interrupt or requests a DMA transfer as long as there is space in the TX FIFO As a SPORT receives bits they accumulate in an internal receive register When a complete word has been received it is written to the SPORT FIFO register and the receive inter...

Page 731: ...ernally The SPORTs are ready to start transmitting or receiving data no later than three serial clock cycles after they are enabled in the SPORTx_TCR1 or SPORTx_RCR1 register No serial clock cycles are lost from this point on The first internal frame sync will occur one frame sync delay after the SPORTs are ready External frame syncs can occur as soon as the SPORT is ready When disabling the SPORT...

Page 732: ...r I2 S and left justified stereo serial data Setting this bit enables the SPORT to generate or accept the special LRCLK style frame sync All other SPORT control bits remain in effect and should be set appropri ately Figure 12 4 and Figure 12 5 show timing diagrams for stereo serial mode operation Table 12 2 shows several modes that can be configured using bits in SPORTx_TCR1 and SPORTx_RCR1 The ta...

Page 733: ...alf the period and twice the frequency For instance setting RFSDIV or TFSDIV 31 produces an LRCLK that transitions every 32 serial clock cycles and has a period of 64 serial clock cycles The LRFS bit determines the polarity of the frame sync pin that is consid ered a right channel Thus setting LRFS 0 indicates that a low signal on the RFS or TFS pin is the left channel This is the default setting ...

Page 734: ...ingle clock in some designs See Figure 12 3 on page 12 9 which shows multiple stereo serial connections being made between the processor and an AD1836 codec Figure 12 4 SPORT Stereo Serial Modes Transmit TFS TSCLKx DTxPRI TFS TSCLKx DTxPRI TFS TSCLKx DTxPRI LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL MSB MSB MSB MSB MSB MSB LSB LSB LSB LSB LSB LSB LEFT JUSTIFIED MODE 3 TO 32 BITS PER CHA...

Page 735: ...annels while ignoring the others Up to 128 channels are available for transmitting or receiving each SPORT can receive and transmit data selectively from any of the 128 channels These 128 channels can be any 128 out of the 1024 Figure 12 5 SPORT Stereo Serial Modes Receive RFS RSCLKx DRxPRI RFS RSCLKx DRxPRI RFS RSCLKx DRxPRI LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL MSB MSB MSB MSB MS...

Page 736: ...ORT is enabled and the secondary transmit is enabled TXSE 1 in the SPORTx_TCR2 register unless the SPORT is in multichannel mode and an inactive time slot occurs a The SPORT multichannel transmit select register and the SPORT multichannel receive select register must be programmed before enabling SPORTx_TX or SPORTx_RX operation for multichannel mode This is especially important in DMA data unpack...

Page 737: ...rial bus Can independently select transmit and receive channels RFS signals start of frame TFS is used as transmit data valid for external logic true only dur ing transmit channels Receive on channels 0 and 2 transmit on channels 1 and 2 Multichannel frame delay is set to 1 See Timing Examples on page 12 39 for more examples Figure 12 6 Multichannel Operation RSCLK B3 B2 B1 B2 DR RFS B0 IGNORED B3...

Page 738: ...g SPORT must also be in multichannel mode a When in multichannel mode do not enable the stereo serial frame sync modes or the late frame sync feature as these features are incompatible with multichannel mode Table 12 3 shows the dependencies of bits in the SPORT configuration register when the SPORT is in multichannel mode Table 12 3 Multichannel Mode Configuration SPORTx_RCR1 or SPORTx_RCR2 SPORT...

Page 739: ...x_RX channels of the SPORT in multichannel mode configuration the corresponding bit pairs in SPORTx_RCR1 and SPORTx_TCR1 and in SPORTx_RCR2 and SPORTx_TCR2 should always be programmed identically with the possible exception of the RXSE and TXSE pair and the RDTYPE and TDTYPE pair This is true even if SPORTx_RX operation is not enabled In multichannel mode RFS timing similar to late alternative fra...

Page 740: ...he SPORT until the complete frame has been transferred If MFD 0 the RFS may occur during the last channels of a previous frame This is acceptable and the frame sync is not ignored as long as the delayed channel 0 starting point falls outside the complete frame In multichannel mode the RFS signal is used for the block or frame start reference after which the word transfers are performed continuousl...

Page 741: ... may occur before data from the last frame has been received because blocks of data occur back to back Window Size The window size WSIZE 3 0 defines the number of channels that can be enabled disabled by the multichannel select registers This range of words is called the active window The number of channels can be any value in the range of 0 to 15 corresponding to active window size of 8 to 128 in...

Page 742: ...ndow offset WOFF 9 0 specifies where in the 1024 channel range to place the start of the active window A value of 0 specifies no offset and 896 is the largest value that permits using all 128 channels As an example a program could define an active window with a window size of 8 WSIZE 0 and an offset of 93 WOFF 93 This 8 channel window would reside in the range from 93 to 100 Neither the window off...

Page 743: ...ndividually enabled or disabled to select which words are received and transmitted during mul tichannel communications Data words from the enabled channels are received or transmitted while disabled channel words are ignored Up to 128 contiguous channels may be selected out of 1024 available channels The SPORTx_MRCSn and SPORTx_MTCSn multichannel select registers are used to enable and disable ind...

Page 744: ...rd is loaded into the SPORTx_RX buffer Clearing the bit in the SPORTx_MRCSn register causes the SPORT to ignore the data Companding may be selected for all channels or for no channels A law or μ law companding is selected with the TDTYPE field in the SPORTx_TCR1 register and the RDTYPE field in the SPORTx_RCR1 register and applies to all active channels See Companding on page 12 29 for more inform...

Page 745: ...uffer would be ignored This mode allows changing the number of enabled channels while the SPORT is enabled with some caution First read the channel register to make sure that the active window is not being serviced If the channel count is 0 then the multichannel select registers can be updated Support for H 100 Standard Protocol The processor supports the H 100 standard protocol The following SPOR...

Page 746: ...ct 2 MHz from 4 MHz and MCCRM 11 chooses HMVIP clock divide extract 8 MHz from 16 MHz Functional Description The following sections provide a functional description of the SPORTs Clock and Frame Sync Frequencies The maximum serial clock frequency for either an internal source or an external source is SCLK 2 The frequency of an internally generated clock is a function of the system clock frequency ...

Page 747: ...ync pulses is of transmit serial clocks between frame sync assertions TFSDIV 1 of receive serial clocks between frame sync assertions RFSDIV 1 Use the following equations to determine the correct value of TFSDIV or RFSDIV given the serial clock frequency and desired frame sync frequency SPORTxTFS frequency TSCLKx frequency SPORTx_TFSDIV 1 SPORTxRFS frequency RSCLKx frequency SPORTx_RFSDIV 1 The fr...

Page 748: ...ines the word length accord ing to this formula Serial Word Length SLEN 1 a The SLEN value should not be set to 0 or 1 values from 2 to 31 are allowed Continuous operation when the last bit of the current word is immediately followed by the first bit of the next word is restricted to word sizes of 4 or longer so SLEN 3 Bit Order Bit order determines whether the serial word is transmitted MSB first...

Page 749: ...id data in the SPORTx_RX register is the right justified expanded value of the eight LSBs received and sign extended to 16 bits A write to SPORTx_TX causes the 16 bit value to be compressed to eight LSBs sign extended to the width of the transmit word and written to the internal transmit register Although the com panding standards support only 13 bit A law or 14 bit μ law maximum word lengths up t...

Page 750: ... generated internally by the processor and the TSCLK or RSCLK pin is an output The clock frequency is determined by the value of the serial clock divisor in the SPORTx_RCLKDIV register When IRCLK or ITCLK 0 the clock signal is accepted as an input on the TSCLK or RSCLK pins and the serial clock divisors in the SPORTx_TCLKDIV SPORTx_RCLKDIV registers are ignored The externally gen erated serial clo...

Page 751: ...e frame sync is needed to initiate communications but is ignored after the first bit is transferred Data words are then transferred continuously unframed a With frame syncs not required interrupt or DMA requests may not be serviced frequently enough to guarantee continuous unframed data flow Monitor status bits or check for a SPORT Error interrupt to detect underflow or overflow of data Figure 12 ...

Page 752: ...pin or RFS pin is an output The frequency of the frame sync signal is determined by the value of the frame sync divisor in the SPORTx_TFSDIV or SPORTx_RFSDIV register When ITFS 0 or IRFS 0 the corresponding frame sync signal is accepted as an input on the TFS pin or RFS pin and the frame sync divisors in the SPORTx_TFSDIV SPORTx_RFSDIV registers are ignored All of the frame sync options are availa...

Page 753: ... and SPORTx_RCR1 registers select the driving and sampling edges of the serial data and frame syncs For the SPORT transmitter setting TCKFE 1 in the SPORTx_TCR1 register selects the falling edge of TSCLKx to drive data and internally generated frame syncs and selects the rising edge of TSCLKx to sample externally gen erated frame syncs Setting TCKFE 0 selects the rising edge of TSCLKx to drive dat...

Page 754: ... SPORTs connected together should always select the same value for TCKFE in the transmitter and RCKFE in the receiver so that the transmitter drives the data on one edge and the receiver samples the data on the opposite edge In Figure 12 10 TCKFE RCKFE 0 and transmit and receive are con nected together to share the same clock and frame syncs In Figure 12 11 TCKFE RCKFE 1 and transmit and receive a...

Page 755: ...ial clock cycle after the frame sync is asserted and the frame sync is not checked again until the entire word has been transmitted or received In multichannel operation this corresponds to the case when multichannel frame delay is 1 If data transmission is continuous in early framing mode in other words the last bit of each word is immediately followed by the first bit of the next word then the f...

Page 756: ...f each word Internally generated frame syncs remain asserted for the entire length of the data word in late framing mode Externally generated frame syncs are only checked during the first bit Figure 12 12 illustrates the two modes of frame signal timing In summary For the LATFS or LARFS bits of the SPORTx_TCR1 or SPORTx_RCR1 reg isters LATFS 0 or LARFS 0 for early frame syncs LATFS 1 or LARFS 1 fo...

Page 757: ...s gen erated once data is loaded into SPORTx_TX This mode of operation allows data to be transmitted only when it is available When DITFS 1 the internally generated TFS is output at its programmed interval regardless of whether new data is available in the SPORTx_TX buffer Whatever data is present in SPORTx_TX is transmitted again with each assertion of TFS The TUVF transmit underflow status bit i...

Page 758: ...MA transfer allowing the processor core to continue running until the entire block of data is transmitted or received Interrupt service routines ISRs can then operate on the block of data rather than on single words significantly reducing overhead For information about DMA see Chapter 5 Direct Memory Access SPORT RX TX and Error Interrupts The SPORT RX interrupt is asserted when RSPEN is enabled a...

Page 759: ... of this chapter in the sections Framed Versus Unframed on page 12 31 Early Versus Late Frame Syncs Normal Versus Alternate Timing on page 12 35 and Frame Syncs in Multichannel Mode on page 12 19 This section con tains additional examples to illustrate other possible combinations of the framing options These timing examples show the relationships between the signals but are not scaled to show the ...

Page 760: ...an externally generated frame sync and also the output timing characteristic of an internally generated frame sync Note Figure 12 13 SPORT Receive Normal Framing Figure 12 14 SPORT Continuous Receive Normal Framing B3 B3 B2 B1 B0 B2 B1 B0 SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DR REPRESENTS DRxPRI AND OR DRxSEC DEPENDING ON DESIRED CONFIGURATION RSCLK...

Page 761: ...gnal occurs only at the start of the first word either one Figure 12 15 SPORT Receive Alternate Framing Figure 12 16 SPORT Continuous Receive Alternate Framing B3 B3 B2 B1 B0 B2 B1 B0 SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DR REPRESENTS DRxPRI AND OR DRxSEC DEPENDING ON DESIRED CONFIGURATION RSCLK RFS OUTPUT DR RFS INPUT RSCLK RFS OUTPUT RFS INPUT DR ...

Page 762: ...gh Figure 12 18 In Figure 12 19 and Figure 12 20 the normal framing mode is shown for non continuous data any number of TSCLK cycles between words and continuous data no TSCLK cycles between words Figure 12 21 and Figure 12 17 SPORT Receive Unframed Mode Normal Framing Figure 12 18 SPORT Receive Unframed Mode Alternate Framing RSCLK RFS DR B3 B2 B1 B0 B3 B2 B1 B0 B2 B3 DR REPRESENTS DRxPRI AND OR ...

Page 763: ...it Normal Framing Figure 12 20 SPORT Continuous Transmit Normal Framing TSCLK TFS OUTPUT DT B2 B1 B0 B3 B2 B1 B0 B3 TFS INPUT SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTxPRI AND OR DTxSEC DEPENDING ON DESIRED CONFIGURATION B2 B1 B0 B3 B2 B1 B0 B3 B3 B2 TSCLK TFS OUTPUT TFS INPUT TR SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EX...

Page 764: ...as the first bit in alternate mode Figure 12 21 SPORT Transmit Alternate Framing Figure 12 22 SPORT Continuous Transmit Alternate Framing B2 B1 B0 B3 B2 B1 B0 B3 SPORT CONTROL REGISTER BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTxPRI AND OR DTxSEC DEPENDING ON DESIRED CONFIGURATION TSCLK TFS OUTPUT DT TFS INPUT B2 B1 B0 B3 B0 B3 B2 B1 TSCLK TFS OUTPUT TFS INPUT T...

Page 765: ...e 12 5 SPORT Register Mapping Register Name Function Notes SPORTx_TCR1 Primary transmit configuration regis ter Bits 15 1 can only be written if bit 0 0 SPORTx_TCR2 Secondary trans mit configuration register SPORTx_TCLK_DIV Transmit clock divider register Ignored if external SPORT clock mode is selected TSCLK TFS DT B3 B3 B0 B1 B2 B1 B0 B3 B2 B2 DT REPRESENTS DTxPRI AND OR DTxSEC DEPENDING ON DESI...

Page 766: ...gister Ignored if external frame sync mode is selected SPORTx_RX SPORT receive data register See description of FIFO buffering at SPORTx_RX Register on page 12 60 SPORTx_STAT Receive and trans mit status SPORTx_MCM1 Primary multichan nel mode configu ration register Configure this register before enabling the SPORT SPORTx_MCM2 Secondary multi channel mode con figuration register Configure this reg...

Page 767: ...STAT are read only registers After a write to a SPORT register while the SPORT is disabled any changes to the control and mode bits generally take effect when the SPORT is re enabled L Most configuration registers can only be changed while the SPORT is disabled TSPEN RSPEN 0 Changes take effect after the SPORT is re enabled The only exceptions to this rule are the TCLKDIV RCLKDIV registers and mul...

Page 768: ...smit Clock Select TDTYPE 1 0 Data Format ting Type Select TLSBIT Transmit Bit Order TSPEN Transmit Enable LTFS Low Transmit Frame Sync Select LATFS Late Transmit Frame Sync 0 Early frame syncs 1 Late frame syncs TCKFE Clock Falling Edge Select 0 External transmit clock selected 1 Internal transmit clock selected 00 Normal operation 01 Reserved 10 Compand using μ law 11 Compand using A law 0 Transm...

Page 769: ...ze the ISR and be ready to service TX interrupts before setting TSPEN Similarly if DMA transfers are used DMA control should be con figured correctly before setting TSPEN Set all DMA control registers before setting TSPEN Figure 12 26 SPORTx Transmit Configuration 2 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPORTx Transmit Configuration 2 Register SPORTx_TCR2 S...

Page 770: ... or the external transmit clock on the TSCLK pin if cleared The TCLKDIV MMR value is not used when an external clock is selected Data formatting type select The two TDTYPE bits specify data for mats used for single and multichannel operation Bit order select TLSBIT The TLSBIT bit selects the bit order of the data words transmitted over the SPORT Serial word length select SLEN The serial word lengt...

Page 771: ...e SPORT requires if set or does not require if cleared a transmit frame sync for every data word L The TFSR bit is normally set during SPORT configuration A frame sync pulse is used to mark the beginning of each word or data packet and most systems need a frame sync to function properly Data Independent transmit frame sync select DITFS This bit selects whether the SPORT generates a data independen...

Page 772: ...yncs If set data and internally generated frame syncs are driven on the falling edge and externally generated frame syncs are sampled on the rising edge If cleared data and internally generated frame syncs are driven on the rising edge and externally generated frame syncs are sampled on the falling edge TxSec enable TXSE This bit enables the transmit secondary side of the SPORT if set Stereo seria...

Page 773: ...he SPORT is enabled to receive RSPEN set corresponding SPORT configuration register writes are not allowed except for SPORTx_RCLKDIV and multichannel mode channel select registers Writes to disallowed registers have no effect While the SPORT is enabled SPORTx_RCR1 is not written except for bit 0 RSPEN For example write SPORTx_RCR1 0x0001 SPORT RX Enabled write SPORTx_RCR1 0xFF01 ignored no effect ...

Page 774: ...frame syncs 1 Late frame syncs RCKFE Clock Falling Edge Select 0 External receive clock selected 1 Internal receive clock selected 00 Zero fill 01 Sign extend 10 Compand using μ law 11 Compand using A law 0 Receive MSB first 1 Receive LSB first Reset 0x0000 0 External RFS used 1 Internal RFS used 0 Drive internal frame sync on rising edge of RSCLK Sample data and external frame sync with falling e...

Page 775: ...enerates DMA requests if DMA is enabled and data is received Set all DMA control registers before setting RSPEN Clearing RSPEN causes the SPORT to stop receiving data it also shuts down the internal SPORT receive circuitry In low power applications battery life can be extended by clearing RSPEN when ever the SPORT is not in use Figure 12 28 SPORTx Receive Configuration 2 Register 15 14 13 12 11 10...

Page 776: ...der of the data words received over the SPORTs Serial word length select SLEN The serial word length the num ber of bits in each word received over the SPORTs is calculated by adding 1 to the value of the SLEN field The SLEN field can be set to a value of 2 to 31 0 and 1 are illegal values for this field L The frame sync signal is controlled by the SPORTx_TFSDIV and SPORTx_RFSDIV registers not by ...

Page 777: ...rising edge If cleared internally generated frame syncs are driven on the rising edge and data and externally generated frame syncs are sampled on the fall ing edge RxSec enable RXSE This bit enables the receive secondary side of the SPORT if set Stereo serial enable RSFSE This bit enables the stereo serial oper ating mode of the SPORT if set By default this bit is cleared enabling normal clocking...

Page 778: ...d length For word length up to and including 16 bits use a 16 bit write Use a 32 bit write for word length greater than 16 bits Figure 12 29 SPORT Transmit FIFO Data Ordering 0 15 0 15 0 15 0 15 PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY W7 W6 W5 W4 W3 W2 W1 W0 PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY W3 LOW W3 HIGH W2 LOW W2 HIGH W1 LOW W1 HIGH W0 LOW W...

Page 779: ...TUVF is set whenever the serial shift register is not loaded and transmission begins on the current enabled channel The TUVF status bit is a sticky write 1 to clear W1C bit and is also cleared by disabling the SPORT writing TXEN 0 If software causes the core processor to attempt a write to a full TX FIFO with a SPORTx_TX write the new data is lost and no overwrites occur to data in the FIFO The TO...

Page 780: ... 4 deep for length 16 bits The FIFO is shared by both primary and secondary receive data The order for reading using PAB DMA reads is important since data is stored in differently depending on the setting of the SLEN and RXSE configuration bits Figure 12 30 SPORTx Transmit Data Register SPORTx Transmit Data Register SPORTx_TX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 781: ... PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY W7 0 PRIMARY AND SECONDARY ENABLED DATA LENGTH 16 BITS PRIMARY AND SECONDARY ENABLED DATA LENGTH 16 BITS 15 W6 W5 W4 W3 W2 W1 W0 W3 LOW 0 15 W3 HIGH W2 LOW W2 HIGH W1 LOW W1 HIGH W0 LOW W0 HIGH SECONDARY W3 0 15 PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY SECONDARY SECONDARY...

Page 782: ...is a sticky bit and is cleared only when the SPORT is disabled To determine if the core can access the RX registers without causing this error first read the RX FIFO status RXNE in the SPORTx status register The RUVF status bit is updated even when the SPORT is disabled The ROVF status bit is set in the SPORTx_STAT register when a new word is assembled in the RX shift register and the RX hold regi...

Page 783: ...e DITFS control bit in the SPORT con figuration register The TUVF status bit is a sticky write 1 to clear W1C bit and is also cleared by disabling the SPORT writing TXEN 0 For continuous transmission TFSR 0 TUVF is set at the end of a trans mitted word if no new word is available in the TX hold register The TOVF bit is set when a word is written to the TX FIFO when it is full It is a sticky W1C bi...

Page 784: ...2 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 SPORTx Status Register SPORTx_STAT 0 Disabled 1 Enabled RUVF Sticky Receive Under flow Status W1C RXNE Receive FIFO Not Empty Status ROVF Sticky Receive Over flow Status W1C TUVF Sticky Transmit Underflow Status W1C 0 Disabled 1 Enabled 0 Empty 1 Data present in FIFO Reset 0x0040 0 Disabled 1 Enabled TOVF Sticky Transmit Overflow Status W...

Page 785: ...er internally or externally gen erated serial clocks These registers are shown in Figure 12 36 and Figure 12 37 Figure 12 35 SPORTx Receive Serial Clock Divider Register Figure 12 36 SPORTx Transmit Frame Sync Divider Register SPORTx Receive Serial Clock Divider Register SPORTx_RCLKDIV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Serial Clock Divide Modulus 15 0 Reset 0x00...

Page 786: ...ltichannel Configuration Register 1 SPORTx Receive Frame Sync Divider Register SPORTx_RFSDIV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Frame Sync Divider 15 0 Reset 0x0000 Number of receive clock cycles counted before gener ating RFS pulse SPORT0 0xFFC0 082C SPORT1 0xFFC0 092C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPORTx Multichannel Conf...

Page 787: ... 0 and 156 Figure 12 39 SPORTx Multichannel Configuration Register 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPORTx Multichannel Configuration Register 2 SPORTx_MCMC2 0x Bypass mode 10 Recover 2 MHz clock from 4 MHz 11 Recover 8 MHz clock from 16 MHz MCDTXPE Multichannel DMA Transmit Packing MCCRM 1 0 2X Clock Recovery Mode FSDR Frame Sync to Data Relationship 0 Disab...

Page 788: ...cify the active receive chan nels There are four registers each with 32 bits corresponding to the 128 channels Setting a bit enables that channel so that the SPORT selects that word for receive from the multiple word block of data For example set ting bit 0 selects word 0 setting bit 12 selects word 12 and so on Setting a particular bit in the SPORTx_MRCSn register causes the SPORT to receive the ...

Page 789: ...t word from multiple word block of data 31 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 63 0 32 31 95 0 64 31 127 0 96 Reset 0x0000 0000 Reset 0x0000 0000 Reset 0x0000 0000 Reset 0x0000 0000 MRCS0 MRCS1 MRCS2 MRCS3 Channel number Bit number in register Channel number Bit number in register Channel number Bit number in register Channel number Bit number in register For ...

Page 790: ...ansmit from the multiple word block of data For example setting bit 0 selects word 0 setting bit 12 selects word 12 and so on Setting a particular bit in a SPORTx_MTCSn register causes the SPORT to transmit the word in that channel s position of the datastream When the secondary transmit side is enabled by the TXSE bit both sides transmit a Table 12 6 SPORTx Multichannel Receive Select Register Me...

Page 791: ... that word from multiple word block of data 31 31 0 0 31 63 0 32 31 95 0 64 31 127 0 96 Reset 0x0000 0000 Reset 0x0000 0000 Reset 0x0000 0000 Reset 0x0000 0000 MTCS0 MTCS1 MTCS2 MTCS3 Channel number Bit number in register Channel number Bit number in register Channel number Bit number in register Channel number Bit number in register For Memory mapped addresses see Table 12 7 0 0 0 0 0 0 0 0 0 0 0...

Page 792: ...or the content of the SPORT s configuration registers SPORTx_RCRx and SPORTx_TCRx and the DMA configuration An example value is given in the comments but for the meaning of the individual bits the user is referred to the detailed explanation in this chapter The example configures both the receive and the transmit section Since they are completely independent the code uses separate labels Table 12 ...

Page 793: ...IG Divider SCLK TCLK value 0 to 65535 W P0 SPORT0_TCLKDIV SPORT0_TCR1 R1 TCK divider register number of Bitclocks between FrameSyncs 1 value SPORT_SLEN to 65535 R1 SPORT_TFSDIV_CONFIG W P0 SPORT0_TFSDIV SPORT0_TCR1 R1 TFSDIV regis ter Transmit configuration Configuration register 2 for instance 0x000E for 16 bit wordlength R1 SPORT_TRANSMIT_CONF_2 W P0 SPORT0_TCR2 SPORT0_TCR1 R1 Configuration regi...

Page 794: ...RCR1 R1 RCK divider register number of Bitclock between FrameSyncs 1 value SPORT_SLEN to 65535 R1 SPORT_RFSDIV_CONFIG W P0 SPORT0_RFSDIV SPORT0_RCR1 R1 RFSDIV regis ter Receive configuration Configuration register 2 for instance 0x000E for 16 bit wordlength R1 SPORT_RECEIVE_CONF_2 W P0 SPORT0_RCR2 SPORT0_RCR1 R1 Configuration register 1 for instance 0x4410 for exter nal clk and framesync R1 SPORT_...

Page 795: ... the SPORT is not enabled yet However if preferred the user can enable the DMA later immediately before enabling the SPORT The only requirement is that the DMA channel be enabled before the associ ated peripheral is enabled to start the transfer Listing 12 2 DMA Initialization Program_DMA_Controller Receiver DMA channel 3 Set P0 to DMA Base Address P0 l lo DMA3_CONFIG P0 h hi DMA3_CONFIG Configura...

Page 796: ...abled yet Transmitter DMA channel 4 Set P0 to DMA Base Address P0 l lo DMA4_CONFIG P0 h hi DMA4_CONFIG Configuration for instance 0x1088 for Autobuffer 32 bit wide transfers R0 DMA_TRANSMIT_CONF z W P0 R0 configuration register tx_buf Buffer in Data memory divide count by four because of 32 bit DMA transfers R1 length tx_buf 4 z W P0 DMA4_X_COUNT DMA4_CONFIG R1 X_count register R1 4 z 4 bytes in a...

Page 797: ...generate an inter rupt request if so programmed The following code fragments show the minimum actions that must be taken Not shown is the programming of the core and system event controllers Listing 12 3 Servicing an Interrupt RECEIVE_ISR SP RETI nesting of interrupts clear DMA interrupt request P0 h hi DMA3_IRQ_STATUS P0 l lo DMA3_IRQ_STATUS R1 1 W P0 R1 l write one to clear RETI SP rti TRANSMIT_...

Page 798: ...eiver and transmitter are enabled The core may just wait for interrupts Listing 12 4 Starting a Transfer Enable Sport0 RX and TX P0 h hi SPORT0_RCR1 P0 l lo SPORT0_RCR1 R1 W P0 Z BITSET R1 0 W P0 R1 ssync Enable Receiver set bit 0 P0 h hi SPORT0_TCR1 P0 l lo SPORT0_TCR1 R1 W P0 Z BITSET R1 0 W P0 R1 ssync Enable Transmitter set bit 0 dummy wait loop do nothing but waiting for interrupts wait_forev...

Page 799: ...ical UART modules The UART modules are full duplex peripherals compatible with PC style industry standard UARTs sometimes called Serial Controller Interfaces SCI The UARTs convert data between serial and parallel formats The serial communication follows an asynchronous protocol that supports var ious word length stop bits bit rate and parity generation options Features Each UART includes these fea...

Page 800: ...RX and a TX pin available through port F These two pins usually connect to an external transceiver device that meets the electrical requirements of full duplex for example EIA 232 EIA 422 4 wire EIA 485 or half duplex for example 2 wire EIA 485 LIN stan dards While the UART0 signals are multiplexed with DMA request inputs the UART1 signals compete with timer 6 and timer 7 To connect UART signals t...

Page 801: ...data flow using either interrupts or polling The DMA method requires minimal software intervention as the DMA engine itself moves the data Each UART has its own separate transmit and receive DMA channels For more information on DMA see Chapter 5 Direct Memory Access Figure 13 1 UART Block Diagram UARTx_IER UARTx_RBR UARTx_THR UARTx_LSR UARTx_LCR UARTx_IIR UARTx_MCR SIC CONTROLLER UARTx_DLL UARTx_D...

Page 802: ...ronous serial protocol consisting of individual data words A word has 5 to 8 data bits All data words require a start bit and at least one stop bit With the optional parity bit this creates a 7 to 12 bit range for each word The for mat of received and transmitted character frames is controlled by the line control register UARTx_LCR Data is always transmitted and received least significant bit LSB ...

Page 803: ... frame format are identical for both transfer directions Transmission is initiated by writes to the UARTx_THR register If no former operation is pending the data is immediately passed from the UARTx_THR register to the internal TSR register where it is shifted out at a bit rate equal to SCLK 16 Divisor with start stop and parity bits appended as defined the UARTx_LCR register The least significant...

Page 804: ...time it is safe to disable the UCEN bit or to three state off chip line drivers UART Receive Operation The receive operation uses the same data format as the transmit configura tion except that one valid stop bit is always sufficient that is the STB bit has no impact to the receiver After detection of the start bit the received word is shifted into the inter nal shift register RSR at a bit rate of...

Page 805: ... in the UARTx_IER register The following error situations are detected Every error has an indicating bit in the UARTx_LSR register Overrun error OE bit Parity error PE bit Framing error Invalid stop bit FE bit Break indicator BI bit Reception is started when a falling edge is detected on the RX input pin The receiver attempts to see a start bit For better immunity against noise and hazards on the ...

Page 806: ...six UART clock periods Similarly the trailing edge of the pulse is truncated by eight UART clock periods This results in the final representation of the original 0 as a high pulse of only 3 16 clock periods in a 16 cycle UART clock period The pulse is centered around the middle of the bit time as shown in Figure 13 3 The final IrDA pulse is fed to the off chip infrared driver This modulation appro...

Page 807: ...opriate shielding The only other source of a glitch is the transmitter itself The processor relies on the transmitter to perform within specification If the transmitter violates the specification unpre dictable results may occur The 4 bit counter adds an extra level of protection at a minimal cost Note because the system clock can change across systems the longest glitch tolerated is inversely pro...

Page 808: ...goes directly to the SIC controller after being ORed with interrupt signals from other modules If the associated DMA channel is enabled the request functions as a DMA request If the DMA channel is disabled it simply forwards the request to the SIC interrupt controller Note that a DMA channel must be associated with the UART module to enable TX and RX interrupts Otherwise the Figure 13 4 IrDA Recei...

Page 809: ...mission has completed For more information see DMA Mode on page 13 17 The THRE bit is cleared by hardware when new data is written to the UARTx_THR register These writes also clear the TX interrupt request How ever they also initiate further transmission If software doesn t want to continue transmission the TX request can alternatively be cleared by either clearing the ETBEI bit or by reading the ...

Page 810: ... a deadlock condition can occur To avoid this always assign the lowest prior ity of the enabled UART interrupts to the UARTx_THR empty event Bit Rate Generation The UART clock is enabled by the UCEN bit in the UARTx_GCTL register The bit rate is characterized by the system clock SCLK and the 16 bit divisor The divisor is split into the UARTx_DLL and the UARTx_DLH regis ters These registers form a ...

Page 811: ...Chapter 15 General Purpose Timers The capture capabilities of the timers are often used to supervise the bit rate at runtime If the Blackfin UART was talking to any device supplied by a weak clock oscillator that drifts over time the Blackfin can re adjust its UART bit rate dynamically as required Often autobaud detection is used for initial bit rate negotiations There the Blackfin processor is mo...

Page 812: ... resolu tion of the captured signal it is recommended not to measure just the pulse width of a single bit but to enlarge the pulse of interest over more bits Traditionally a NULL character ASCII 0x00 was used in autobaud detection as shown in Figure 13 5 Because the example frame in Figure 13 5 encloses 8 data bits and 1 start bit apply the formula DIVISOR TIMERx_WIDTH 16 x 9 Real UART RX signals ...

Page 813: ..._PERIOD 7 An example is provided in Listing 13 2 on page 13 33 Programming Model The following sections describe a programming model for the UARTs Non DMA Mode In non DMA mode data is moved to and from the UART by the proces sor core To transmit a character load it into UARTx_THR Received data can be read from UARTx_RBR The processor must write and read one char acter at time To prevent any loss o...

Page 814: ... careful if transmit and receive are served by different software threads because read operations on UART_LSR and UART_IIR registers are destruc tive Polling the SIC_ISR register without enabling the interrupts by SIC_MASK is an alternate method of operation to consider Software can write up to two words into the UARTx_THR register before enabling the UART clock As soon as the UCEN bit is set thos...

Page 815: ...ters to clear the latched request of the pending interrupt The UART s DMA is enabled by first setting up the system DMA control registers and then enabling the UART ERBFI and or ETBEI interrupts in the UARTx_IER register This is because the interrupt request lines double as DMA request lines Depending on whether DMA is enabled or not upon receiving these requests the DMA control unit either genera...

Page 816: ...er ated Transmission may abort in the middle of the stream causing data loss if the UART clock was disabled without additional poll ing of the TEMT bit The UART s DMA supports 8 bit and 16 bit operation but not 32 bit operation Sign extension is not supported Mixing Modes Especially on the transmit side switching from DMA mode to non DMA operation on the fly requires some thought By default the in...

Page 817: ...isters for each UART These Memory mapped Registers MMRs are byte wide registers that are mapped as half words with the most significant byte zero filled Table 13 2 provides an overview of the UART registers Consistent with industry standard devices multiple registers are mapped to the same address location The UARTx_DLH and UARTx_DLL registers share their addresses with the UARTx_THR registers the...

Page 818: ...r latch low byte UARTx_IER 0x0004 0 R W 0x00 Interrupt enable regis ter UARTx_DLH 0x0004 1 R W 0x00 Divisor latch high byte UARTx_IIR 0x0008 X R Read operations are destructive 0x01 Interrupt identifica tion register UARTx_LCR 0x000C X R W 0x00 Line control register UARTx_MCR 0x0010 X R W 0x00 Modem control regis ter UARTx_LSR 0x0014 X R Read operations are destructive 0x60 Line status register UA...

Page 819: ...n the receiver is always satisfied with one stop bit Figure 13 7 UART Line Control Registers DLAB Divisor Latch Access 1 Enables access to UARTx_DLL and UARTx_DLH 0 Enables access to UARTx_THR UARTx_RBR and UARTx_IER SB Set Break 0 No force 1 Force TX pin to 0 STP Stick Parity Forces parity to defined value if set and PEN 1 EPS 1 parity transmitted and checked as 0 EPS 0 parity transmitted and che...

Page 820: ...TP 0 the hardware cal culates the parity bit value based on the data bits Then the EPS bit determines whether odd or even parity mode is chosen If EPS 0 odd par ity is used That means that the total count of logical 1 data bits including the parity bit must be an odd value Even parity is chosen by STP 0 and EPS 1 Then the count of logical 1 bits must be a even value If the STP bit is set then hard...

Page 821: ...LAB 0 or the divisor latch regis ters DLH and DLL alternatively DLAB 1 UARTx_MCR Registers The UARTx_MCR registers control the UART port as shown in Figure 13 8 Even if modem functionality is not supported the UART modem control registers are available in order to support the loopback mode Loopback mode disconnects the receiver s input from the RX pin but redirects it to the transmit output intern...

Page 822: ...ata overwrites the content of the buffers To avoid overruns read the UARTx_RBR register in time The OE bit cleared when the LSR register is read Figure 13 9 UART Line Status Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 DR Data Ready TEMT TSR and UARTx_THR Empty UART Line Status Registers UARTx_LSR 0 Full 1 Both empty 0 THR not empty 1 THR empty 0 No break interru...

Page 823: ...low bits only It is cleared by hardware when the UARTx_RBR register is read L Because of the destructive nature of these read operations special care should be taken For more information see the Memory chap ter of the ADSP BF53x BF56x Blackfin Processor Programming Reference The THRE bit indicates that the UART transmit channel is ready for new data and software can write to UARTx_THR Writes to UA...

Page 824: ...the same address as the write only UARTx_THR and UARTx_DLL registers To access UARTx_RBR the DLAB bit in UARTx_LCR must be cleared When the DLAB bit is cleared writes to this address target the UARTx_THR register while reads from this address return the UARTx_RBR register Figure 13 10 UART Transmit Holding Registers Figure 13 11 UART Receive Buffer Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0...

Page 825: ...ng routines must be present For backward compatibility the UARTx_IIR still reflects the correct interrupt status L Each UART features three separate interrupt channels to handle data transmit data receive and line status events independently regardless whether DMA is enabled or not At system level the two UART status interrupt channels are ORed prior being connected to the SIC controller With syst...

Page 826: ...pletely The ELSI bit enables interrupt generation on an independent interrupt channel when any of the following conditions are raised by the respective bit in the UARTx_LSR register Receive overrun error OE Receive parity error PE Receive framing error FE Break interrupt BI Figure 13 12 UART Interrupt Enable Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERBFI Enab...

Page 827: ...al role of the UARTx_IIR register read in the case where the service routine does not want to transmit further data If software stops transmission it must read the UARTx_IIR register to reset the interrupt request As long as the UARTx_IIR register reads 0x04 or 0x06 indicating that another interrupt of higher priority is pending the UARTx_THR empty latch cannot be cleared by reading UARTx_IIR Figu...

Page 828: ...own in Figure 13 14 can be accessed L Note the 16 bit divisor formed by UARTx_DLH and UARTx_DLL resets to 0x0001 resulting in the highest possible clock frequency by default If the UART is not used disabling the UART clock saves power The UARTx_DLH and UARTx_DLL registers can be programmed by software before or after setting the UCEN bit Figure 13 14 UART Divisor Latch Registers Divisor Latch Low ...

Page 829: ... 7 0 UART Scratch Registers UARTx_SCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 UART0 0xFFC0 041C UART1 0xFFC0 201C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCEN Enable UART Clocks 1 Enable UART clocks 0 Disable UART clocks Reset 0x0000 IREN Enable IrDA Mode 1 Enable IrDA 0 Disable IrDA FPE Force Parity Error on Transmit 1 Force...

Page 830: ...ly in IrDA mode The two force error bits FPE and FFE are intended for test purposes They are useful for debugging software espe cially in loopback mode Programming Examples The subroutine in Listing 13 1 shows a typical UART initialization sequence Listing 13 1 UART Initialization Configures UART in 8 data bits no parity 1 stop bit mode Input parameters r0 holds divisor latch value to be written i...

Page 831: ... in Listing 13 2 performs autobaud detection similarly to UART boot Listing 13 2 UART Autobaud Detection Subroutine Assuming 8 data bits this functions expects a ASCII 0x40 character on the UARTx RX pin A Timer performs the autobaud detection Input parameters p0 contains the UARTx_GCTL register address p1 contains the TIMERx_CONFIG register address Return values r0 holds timer period value equals ...

Page 832: ...mer x p5 TIMER_STATUS TIMER_STATUS r6 clear pending latches period capture falling edge to falling edge r7 TIN_SEL IRQ_ENA PERIOD_CNT WDTH_CAP z w p1 TIMER0_CONFIG TIMER0_CONFIG r7 w p5 TIMER_ENABLE TIMER_STATUS r5 uart_autobaud wait wait for timer event r7 w p5 TIMER_STATUS TIMER_STATUS z r7 r7 r5 CC r7 0 if CC jump uart_autobaud wait w p5 TIMER_DISABLE TIMER_STATUS r5 disable Timer x p5 TIMER_ST...

Page 833: ...5 p5 TIMER_STATUS TIMER_STATUS r6 r7 5 p5 5 sp rts uart_autobaud end The parent routine in Listing 13 3 performs autobaud detection using UART0 and TIMER1 Listing 13 3 UART Autobaud Detection Parent Routine p0 l lo PORTF_FER function enable on UART0 pins PF0 and PF1 p0 h hi PORTF_FER by default PORT_MUX register is all set r0 PF1 PF0 z w p0 r0 p0 l lo UART0_GCTL select UART 0 p0 h hi UART0_GCTL p1...

Page 834: ...TL register address Return values none uart_putc sp r7 uart_putc wait r7 w p0 UART0_LSR UART0_GCTL z CC bittst r7 bitpos THRE if CC jump uart_putc wait w p0 UART0_THR UART0_GCTL r0 write initiates transfer r7 sp rts uart_putc end Use the routine shown in Listing 13 5 to transmit a C style string that is terminated by a null character Listing 13 5 UART String Transmission Transmit a null terminated...

Page 835: ...bits It is therefore not recommended to poll UART0_LSR for transmission this way while data is received In case write a polling loop that reads UARTx_LSR once and then evaluates all status bits of interest as shown in Listing 13 6 Listing 13 6 UART Polling Loop uart_loop r7 w p0 UART0_LSR UART0_GCTL z CC bittst r7 bitpos DR if CC jump uart_loop transmit r6 w p0 UART0_RBR UART0_GCTL z r5 BI OE FE P...

Page 836: ... request lines may or may not be ORed together in the SIC controller If they had three different service routines they may look as shown in Listing 13 7 Listing 13 7 UART Non DMA Interrupt Operation isr_uart_rx sp astat sp r7 r7 w p0 UART0_RBR UART0_GCTL z b p4 r7 ssync r7 sp astat sp rti isr_uart_rx end isr_uart_tx sp astat sp r7 r7 b p3 z CC r7 0 if CC jump isr_uart_tx final w p0 UART0_THR UART0...

Page 837: ...sp rti isr_uart_tx end isr_uart_error sp astat sp r7 r7 w p0 UART0_LSR UART0_GCTL z read clears inter rupt request do something with the error r7 sp astat sp ssync rti isr_uart_error end Listing 13 8 transmits a string by DMA operation waits until DMA com pletes and sends an additional string by polling Note the importance of the SYNC bit Listing 13 8 UART Transmission SYNC Bit Use section data by...

Page 838: ... interrupt in SIC r0 l 0x1000 r0 h 0x0000 p1 r0 sp reti enable nesting of interrupts p5 l lo DMA9_CONFIG setup DMA in STOP mode p5 h hi DMA9_CONFIG r7 l lo sHello r7 h hi sHello p5 DMA9_START_ADDR DMA9_CONFIG r7 r7 length sHello z r7 1 don t send trailing null character w p5 DMA9_X_COUNT DMA9_CONFIG r7 r7 1 w p5 DMA9_X_MODIFY DMA9_CONFIG r7 r7 FLOW_STOP WDSIZE_8 DI_EN SYNC DMAEN z w p5 r7 p0 l lo ...

Page 839: ... DMA9_IRQ_STATUS DMA9_CONFIG z CC bittst r0 bitpos DMA_RUN if CC jump wait4dma p1 l lo sWorld p1 h hi sWorld call uart_puts forever jump forever isr_uart_tx sp astat sp r7 r7 DMA_DONE z W1C interrupt request w p5 DMA9_IRQ_STATUS DMA9_CONFIG r7 r7 0 pulse ETBEI for general case w p0 UART0_IER UART0_GCTL r7 ssync r7 sp astat sp rti isr_uart_tx end ...

Page 840: ...Programming Examples 13 42 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 841: ... scheme provides great flexibility to the external application space Table 14 1shows all the peripheral signals that can be accessed off chip In total there are signal count of 124 signals on the ADSP BF534 or 142 sig nals on the ADSP BF536 and ADSP BF537 The ADSP BF534 ADSP BF536 and ADSP BF537 processors feature 60 pins for peripheral purposes from which the rich peripheral set signals are multi...

Page 842: ...mary timer signals Primary SPI signals Handshake memDMA request signals GPIOs Port G provides 16 pins SPORT1 signals PPI data signals GPIOs SPORTs Data 8 clock 4 frame sync 4 UARTs Data 4 Timers PWM capture clock 8 alternate clock input 8 alternate cap ture input 3 General Purpose I O GPIO 48 Handshake MemDMA MemDMA request 2 1 ADSP BF536 and ADSP BF537 only Table 14 1 General Purpose and Special ...

Page 843: ...II RMII pins ADSP BF536 and ADSP BF537 only on the ADSP BF534 PJ0 should be left No Connect and PJ1 should be Connect to Ground Interface Overview By default all pins of port F port G and port H are in general purpose I O GPIO mode Port J does not provide GPIO functionality In this mode a pin can function as either digital input digital output or inter rupt input See General Purpose I O Modules on...

Page 844: ...t F Port F is controlled by the PORT_MUX and the PORTF_FER registers Port F provides both UART ports If only one UART is required in the target application the user has the option to enable either the handshake memDMA request pins see Handshaked Memory DMA Operation on page 5 40 or two additional timers Other timers are competing with additional SPI slave select signals and with the rarely used PP...

Page 845: ...ion mode The high current option does not need to be enabled It is always on Refer to the part specific data sheet for further details Port G Structure Figure 14 2 shows the multiplexer scheme for port G It is controlled by the PORT_MUX and the PORTG_FER registers Figure 14 1 Port F Multiplexing Scheme PFDE PPI CLK TMRCLK SPI SS PF0 PORT F GPIO PF0 DMAR0 SPI MOSI TMR2 PPI FS1 TMR0 SPI SSEL1 UART0 ...

Page 846: ...ction Port H Structure Figure 14 3 shows the multiplexer scheme for port H It is controlled by the PORT_MUX and the PORTH_FER registers On the ADSP BF534 processor port H functions as a GPIO port only Figure 14 2 Port G Multiplexing Scheme PPI D15 PPI D14 PG0 PORT G GPIO PG0 PPI D11 PPI D7 PPI D9 PPI D10 PPI D0 PPI D13 PPI D12 DT1PRI GPIO PG1 GPIO PG2 GPIO PG3 GPIO PG4 GPIO PG5 GPIO PG6 GPIO PG7 G...

Page 847: ...4 4 shows the multiplexer scheme for port J It is controlled by the PORT_MUX register Figure 14 3 Port H Multiplexing Scheme PH0 ADSP BF534 PORT H GPIO PH0 GPIO PH1 GPIO PH2 GPIO PH3 GPIO PH4 GPIO PH5 GPIO PH6 GPIO PH7 GPIO PH8 GPIO PH9 GPIO PH10 GPIO PH11 GPIO PH12 GPIO PH13 GPIO PH14 GPIO PH15 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 TACLK6 TACLK5 TACLK7 MII CRS MII RXER...

Page 848: ...ins and the TWI pins are not multi plexed at all When the CAN interface is selected by the PJCE bit field and in the PORT_MUX register timer 0 can capture the CAN RX pin through its TACI0 input for autobaud detection Internal Interfaces Port control and GPIO registers are part of the system memory mapped registers MMRs The addresses of the GPIO module MMRs appear in Appendix B Core access to the G...

Page 849: ...g detect able by the processor When configured for level sensitive interrupt generation there is a minimum latency of 4 SCLK cycles between the time the signal is asserted on the pin and the time that program flow is inter rupted When configured for edge sensitive interrupt generation an additional SCLK cycle of latency is introduced giving a total latency of 5 SCLK cycles between the time the edg...

Page 850: ...e state of the pin When using a particular peripheral interface pins required for the peripheral must be individually enabled Keep the related function enable bit cleared if a signal provided by the peripheral is not required by your application This allows it to be used in GPIO mode General Purpose I O Modules The processor supports 48 bidirectional or general purpose I O GPIO signals These 48 GP...

Page 851: ... used as an input Leaving the input buffer disabled eliminates the need for pull ups and pull downs when a particular PFx PGx or PHx pin is not used in the system By default the input buffers are disabled a Once the input driver of a GPIO pin is enabled the GPIO is not allowed to operate as an output anymore Never enable the input driver by setting PORTxIO_INEN bits and the output driver by set ti...

Page 852: ...ORTxIO_CLEAR or to the GPIO toggle registers PORTxIO_TOGGLE instead While a direct write to a GPIO data register alters all bits in the register writes to a GPIO set register can be used to set a single or a few bits only No read modify write operations are required The GPIO set registers are write 1 to set registers All 1s contained in the value written to a GPIO set register sets the respective ...

Page 853: ...n the PF4 and PF5 pins without affecting the state of any other PFx pins L If an edge sensitive pin generates an interrupt request the service routine must acknowledge the request by clearing the respective GPIO latch This is usually performed through the clear registers Read operations from the GPIO clear registers return the content of the GPIO data registers The GPIO toggle registers provide an...

Page 854: ...register must be set The function enable bit in the PORTx_FER register is typically cleared Then an interrupt request can be generated according to the state of the pin either high or low an edge transition low to high or high to low or on both edge transitions low to high and high to low Input sensitivity is defined on a per bit basis by the GPIO polarity registers PORTFIO_POLAR PORTGIO_POLAR and...

Page 855: ... interrupt being generated on both the rising and falling edges This register has no effect on GPIOs that are defined as level sensitive or as outputs See Table 14 2 on page 14 12 for information on how the GPIO set on both edges register interacts with the GPIO polarity and GPIO interrupt sensitivity registers When the GPIO s input drivers are enabled while the GPIO direction reg isters configure...

Page 856: ...pts the interrupt condition must be cleared each time a corresponding interrupt is serviced by writing 1 to the appropriate bit in the GPIO clear register At reset all interrupts are masked and disabled Similarly to the GPIOs themselves the mask register can either be written through the GPIO mask data registers PORTxIO_MASKA PORTxIO_MASKB or be controlled by the mask A mask B set clear and toggle...

Page 857: ...14 5 GPIO Interrupt Generation Flow for Interrupt Channel A NO INPUT YES YES YES YES GENERATE INTERRUPT A START IS THE GPIO SET AS AN OUTPUT IN PORTxIO_DIR IS THE GPIO EDGE SENSITIVE AS DEFINED IN PORTxIO_EDGE IS THE INPUT AN ACTIVE LEVEL AS DEFINED IN PORTxIO_POLAR IS THE GPIO SET TO ONE YES IS EDGE DETECTED AS DEFINED IN PORTxIO_POLAR PORTxIO_BOTH IS THE INPUT DRIVER ENABLED IN PORTxIO_INEN IS T...

Page 858: ...upt registers While a direct write to a mask interrupt register alters all bits in the register writes to a mask interrupt toggle reg ister can be used to toggle a single bit or a few bits only No read modify write operations are required The mask interrupt toggle registers are write 1 to clear registers All ones contained in the value written to the mask interrupt toggle register toggle the respe...

Page 859: ...e total number of GPIO interrupt channels is five therefore Figure 14 6 GPIO Interrupt Channels PF0 PORTFIO_MASKA_D PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PORTFIO_MASKB_D PG0 PORTGIO_MASKA_D PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PORTGIO_MASKB_D PH0 PORTHIO_MASKA_D PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PORTHIO_MASKB_...

Page 860: ...R PERIPHERAL WRITE PORTx_FER TO CLEAR APPROPRIATE PFx PGx AND PHx BITS SEE PERIPHERAL FOR MORE DETAILS OUTPUT INPUT GPIO OUTPUT OR INPUT WRITE PORTxIO_DIR TO CLEAR APPROPRIATE BITS FOR INPUT DIRECTION WRITE PORTxIO_INEN TO SET APPROPRIATE BITS TO ENABLE INPUT DRIVERS DIRECTION A WRITE PORTxIO_DIR TO SET APPROPRIATE BITS FOR OUTPUT DIRECTION SET CLEAR SET OR CLEAR GPIO WRITE PORTxIO_CLEAR TO SET AP...

Page 861: ...ROGATE PORTx_DATA BITS TO DETERMINE EVENTS RISING OR FALLING BOTH EDGE RISING FALLING OR BOTH WRITE PORTxIO_BOTH TO SET APPROPRIATE BITS FOR BOTH EDGE SENSITIVITY WRITE PORTxIO_BOTH TO CLEAR APPROPRIATE BITS FOR EDGE SENSITIVITY RISING FALLING EDGE RISING OR FALLING WRITE PORTxIO_POLAR TO SET APPROPRIATE BITS FOR FALLING EDGE SENSITIVITY WRITE PORTxIO_POLAR TO CLEAR APPROPRIATE BITS FOR RISING EDG...

Page 862: ... Enable PFDE Port F DMA Request Enable PFTE Port F Timer Enable PJSE Port J SPI Enable PGSE Port G SPORT Sec ondary Enable PGRE Port G SPORT Receive Enable PGTE Port G SPORT Transmit Enable 00 Enable DR0SEC DT0SEC 01 Enable CAN RX CAN TX 10 Enable SPI SSEL 7 11 Reserved Reset 0x0000 0 Enable TMR5 1 Enable SPI SSEL 6 0 Enable PPI D13 PPI D14 PPI D15 1 Enable TSCLK1 TFS1 DT1PRI 0 Enable PPI D8 PPI D...

Page 863: ...eral function Px6 Px7 Px11 Px10 Px9 Px8 Reset 0x0000 Port F 0xFFC0 3200 Port G 0xFFC0 3204 Port H 0xFFC0 3208 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Direction Registers PORTxIO_DIR Px0 Direction Px12 Direction Px13 Direction Px14 Direction Px15 Direction Px1 Direction Px2 Direction Px3 Direction Px4 Direction Px5 Direction For all bits 0 Input 1 Output Px6 Direc...

Page 864: ...x5 Input Enable For all bits 0 Input Buffer Disabled 1 Input Buffer Enabled Px6 Input Enable Px7 Input Enable Px11 Input Enable Px10 Input Enable Px9 Input Enable Px8 Input Enable Reset 0x0000 Port F 0xFFC0 0740 Port G 0xFFC0 1540 Port H 0xFFC0 1740 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Data Registers PORTxIO Program Px0 Program Px12 Program Px13 Program Px14 P...

Page 865: ...x3 Set Px4 Set Px5 Write 1 to set Set Px6 Set Px7 Set Px11 Set Px10 Set Px9 Set Px8 Reset 0x0000 Port F 0xFFC0 0708 Port G 0xFFC0 1508 Port H 0xFFC0 1708 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Clear Registers PORTxIO_CLEAR Clear Px0 Clear Px12 Clear Px13 Clear Px14 Clear Px15 Clear Px1 Clear Px2 Clear Px3 Clear Px4 Clear Px5 Write 1 to clear Clear Px6 Clear Px7 ...

Page 866: ...ggle Px6 Toggle Px7 Toggle Px11 Toggle Px10 Toggle Px9 Toggle Px8 Reset 0x0000 Port F 0xFFC0 070C Port G 0xFFC0 150C Port H 0xFFC0 170C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Polarity Registers PORTxIO_POLAR Px0 Polarity Px12 Polarity Px13 Polarity Px14 Polarity Px15 Polarity Px1 Polarity Px2 Polarity Px3 Polarity Px4 Polarity Px5 Polarity For all bits 0 Active ...

Page 867: ...e Px6 Sensitivity Px7 Sensitivity Px11 Sensitivity Px10 Sensitivity Px9 Sensitivity Px8 Sensitivity Reset 0x0000 Port F 0xFFC0 0738 Port G 0xFFC0 1538 Port H 0xFFC0 1738 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Set on Both Edges Registers PORTxIO_BOTH Px0 Both Edges Px12 Both Edges Px13 Both Edges Px14 Both Edges Px15 Both Edges Px1 Both Edges Px2 Both Edges Px3 B...

Page 868: ...upt A Enable Px7 Interrupt A Enable Px11 Interrupt A Enable Px10 Interrupt A Enable Px9 Interrupt A Enable Px8 Interrupt A Reset 0x0000 Port F 0xFFC0 0710 Port G 0xFFC0 1510 Port H 0xFFC0 1710 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO Mask Interrupt B Registers PORTxIO_MASKB Enable Px0 Interrupt B Enable Px12 Interrupt B Enable Px13 Interrupt B Enable Px14 Interrup...

Page 869: ...nterrupt A Enable Set Px13 Interrupt A Enable Set Px14 Interrupt A Enable Set Px15 Interrupt A Enable Set Px1 Interrupt A Enable Set Px2 Interrupt A Enable Set Px3 Interrupt A Enable Set Px4 Interrupt A Enable Set Px5 Interrupt A Enable For all bits 1 Set Set Px6 Interrupt A Enable Set Px7 Interrupt A Enable Set Px11 Interrupt A Enable Set Px10 Interrupt A Enable Set Px9 Interrupt A Enable Set Px8...

Page 870: ...rt F 0xFFC0 0728 Port G 0xFFC0 1528 Port H 0xFFC0 1728 Set Px0 Interrupt B Enable Set Px1 Interrupt B Enable Set Px2 Interrupt B Enable Set Px3 Interrupt B Enable Set Px4 Interrupt B Enable Set Px5 Interrupt B Enable Set Px6 Interrupt B Enable Set Px7 Interrupt B Enable Set Px9 Interrupt B Enable Set Px8 Interrupt B Enable Set Px12 Interrupt B Enable Set Px13 Interrupt B Enable Set Px14 Interrupt ...

Page 871: ... Enable Clear Px13 Interrupt A Enable Clear Px14 Interrupt A Enable Clear Px15 Interrupt A Enable Clear Px1 Interrupt A Enable Clear Px2 Interrupt A Enable Clear Px3 Interrupt A Enable Clear Px4 Interrupt A Enable Clear Px5 Interrupt A Enable For all bits 1 Clear Clear Px6 Interrupt A Enable Clear Px7 Interrupt A Enable Clear Px11 Interrupt A Enable Clear Px10 Interrupt A Enable Clear Px9 Interrup...

Page 872: ...0724 Port G 0xFFC0 1524 Port H 0xFFC0 1724 Clear Px0 Interrupt B Enable Clear Px1 Interrupt B Enable Clear Px2 Interrupt B Enable Clear Px3 Interrupt B Enable Clear Px4 Interrupt B Enable Clear Px5 Interrupt B Enable Clear Px6 Interrupt B Enable Clear Px7 Interrupt B Enable Clear Px9 Interrupt B Enable Clear Px8 Interrupt B Enable Clear Px12 Interrupt B Enable Clear Px13 Interrupt B Enable Clear P...

Page 873: ...le Toggle Px13 Interrupt A Enable Toggle Px14 Interrupt A Enable Toggle Px15 Interrupt A Enable Toggle Px1 Interrupt A Enable Toggle Px2 Interrupt A Enable Toggle Px3 Interrupt A Enable Toggle Px4 Interrupt A Enable Toggle Px5 Interrupt A Enable For all bits 1 Toggle Toggle Px6 Interrupt A Enable Toggle Px7 Interrupt A Enable Toggle Px11 Interrupt A Enable Toggle Px10 Interrupt A Enable Toggle Px9...

Page 874: ... Mask Interrupt B Toggle Registers PORTxIO_MASKB_TOGGLE For all bits 1 Toggle Reset 0x0000 Port F 0xFFC0 072C Port G 0xFFC0 152C Port H 0xFFC0 172C Toggle Px0 Interrupt B Enable Toggle Px1 Interrupt B Enable Toggle Px2 Interrupt B Enable Toggle Px3 Interrupt B Enable Toggle Px4 Interrupt B Enable Toggle Px5 Interrupt B Enable Toggle Px6 Interrupt B Enable Toggle Px7 Interrupt B Enable Toggle Px9 I...

Page 875: ...0 h hi PORTFIO_DIR r0 h 0x0000 r0 l 0x0FC0 w p0 r0 ssync set port f clear register p0 l lo PORTFIO_CLEAR p0 h hi PORTFIO_CLEAR r0 l 0xFC0 w p0 r0 ssync set port f input enable register to enable input drivers of some GPIOs p0 l lo PORTFIO_INEN p0 h hi PORTFIO_INEN r0 h 0x0000 r0 l 0x003C w p0 r0 ssync set port f polarity register p0 l lo PORTFIO_POLAR p0 h hi PORTFIO_POLAR r0 0x00000 w p0 r0 ssync...

Page 876: ...Programming Examples 14 36 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 877: ...er module that contains eight identical 32 bit timers Every timer can operate in various operating modes on individual configuration Although the timers operate com pletely independent from each other all of them can be started and stopped simultaneously for synchronous operation Features The general purpose timers support the following operating modes Single shot mode for interval timing and sing...

Page 878: ...etection for CAN and both UART modules Graceful bit pattern termination when stopping Support for center aligned PWM patterns Error detection on implausible pattern values All read and write accesses to 32 bit registers are atomic Every timer has its dedicated interrupt request output Unused timers can function as edge sensitive pin interrupts Interface Overview Figure 15 1 shows the derivative sp...

Page 879: ...ly The other timers have identical structure Figure 15 1 Timer Block Diagram TIMER 7 SIC CONTROLLER PAB TIMER 6 TIMER 5 TIMER 4 TIMER 3 TIMER 2 TIMER 1 TIMER 0 TIMER_DISABLE TIMER_ENABLE TIMER_STATUS PORT CONTROL IRQ 26 IRQ 25 IRQ 24 IRQ 23 IRQ 22 IRQ 21 IRQ 20 IRQ 19 PF2 UART1 RX PF3 PF4 PF5 PF6 PF7 UART 0 RX PF1 PF8 PH14 PH12 PJ8 PJ7 PJ6 PF9 CAN RX PJ4 PH13 PJ9 PF14 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2...

Page 880: ...e The timer outputs TMR2 to TMR7 connect to pin drivers that can source and sink higher current than others See the product data sheet for details Figure 15 2 Internal Timer Structure TIMER0_CONFIG PERIOD MATCH SCLK ENABLE LATCH 32 TMRCLK TACLK0 TMR0 TIMER0_PERIOD WRITE TIMER0_PERIOD READ COMPARATOR TIMER0_COUNTER COMPARATOR TIMER0_WIDTH READ TIMER0_WIDTH WRITE 32 32 32 32 32 INTERRUPT CONTROL PIN...

Page 881: ... PPI module for frame sync generation In order to enable TMRCLK PORTF_FER bit 15 must be set and input enable for GPIO bit 15 needs to be set in the PORTxIO_INEN register The timer signals TMR0 TMR1 and TMR2 are multiplexed with the PPI frame syncs when the frame syncs are applied externally PPI modes requiring only two frame syncs free up TMR2 for any purpose Similarly PPI modes requiring only on...

Page 882: ...nding on operation mode the counter is reset to either 0x0000 0000 or 0x0000 0001 when the timer is enabled The counter always counts upward Usually it is clocked by SCLK In PWM mode it can be clocked by the alternate clock input TACLKx or the common timer clock input TMRCLK alternatively In counter mode the counter is clocked by edges on the TMRx input The sig nificant edge is programmable After ...

Page 883: ...o allow simultaneous or independent disabling of the eight timers Either the timer enable or the timer disable register can be read back to check the enable status of the timers A 1 indicates that the corresponding timer is enabled The timer starts counting three SCLK cycles after the TIMENx bit is set While the PWM mode is used to generate PWM patterns the capture mode WDTH_CAP is designed to rec...

Page 884: ... by error conditions as reported by the TOVF_ERRx bits The system interrupt controller enables flexible interrupt handling All timers may or may not share the same CEC interrupt channel so that a single interrupt routine services more than one timer In PWM mode multiple timers may run with the same period settings and issue their interrupt requests simultaneously In this case the service routine m...

Page 885: ...rrupt structure Figure 15 3 Timers Interrupt Structure ERROR EVENT IRQ_ENA TIMILx TIMER IRQx PROCESSOR CORE TMODE PWM_OUT WDTH_CAP EXT_CLK TOVF_ERRx RST RST SET SET INTERRUPT EVENT RESET TOVF_ERRx WRITE DATA TIMILx WRITE DATA MMR WRITE TO TIMER_STATUS COUNTER OVERFLOW ILLEGAL TIMERX_PERIOD ILLEGAL TIMERX_WIDTH 1 0 1 0 PERIOD_CNT LEADING EDGE TRAILING EDGE COUNT WIDTH COUNT PERIOD TMODE PWM_OUT WDT...

Page 886: ... the value 1 Overflow The timer counter was incremented instead of doing a rollover when it was holding the maximum possible count value of 0xFFFF FFFF The counter does not have a large enough range to express the next greater value and so erroneously loads a new value of 0x0000 0000 Unchanged No new error When ERR_TYP is unchanged it displays the previously reported error code or 00 if there has ...

Page 887: ...e timer Illegal cases may cause unwanted behavior of the TMRx pin Table 15 1 Overview of Illegal States Mode Event TIMERx_ PERIOD TIMERx_ WIDTH ERR_TYP TOVF_ERR PWM_OUT PERIOD_ CNT 1 Startup No boundary condition tests performed on TIMERx_ WIDTH 0 Anything b 10 Set 1 Anything b 10 Set 2 Anything Unchanged Unchanged Rollover 0 Anything b 10 Set 1 Anything b 11 Set 2 0 b 11 Set 2 TIMERx_ PERIOD Unch...

Page 888: ...TIMERx_ WIDTH 0 Anything Anything b 01 Set WDTH_CAP Startup TIMERx_PERIOD and TIMERx_WIDTH are read only in this mode no error possible Rollover TIMERx_PERIOD and TIMERx_WIDTH are read only in this mode no error possible Overflow Anything Anything b 01 Set EXT_CLK Startup 0 Anything b 10 Set 1 Anything Unchanged Unchanged Rollover 0 Anything b 10 Set 1 Anything Unchanged Unchanged Overflow not pos...

Page 889: ...tionality They may be set individually or in any combination although some combina tions are not useful such as TOGGLE_HI 1 with OUT_DIS 1 or PERIOD_CNT 0 Once a timer has been enabled the timer counter register is loaded with a starting value If CLK_SEL 0 the timer counter starts at 0x1 If CLK_SEL 1 it is reset to 0x0 as in EXT_CLK mode The timer counts upward to the value of the timer period reg...

Page 890: ...D_CNT 1 counts to the end of the period L The TIMERx_PERIOD and TIMERx_WIDTH registers are read only in some operation modes Be sure to set the TMODE field in the TIMERx_CONFIG register to b 01 before writing to these registers Figure 15 4 Timer Flow Diagram PWM_OUT Mode TIN_SEL DATA BUS 0 1 PWM_CLK SCLK CLK_SEL EQUAL TIMER_ENABLE EQUAL 1 1 0 0 YES CLOCK RESET ASSERT DEASSERT INTERRUPT PERIOD_CNT ...

Page 891: ...generates a single pulse on the TMRx pin This mode can also be used to implement a precise delay The pulse width is defined by the pulse width register and the period reg ister is not used See Figure 15 5 At the end of the pulse the timer interrupt latch bit TIMILx is set and the timer is stopped automatically No writes to the TIMERx_DISABLE register are required in this mode If the PULSE_HI bit i...

Page 892: ...mer pulse width TIMERx_WIDTH registers are programmed with the values required by the PWM signal When the timer is enabled in this mode the TMRx pin is pulled to a deas serted state each time the counter equals the value of the pulse width register and the pin is asserted again when the period expires or when the timer gets started To control the assertion sense of the TMRx pin the PULSE_HI bit in...

Page 893: ... the old values until the period expires The TOVF_ERRx status bit signifies an error condition in PWM_OUT mode The TOVF_ERRx bit is set if TIMERx_PERIOD 0 or TIMERx_PERIOD 1 at startup or when the timer counter register rolls over It is also set if the timer pulse width register is greater than or equal to the timer period reg ister by the time the counter rolls over The ERR_TYP bits are set when ...

Page 894: ...ggle Mode The waveform produced in PWM_OUT mode with PERIOD_CNT 1 normally has a fixed assertion time and a programmable deassertion time via the TIMERx_WIDTH register When two timers are running synchronously by the same period settings the pulses are aligned to the asserting edge as shown in Figure 15 7 The TOGGLE_HI mode enables control of the timing of both the asserting and deasserting edges ...

Page 895: ...periods When PULSE_HI is cleared an active high pulse is generated in the first third and all odd numbered periods and an active low pulse is generated in the second fourth and all even numbered periods The deasserted state at the end of one period matches the asserted state at the beginning of the next period so the output waveform only transitions when Count Pulse Width The net result is an outp...

Page 896: ...IOD 1 TIMER PERIOD 2 TIMER PERIOD 3 TIMER PERIOD 4 WAVEFORM PERIOD 1 WAVEFORM PERIOD 2 TIMER ENABLE ACTIVE LOW ACTIVE HIGH ACTIVE HIGH ACTIVE HIGH ACTIVE HIGH ACTIVE HIGH ACTIVE HIGH ACTIVE LOW ACTIVE LOW ACTIVE LOW ACTIVE LOW ACTIVE LOW TOGGLE_HI 1 PULSE_HI 1 TOGGLE_HI 1 PULSE_HI 1 TOGGLE_HI 1 PULSE_HI 1 TMR0 TMR1 WAVEFORM PERIOD 1 WAVEFORM PERIOD 2 TIMER ENABLE ACTIVE LOW ACTIVE HIGH ACTIVE HIGH...

Page 897: ...odd numbered periods write Period Width instead of Width to the timer pulse width register in order to obtain center aligned pulses For example if the pseudo code when TOGGLE_HI 0 is int period width for period generate_period width generate_width waitfor interrupt write TIMERx_PERIOD period write TIMERx_WIDTH width Then when TOGGLE_HI 1 the pseudo code would be int period width int per1 per2 wid1...

Page 898: ... before the timer is disabled As when TOGGLE_HI 0 errors are reported if the TIMERx_PERIOD register is either set to 0 or 1 or when the width value is greater than or equal to the period value Externally Clocked PWM_OUT By default the timer is clocked internally by SCLK Alternatively if the CLK_SEL bit in the Timer Configuration TIMERx_CONFIG register is set the timer is clocked by PWM_CLK The PWM...

Page 899: ... mum PWM_CLK clock high time is one SCLK period This implies the maximum PWM_CLK clock frequency is SCLK 2 The alternate timer clock inputs TACLKx are enabled when a timer is in PWM_OUT mode with CLK_SEL 1 and TIN_SEL 0 without regard to the content of the multiplexer control and function enable registers Using PWM_OUT Mode With the PPI Up to three timers are used to generate frame sync signals fo...

Page 900: ...uous PWM generation mode PWM_OUT PERIOD_CNT 1 software can stop the timer by writing to the TIMERx_DISABLE register To prevent the ongoing PWM pattern from being spoiled in unpredictable fashion the timer does not stop immediately when the corresponding 1 has been written to the TIMERx_DISABLE register Rather the write simply clears the enable latch and the timer still completes the ongoing PWM pa...

Page 901: ... used to regain immediate control of a timer during an error recovery sequence a Use this feature carefully because it may corrupt the PWM pattern generated at the TMRx pin When timers are disabled the timer counter registers retain their state when a timer is re enabled the timer counter is reinitialized based on the operating mode The timer counter registers are read only Software can not overwr...

Page 902: ...edge of a waveform the timer captures the cur rent 32 bit value of the TIMERx_COUNTER register into the width buffer register At the next leading edge the timer transfers the current 32 bit value of the TIMERx_COUNTER register into the period buffer register The count register is reset to 0x0000 0001 again and the timer continues counting and capturing until it is disabled In this mode software ca...

Page 903: ... the period buffer register 2 The TIMERx_WIDTH register is updated from the width buffer register 3 The TIMILx bit gets set if enabled but does not generate an error Figure 15 11 Timer Flow Diagram WDTH_CAP Mode SCLK TIMER_ENABLE RESET INTERRUPT PERIOD_CNT TMRx INTERRUPT LOGIC PULSE_HI TOVF_ERR TMRx PULSE_HI TRAILING EDGE DETECT DATA BUS LEADING EDGE DETECT TIMERx_COUNTER TIMERx_WIDTH TIMERx_PERIO...

Page 904: ...he width buffer register captures its value at a trailing edge If the PERIOD_CNT bit is set and a leading edge occurred see Figure 15 12 then the TIMERx_PERIOD and TIMERx_WIDTH registers report the pulse period and pulse width measured in the period that just ended If the PERIOD_CNT bit is cleared and a trailing edge occurred see Figure 15 13 then the TIMERx_WIDTH register reports the pulse width ...

Page 905: ...T 1 STARTS COUNTING NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN SCLK 1 3 1 2 3 4 6 7 8 TMRx PULSE_HI 0 TMRx PULSE_HI 1 2 4 5 1 X TIMERx_COUNTER 4 TIMERx_PERIOD BUFFER 2 3 TIMERx_WIDTH BUFFER 4 TIMERx_PERIOD 2 8 8 3 TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx X 0 X 0 X 0 X 0 MEASUREMENT REPORT MEASUREMENT REPORT ...

Page 906: ...ULSE_HI 0 TMRx PULSE_HI 1 2 3 5 6 8 3 4 3 4 7 1 2 1 X TIMERx_COUNTER 8 4 TIMERx_PERIOD BUFFER 3 TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx 2 1 2 0 4 3 8 1 2 X 0 X 0 X 0 X 0 STARTS COUNTING MEASUREMENT REPORT MEASUREMENT REPORT MEASUREMENT REPORT NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN ...

Page 907: ...measurement and logging errors generated by the timer count overflowing A timer interrupt if enabled is generated if the timer counter register wraps around from 0xFFFF FFFF to 0 in the absence of a leading edge At that point the TOVF_ERRx bit in the TIMER_STATUS register and the ERR_TYP bits in the TIMERx_CONFIG register are set indicating a count overflow due to a period greater than the counter...

Page 908: ...NTING SCLK 1 TMRx PULSE_HI 0 TMRx PULSE_HI 1 2 3 1 2 3 4 0 X TIMERx_COUNTER 4 TIMERx_PERIOD BUFFER 2 TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx 4 5 2 ERROR REPORT MEASUREMENT REPORT 0xFFFF FFFC 0xFFFF FFFD 0xFFFF FFFE 0xFFFF FFFF X 0 X 0 X 0 X 0 0 2 0 0 NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN ...

Page 909: ...15 15 Example Timing for Width Capture Followed by Period Overflow WDTH_CAP mode PERIOD_CNT 0 SCLK 1 TMRx PULSE_HI 0 TMRx PULSE_HI 1 2 1 2 3 4 0 X TIMERx_COUNTER 4 X TIMERx_PERIOD BUFFER 3 TIMERx_WIDTH BUFFER TIMERx_PERIOD TIMERx_WIDTH TIMILx TOVF_ERRx TIMENx 1 2 0 3 0 X 0 X 0 X 0 0 3 0 3 NOTE FOR SIMPLICITY THE SYNCHRONIZATION DELAY BETWEEN TMRx EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN STAR...

Page 910: ... the maximum TMRx input frequency is SCLK 2 with a 50 duty cycle Under these conditions the WDTH_CAP mode timer would measure Period 2 and Pulse Width 1 Autobaud Mode In WDTH_CAP mode some of the timers can provide autobaud detection for the Universal Asynchronous Receiver Transmitter UART and Control ler Area Network CAN interfaces The timer input select TIN_SEL bit in the TIMERx_CONFIG register ...

Page 911: ... applied to the TMRx pin is not required to have a 50 duty cycle but the minimum TMRx low time is one SCLK period and the mini mum TMRx high time is one SCLK period This implies the maximum TMRx input frequency is SCLK 2 Period may be programmed to any value from 1 to 232 1 inclusive After the timer has been enabled it resets the timer counter register to 0x0 and then waits for the first leading e...

Page 912: ... at startup or when the timer counter register rolls over from Count Period to Count 0x1 The timer pulse width register is unused Programming Model The architecture of the timer block enables any of the eight timers to work individually or synchronously along with others as a group of timers Regardless of the operation mode the timers programming model is always straightforward Because of the erro...

Page 913: ... started timers require minimal interaction with software which is usually performed by an interrupt service routine In PWM_OUT mode soft ware must update the pulse width and or settings as required In WDTH_CAP mode it must store captured values for further processing In any case the service routine should clear the TIMILx bits of the timers it controls Timer Registers The timer peripheral module ...

Page 914: ...t accesses are allowed for the timer enable timer disable and timer status registers On a 32 bit read of one of the 16 bit registers the upper word returns all 0s TIMER_ENABLE Register The TIMER_ENABLE register shown in Figure 15 17 allows all eight timers to be enabled simultaneously in order to make them run completely syn chronously For each timer there is a single W1S control bit Writing a 1 e...

Page 915: ...cates that the timer is enabled All unused bits return 0 when read Figure 15 17 Timer Enable Register 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 0 Timer Enable Register TIMER_ENABLE TIMEN0 Timer0 Enable TIMEN1 Timer1 Enable 1 Enable timer Read as 1 when enabled 1 Enable timer Read as 1 when enabled TIMEN2 Timer2 Enable 1 Enable timer Read as 1 when enabled 0xF...

Page 916: ...ck the status of eight timers with a single read The TIMER_STATUS reg ister shown in Figure 15 19 reports the status of timer 0 through timer 7 Status bits are sticky and W1C The TRUNx bits can clear themselves Figure 15 18 Timer Disable Register 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 0 Timer Disable Register TIMER_DISABLE TIMDIS0 Timer0 Disable TIMDIS1 Ti...

Page 917: ...ll reserved or unused bits return a 0 For detailed behavior and usage of the TRUNx bit see Stopping the Timer in PWM_OUT Mode on page 15 23 Writing the TRUNx bits has no effect in other modes or when a timer has not been enabled Writing the TRUNx bits to 1 in PWM_OUT mode has no effect on a timer that has not first been disabled Error conditions are explained in Illegal States on page 15 10 ...

Page 918: ...RQ_ENA is set Read as 1 if timer running W1C to abort in PWM_OUT mode TRUN7 Timer7 Slave Enable Status TOVF_ERR6 Timer6 Counter Overflow Indicates that an error or an overflow occurred All bits are W1C 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 TIMIL0 Timer0 Interrupt 0 Read as 1 if timer running W1C to abort in PWM_OUT mode Indicates an interrupt request when IRQ_ENA is set...

Page 919: ... The TIMERx_CONFIG registers may be read at any time The ERR_TYP field is read only It is cleared at reset and when the timer is enabled Each time TOVF_ERRx is set ERR_TYP 1 0 is loaded with a code that identifies the type of error that was detected This value is held until the next error or timer enable occurs For an overview of error conditions see Table 15 1 on page 15 11 The TIMERx_CONFIG regi...

Page 920: ...tes each period 00 No error 01 Counter overflow error 10 Period register programming error 11 Pulse width register programming error 00 Reset state unused 01 PWM_OUT mode 10 WDTH_CAP mode 11 EXT_CLK mode PULSE_HI CLK_SEL Timer Clock Select TOGGLE_HI PWM_OUT PULSE_HI Toggle Mode ERR_TYP 1 0 Error Type RO PERIOD_CNT Period Count 0 Interrupt request disable 1 Interrupt request enable 0 Count to end o...

Page 921: ...xecution stops By default the TIMERx_COUNTER also halts its counting during an emulation access in order to remain synchronized with the software While stopped the count does not advance in PWM_OUT mode the TMRx pin waveform is stretched in WDTH_CAP mode measured values are incorrect in EXT_CLK mode input events on TMRx may be missed All other timer functions such as register reads and writes inte...

Page 922: ...Timer Counter Registers Table 15 3 Timer Counter Register Memory mapped Addresses Register Name Memory mapped Address TIMER0_COUNTER 0xFFC0 0604 TIMER1_COUNTER 0xFFC0 0614 TIMER2_COUNTER 0xFFC0 0624 TIMER3_COUNTER 0xFFC0 0634 TIMER4_COUNTER 0xFFC0 0644 TIMER5_COUNTER 0xFFC0 0654 TIMER6_COUNTER 0xFFC0 0664 TIMER7_COUNTER 0xFFC0 0674 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 923: ...egister is not used If new values are not written to the timer period register or the timer pulse width register the value from the previous period is reused Writes to the 32 bit timer period register and timer pulse width register are atomic it is not possible for the high word to be written without the low word also being written Values written to the timer period registers or timer pulse width ...

Page 924: ...ess than 10 counts there may not be enough time between updates from the buffer registers to write both the timer period register and the timer pulse width register The next period may use one old value and one new value In order to prevent pulse width period errors write the timer pulse width register before the timer period register when decreasing the values and write the timer period register ...

Page 925: ...xFFC0 0668 TIMER7_PERIOD 0xFFC0 0678 Figure 15 23 Timer Width Registers Table 15 5 Timer Width Register Memory mapped Addresses Register Name Memory mapped Address TIMER0_WIDTH 0xFFC0 060C TIMER1_WIDTH 0xFFC0 061C TIMER2_WIDTH 0xFFC0 062C TIMER3_WIDTH 0xFFC0 063C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer Width 15 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0...

Page 926: ...er 0 No effect TIMER_DISABLE 1 Disable timer at end of period 0 No effect 1 Disable timer 0 No effect 1 Disable timer 0 No effect TMODE b 01 b 10 b 11 PULSE_HI 1 Generate high width 0 Generate low width 1 Measure high width 0 Measure low width 1 Count rising edges 0 Count falling edges PERIOD_CNT 1 Generate PWM 0 Single width pulse 1 Interrupt after measuring period 0 Interrupt after measuring wid...

Page 927: ...iod every one counter period Unused Unused ERR_TYP Reports b 00 b 01 b 10 or b 11 as appropriate Reports b 00 or b 01 as appropriate Reports b 00 b 01 or b 10 as appropri ate EMU_RUN 0 Halt during emulation 1 Count during emulation 0 Halt during emulation 1 Count during emulation 0 Halt during emulation 1 Count during emulation TMR Pin Depends on OUT_DIS 1 Three state 0 Output Depends on TIN_SEL 1...

Page 928: ...status Write 1 No effect 0 No effect TOVF_ERR Set at startup or roll over if period 0 or 1 Set at rollover if width Period Set if counter wraps Set if counter wraps Set if counter wraps or set at startup or roll over if period 0 IRQ Depends on IRQ_ENA 1 Set when TOVF_ERR set or when counter equals period and PERIOD_CNT 1 or when counter equals width and PERIOD_CNT 0 0 Not set Depends on IRQ_ENA 1 ...

Page 929: ...s width 0x20 SCLKs while the PWM sig nal generated by timer 4 has the same period but 25 duty cycle width 0x10 SCLKs If the preprocessor constant SINGLE_PULSE is defined every TMRx pin out puts only a single high pulse of 0x20 timer 4 and 0x10 SCLKs timer 5 duration In any case the timers are started synchronously and the rising edges are aligned that is the pulses are left aligned Listing 15 2 Si...

Page 930: ...if r7 l TIMEN5 TIMEN4 w p5 r7 r7 7 p5 5 sp rts timer45_signal_generation end All subsequent examples use interrupts Thus Listing 15 3 illustrates how interrupts are generated and how interrupt service routines can be regis ters In this example the timer 5 interrupt is assigned to the IVG7 interrupt channel of the CEC controller Listing 15 3 Interrupt Setup timer5_interrupt_setup sp r7 7 p5 5 p5 h ...

Page 931: ... nesting r7 7 p5 5 sp sp reti rts timer5_interrupt_setup end The example shown in Listing 15 4 does not drive the TMRx pin It gener ates periodic interrupt requests every 0x1000 SCLK cycles If the preprocessor constant SINGLE_PULSE was defined timer 5 requests an interrupt only once Unlike in a real application the purpose of the inter rupt service routine shown in this example is just the clearin...

Page 932: ...PWM_OUT endif w p5 TIMER5_CONFIG TIMER_ENABLE r7 r7 0x1000 z ifndef SINGLE_PULSE p5 TIMER5_PERIOD TIMER_ENABLE r7 r7 0x1 z endif p5 TIMER5_WIDTH TIMER_ENABLE r7 r7 l TIMEN5 w p5 r7 r7 7 p5 5 sp r0 0 z rts timer5_interrupt_generation end isr_timer5 sp astat sp r7 7 p5 5 p5 h hi TIMER_STATUS p5 l lo TIMER_STATUS r7 h hi TIMIL5 r7 l lo TIMIL5 p5 r7 r0 1 ssync r7 7 p5 5 sp astat sp rti isr_timer5 end ...

Page 933: ...ns how the signal waveform represented by the period P and the pulse width W translates to timer period and width values Table 15 7 summarizes the register writes Figure 15 24 Non Overlapping Clock Pulses Table 15 7 Register Writes for Non Overlapping Clock Pulses Register Before Enable After Enable At IRQ1 At IRQ2 TIMER5_PERIOD P 2 TIMER5_WIDTH P 2 W 2 W 2 P 2 W 2 W 2 TIMER4_PERIOD P P 2 TIMER4_W...

Page 934: ... 0x1000 signal period define W 0x0600 signal pulse width define N 4 number of pulses before disable timer45_toggle_hi sp r7 1 p5 5 p5 h hi TIMER_ENABLE p5 l lo TIMER_ENABLE config timers r7 l IRQ_ENA PERIOD_CNT TOGGLE_HI PULSE_HI PWM_OUT w p5 TIMER5_CONFIG TIMER_ENABLE r7 r7 l PERIOD_CNT TOGGLE_HI PULSE_HI PWM_OUT w p5 TIMER4_CONFIG TIMER_ENABLE r7 calculate timers widths and period r0 l lo P r0 h...

Page 935: ...o N 2 1 r7 1 p5 5 sp rts timer45_toggle_hi end isr_timer5 sp astat sp r7 5 p5 5 p5 h hi TIMER_ENABLE p5 l lo TIMER_ENABLE clear interrupt request r7 h hi TIMIL5 r7 l lo TIMIL5 p5 TIMER_STATUS TIMER_ENABLE r7 toggle width values width period width r7 p5 TIMER5_PERIOD TIMER_ENABLE r6 p5 TIMER5_WIDTH TIMER_ENABLE r5 r7 r6 p5 TIMER5_WIDTH TIMER_ENABLE r5 r5 p5 TIMER4_WIDTH TIMER_ENABLE r7 r7 r5 CC r7 ...

Page 936: ...timer 5 in WDTH_CAP mode If looped back exter nally this code might be used to receive N PWM patterns generated by one of the other timers Ensure that the PWM generator and consumer both use the same PERIOD_CNT and PULSE_HI settings Listing 15 6 Timer Configured in WDTH_CAP Mode section L1_data_a align 4 define N 1024 var buffReceive N 2 section L1_code timer5_capture sp r7 7 p5 5 setup DAG2 r7 h ...

Page 937: ...NABLE r7 r7 l TIMEN5 w p5 TIMER_ENABLE TIMER_ ENABLE r7 r7 7 p5 5 sp rts timer5_capture end isr_timer5 sp astat sp r7 7 p5 5 clear interrupt request first p5 h hi TIMER_STATUS p5 l lo TIMER_STATUS r7 h hi TIMIL5 r7 l lo TIMIL5 p5 r7 r7 p5 TIMER0_PERIOD TIMER_STATUS i2 r7 r7 p5 TIMER0_WIDTH TIMER_STATUS i2 r7 ssync r7 7 p5 5 sp astat sp rti isr_timer5 end ...

Page 938: ...Programming Examples 15 62 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 939: ...d Features The core timer is a programmable 32 bit interval timer which can gener ate periodic interrupts Unlike other peripherals the core timer resides inside the Blackfin core and runs at the core clock CCLK rate Core timer features include 32 bit timer with 8 bit prescaler Operates at core clock CCLK rate Dedicated high priority interrupt channel Single shot or continuous operation Timer Overv...

Page 940: ...ated interrupt request signal which is of higher priority than all other peripher als requests Description of Operation It is up to software to initialize the core timer s counter TCOUNT before the timer is enabled The TCOUNT register can be written directly However writes to the TPERIOD register are also passed through to TCOUNT Figure 16 1 Core Timer Block Diagram DEC TSCALE CCLK TIMER ENABLE AN...

Page 941: ...R is set the core timer may then be enabled by setting the TMREN bit in the TCNTL register a Hardware behavior is undefined if TMREN is set when TMPWR 0 Interrupt Processing The core timer has its dedicated interrupt request signal which is of higher priority than all other peripherals requests The requests goes directly to the Core Event Controller CEC and does not pass the System Interrupt Contr...

Page 942: ...10 9 8 7 6 5 4 3 2 1 0 0 X X X X X X X X X X X X 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X TMPWR Core Timer Control Register TCNTL Reset Undefined TMREN 0 Puts the timer in low power mode 1 Active state Timer can be enabled using the TMREN bit Meaningful only when TMPWR 1 0 Disable timer 1 Enable timer TINT TAUTORLD Sticky status bit 0 Timer has not gene...

Page 943: ...he TCOUNT register can be written directly In auto reload mode the value written to TCOUNT may differ from the TPERIOD value to let the initial period be shorter or longer than the fol lowing ones To do this write to TPERIOD first and overwrite TCOUNT afterward Writes to TCOUNT are ignored once the timer is running Figure 16 3 Core Timer Count Register Core Timer Count Register TCOUNT 15 14 13 12 ...

Page 944: ...r TPERIOD shown in Figure 16 4 whenever TCOUNT reaches 0 Writes to TPERIOD are ignored when the timer is running Figure 16 4 Core Timer Period Register Core Timer Period Register TPERIOD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Reset Undefined Period Value 31 16 Period Value 15 0 0xFFE0 300...

Page 945: ...mming Examples Listing 16 1 configures the core timer in auto reload mode Assuming a CCLK of 500 MHz the resulting period is 1 s The initial period is twice as long as the others Listing 16 1 Core Timer Configuration include defBF534 h section L1_code global _main _main Register service routine at EVT6 and unmask interrupt p1 l lo IMASK p1 h hi IMASK Figure 16 5 Core Timer Scale Register 31 30 29 ...

Page 946: ...000 000 First Period 20 000 000 p1 l lo TCNTL p1 h hi TCNTL r0 50 z p1 TSCALE TCNTL r0 r0 l lo 10000000 r0 h hi 10000000 p1 TPERIOD TCNTL r0 r0 1 p1 TCOUNT TCNTL r0 R6 counts interrupts r6 0 z start in auto reload mode r0 TAUTORLD TMPWR TMREN z p1 r0 _main forever jump _main forever _main end interrupt service routine simple increments R6 isr_core_timer sp astat r6 1 astat sp rti isr_core_timer en...

Page 947: ...dog expires before being updated by software Watchdog timer key features include 32 bit watchdog timer 8 bit disable bit pattern System reset on expire option NMI on expire option General purpose interrupt option Typically the watchdog timer is used to supervise stability of the system software When used in this way software reloads the watchdog timer in a regular manner in so that the downward co...

Page 948: ... NMI service routine may request the host device to reset and or reboot the Blackfin processor Often the watchdog timer is also programmed to let the processor wake up from sleep mode after a programmable period of time L For easier debugging the watchdog timer does not decrement even if enabled when the processor is in emulation mode Interface Overview Figure 17 1 provides a block diagram of the ...

Page 949: ...e Core Event Controller CEC or a general purpose interrupt request is passed to the System Interrupt Controller SIC Description of Operation If enabled the 32 bit watchdog timer counts downward every SCLK cycle If it becomes 0 one of three event requests can be issued to either the CEC or the SIC Depending on how the WDEV bit field in the WDOG_CTL register is programmed the event that is generated...

Page 950: ... generated The counter stops decrementing and remains at zero Additionally the WDRO latch bit in the WDOG_CTL register is set and can be interrogated by software in case event generation is not enabled When the watchdog is programmed to generate a reset it resets the pro cessor core and peripherals If the NOBOOT bit in the SYSCR register was set by the time the watchdog reset the part the chip is ...

Page 951: ...g a 0xAD value WDDIS to the WDEN field in the WDG_CTL register Register Definitions The watchdog timer is controlled by three registers WDOG_CNT Register The watchdog count register WDOG_CNT shown in Figure 17 2 holds the 32 bit unsigned count value The WDOG_CNT register must always be accessed with 32 bit read writes The watchdog count register holds the programmable count value A valid write to ...

Page 952: ...atchdog timer is disabled writing the WDOG_CNT register pre loads the WDOG_STAT register While the watchdog timer is enabled but not rolled over yet writes to the WDOG_STAT register load it with the value in WDOG_CNT L Enabling the watchdog timer does not automatically reload WDOG_STAT from WDOG_CNT Figure 17 2 Watchdog Count Register Watchdog Count Register WDOG_CNT 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 953: ... be appropriately configured to unmask that interrupt If the generation of watchdog events is disabled the watchdog timer oper ates as described except that no event is generated when the watchdog timer expires The watchdog enable WDEN 7 0 bit field is used to enable and disable the watchdog timer Writing any value other than the disable value 0xAD into this field enables the watchdog timer This m...

Page 954: ... 0 It can be cleared only by writing a 1 to the bit when the watch dog has been disabled first Figure 17 4 Watchdog Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0 0 Watchdog Control Register WDOG_CTL WDEV 1 0 00 Generate reset event 01 Generate NMI 10 Generate GP interrupt 11 Disable event generation WDEN 7 0 0xAD Counter disabled All other values Counter enab...

Page 955: ...t to prevent the memory from being rebooted Listing 17 1 Watchdog Timer Configuration include defBF534 h define WDOGPERIOD 0x00200000 section L1_code global _reset _reset optionally test whether reset was caused by watchdog p0 h hi SWRST p0 l lo SWRST r6 w p0 z CC bittst r6 bitpos RESET_WDOG if CC jump _reset no_watchdog_reset optionally warn at system level or host device here _reset no_watchdog_...

Page 956: ...l lo WDOGPERIOD p0 r0 p0 l lo WDOG_CTL r0 l WDEN WDEV_RESET w p0 r0 jump _main _reset end The subroutine shown in Listing 17 2 can be called by software to service the watchdog Note that the value written to the WDOG_STAT register does not matter Listing 17 2 Service Watchdog service_watchdog sp p5 p5 h hi WDOG_STAT p5 l lo WDOG_STAT p5 r0 p5 sp rts service_watchdog end ...

Page 957: ... Note that the watchdog must be disabled first Listing 17 3 Watchdog Restarted by Interrupt Service Routine isr_watchdog sp astat sp p5 5 r7 7 p5 h hi WDOG_CTL p5 l lo WDOG_CTL r7 l WDDIS w p5 r7 bitset r7 bitpos WDRO w p5 r7 r7 p5 WDOG_CNT WDOG_CTL p5 WDOG_CNT WDOG_CTL r7 r7 l WDEN WDEV_GPI w p5 r7 p5 5 r7 7 sp astat sp rti isr_watchdog end ...

Page 958: ...Programming Examples 17 12 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 959: ... life counter which counts the elapsed time since the last system reset The RTC watch features are clocked by a 32 768 kHz crystal external to the processor The RTC uses dedicated power supply pins and is indepen dent of any reset which enables it to maintain functionality even when the rest of the processor is powered down The RTC input clock is divided down to a 1 Hz signal by a prescaler which ...

Page 960: ...e specified The second alarm feature allows the application to specify a day as well as a time When the day alarm inter rupt is enabled the RTC generates an interrupt on the day and time specified The alarm interrupt and day alarm interrupt can be enabled or disabled independently The RTC provides a stopwatch function that acts as a countdown timer The application can program a second count into t...

Page 961: ...iption of Operation The following sections describe the operation of the RTC Figure 18 1 RTC Block Diagram DAYS COUNTER DAY ALARM EVENT 24 HOURS EVENT 1 0 9 RTC_ALARM REGISTER RTC_PREN EQUAL HOURS COUNTER MINUTES COUNTER SECONDS COUNTER HOURS EVENT MINUTES EVENT SECONDS EVENT PRESCALE COUNTER 5 6 6 9 5 6 6 ALARM EVENT Y Y Y Y RTXI 32 768 kHz 1 Hz TICK SET RST STOPWATCH EVENT STOPWATCH ENABLE Y 16 ...

Page 962: ...enable register RTC_PREN is written using a synchronization path Clearing of the bit is synchronized to the 32 768 kHz clock This faster synchronization allows the module to be put into high speed mode bypassing the prescaler without waiting the full 1 second for the write to complete that would be necessary if the mod ule were already running with the prescaler enabled When this bit is cleared th...

Page 963: ...of real time by the counters To avoid these potential errors initialize the RTC during startup via RTC_PREN and do not dynamically alter the state of the prescaler during normal operation Running without the prescaler enabled is provided primarily as a test mode All functionality works just 32 768 times as fast Typical software should never program RTC_PREN to 0 The only reason to do so is to syn ...

Page 964: ...ply This logic is never reset it comes up in an unknown state when RTC Vdd is first powered on The RTC also contains logic powered by the same internal Vdd as the pro cessor core and other peripherals This logic contains some control functionality holding registers for PAB write data and prefetched PAB read data shadow registers for each of the five RTC Vdd powered registers This logic is reset by...

Page 965: ...us bit is set when a write is initiated and is cleared when all writes are complete The falling edge of the write pending status bit causes the write complete flag in RTC_ISTAT to be set This flag can be configured in RTC_ICTL to cause an Figure 18 2 RTC Register Architecture FALLING EDGE DETECT WRITE COMPLETE EVENT N 1 Hz TICK RST SET PAB 16 32 REG WRITE PENDING REG WRITE HOLDING REG READ SHADOW ...

Page 966: ...efore attempting a read or write Write Latency Writes to the RTC MMRs are synchronized to the 1 Hz RTC clock When setting the time of day do not factor in the delay when writing to the RTC MMRs The most accurate method of setting the RTC is to monitor the seconds 1 Hz event flag or to program an interrupt for this event and then write the current time to the RTC status register RTC_STAT in the int...

Page 967: ...reasons They always return coherent values although the values may be unknown Deep Sleep When the Dynamic Power Management Controller DPMC state is deep sleep all clocks in the system except RTXI and the RTC 1 Hz tick are stopped In this state the RTC Vdd counters continue to increment The internal Vdd shadow registers are not updated but neither can they be read During deep sleep state all bits i...

Page 968: ..._STAT can occur a full second before the write to RTC_ALARM This would cause an extra second of delay between the validity of RTC_STAT and RTC_ALARM if the value of the RTC_ALARM out of reset is the same as the value written to RTC_STAT Wait for the writes to complete on these registers before using the flags and interrupts associated with their values The following is a list of flags along with t...

Page 969: ...our field in RTC_STAT is valid Use the write complete and write pending status flags or interrupts to validate the RTC_STAT value before using this flag value or enabling the interrupt Stopwatch event flag Valid only after the RTC_SWCNT register is valid Use the write com plete and write pending status flags or interrupts to validate the RTC_SWCNT value before using this flag value or enabling the...

Page 970: ...TC_STAT is used to read or write the current time Reads return a 32 bit value that always reflects the current state of the days hours minutes and seconds counters Reads and writes must be 32 bit transactions attempted 16 bit transactions result in an MMR error Reads always return a coherent 32 bit value The hours minutes and seconds fields are usually set to match the real time of day The day cou...

Page 971: ...tch can be programmed to any value between 0 and 216 1 seconds which is a range of 18 hours 12 minutes and 15 seconds Typically software should wait for a 1 Hz tick then write RTC_SWCNT One second later RTC_SWCNT changes to the new value and begins decrement ing Because the register write occupies nearly one second the time from writing a value of N until the stopwatch interrupt is nearly N 1 seco...

Page 972: ...sked or enabled by the RTC interrupt control register RTC_ICTL The seconds interrupt is generated on each 1 Hz clock tick if enabled The minutes interrupt is generated at the 1 Hz clock tick that advances the seconds counter from 59 to 0 The hour interrupt is gener ated at the 1 Hz clock tick that advances the minute counter from 59 to 0 The 24 hour interrupt occurs once per 24 hour period at the ...

Page 973: ... regis ter is cleared at reset and during deep sleep The RTC interrupt is set whenever an event latched into the RTC_ISTAT register is enabled in the RTC_ICTL register The pending RTC interrupt is cleared whenever all enabled and set bits in RTC_ISTAT are cleared or when all bits in RTC_ICTL corresponding to pending events are cleared As shown in Figure 18 3 the RTC generates an interrupt request ...

Page 974: ... running External Vdd may still be powered Registers described as as written are holding the last value software wrote to the register If the register has not been written since RTC Vdd power was applied then the state is unknown for all bits of RTC_STAT RTC_ALARM and RTC_SWCNT and for some bits of RTC_ISTAT RTC_PREN and RTC_ICTL Figure 18 3 RTC Interrupt Structure VOLTAGE REGULATOR WRITE COMPLETE...

Page 975: ...n On On Deep sleep As written 0 Counting As written On Off Off As written X Counting As written Table 18 2 RTC System State Transition Events At This Event Execute This Sequence Power on from no power Write RTC_PREN 1 Wait for write complete Write RTC_STAT to current time Write RTC_ALARM if needed Write RTC_SWCNT Write RTC_ISTAT to clear any pending RTC events Write RTC_ICTL to enable any desired ...

Page 976: ...chedule a wakeup event Write RTC_ICTL to enable the desired RTC interrupt sources for wakeup Wait for write complete Enable RTC for wakeup in the system interrupt wakeup enable register SIC_IWR Before going to deep sleep Write RTC_ALARM and or RTC_SWCNT as needed to schedule a wakeup event Write RTC_ICTL to enable the desired RTC event sources for deep sleep wakeup Wait for write complete Before g...

Page 977: ... functions of the RTC registers Table 18 3 RTC Register Mapping Register Name Function Notes RTC_STAT RTC status register Holds time of day RTC_ICTL RTC interrupt control register Bits 14 7 are reserved RTC_ISTAT RTC interrupt sta tus register Bits 13 7 are reserved RTC_SWCNT RTC stopwatch count register Undefined at reset RTC_ALARM RTC alarm register Undefined at reset RTC_PREN Prescaler enable r...

Page 978: ...Counter 14 0 0 32767 Seconds 5 0 0 59 Minutes 5 0 0 59 Hours 3 0 0 23 Reset Undefined RTC Status Register RTC_STAT 0xFFC0 0300 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0 0 0 0 0 0 0 0 0 X X X X X X Stopwatch Interrupt Enable Alarm Interrupt Enable Hour Minute Second Seconds 1Hz Interrupt Enable Minutes Interrupt Enable Write Complete Interrupt Enable Day Alarm Interrupt Enable Day Hour Minute Secon...

Page 979: ...tes Event Flag 0 No event 1 Event occurred Hours Event Flag 0 No event 1 Event occurred Write Complete 0 Writes if any not yet complete 1 All pending writes complete Write Pending Status RO 0 No writes pending 1 At least one write pending Day Alarm Event Flag 0 No event 1 Event occurred 24 Hours Event Flag 0 No event 1 Event occurred Reset 0x0000 RTC Interrupt Status Register RTC_ISTAT All bits ar...

Page 980: ...0 X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Hours 4 0 to 23 Day 14 0 0 to 32767 Seconds 5 0 0 to 59 Minutes 5 0 0 to 59 Hours 3 0 0 to 23 Reset Undefined RTC Alarm Register RTC_ALARM 0xFFC0 0310 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREN Prescaler Enable Prescaler Enable Register RTC_PREN Reset Un...

Page 981: ...iate header file is included in the source code that is include defBF537 h for ADSP BF537 projects Enable RTC Prescaler Listing 18 1 properly enables the prescaler and clears any pending interrupts Listing 18 1 Enabling the RTC Prescaler RTC_Initialization P0 H HI RTC_PREN P0 L LO RTC_PREN R0 PREN Z enable pre scalar for 1 Hz ticks W P0 R0 L P0 L LO RTC_ISTAT R0 0x807F Z W P0 R0 L clear any pendin...

Page 982: ...he RTC prescaler has already been enabled properly Listing 18 2 RTC Stopwatch Interrupt to Exit Deep Sleep RTC Wake Up Interrupt To Be Used With Deep Sleep Code _RTC_Interrupt P0 H HI PLL_CTL P0 L LO PLL_CTL R0 W P0 Z BITCLR R0 BITPOS BYPASS W P0 R0 BYPASS Set By Default Must Clear It IDLE Must go to IDLE for PLL changes to be effected R0 0x807F Z P0 H HI RTC_ISTAT P0 L LO RTC_ISTAT W P0 R7 clear ...

Page 983: ...R1 0x807F Z W P0 R1 L clear any pending RTC interrupts R0 WRITE_COMPLETE Z mask for WRITE COMPLETE bit Poll_WC1 R1 W P0 Z R1 R1 R0 wait for Write Complete CC AZ IF CC JUMP Poll_WC1 RTC now running with correct stop watch count and interrupts P0 H HI PLL_CTL P0 L LO PLL_CTL R0 W P0 Z BITSET R0 BITPOS PDWN set PDWN To Go To Deep Sleep W P0 R0 L Issue Command for Deep Sleep CLI R0 Perform PLL Program...

Page 984: ... RTC Alarm to Exit Hibernate State Hibernate_Code P0 H HI RTC_ALARM P0 L LO RTC_ALARM R0 0x0010 Z set alarm to 16 seconds from now W P0 R0 L P0 L LO RTC_STAT R0 0 Clear RTC Status to Start Counting at 0 W P0 R0 L P0 L LO RTC_ICTL R0 ALARM Z W P0 R0 L enable Alarm interrupt P0 L LO RTC_ISTAT R0 0x807F Z W P0 R0 L clear any pending RTC interrupts R0 WRITE_COMPLETE Z Poll_WC1 R1 W P0 Z R1 R1 R0 wait ...

Page 985: ...k P0 H HI VR_CTL P0 L LO VR_CTL R0 W P0 Z BITCLR R0 0 Clear FREQ bits 0 and 1 to BITCLR R0 1 go to Hibernate State BITSET R0 BITPOS WAKE Enable RTC Wakeup W P0 R0 L CLI R0 Use PLL programming sequence to IDLE make VR_CTL changes take effect RTS Should Never Execute This ...

Page 986: ...Programming Examples 18 28 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 987: ...atile memories The boot kernel processes the boot stream block by block until it is instructed by a special command to terminate the procedure and to jump to the processor s reset vector at 0xFFA0 0000 in on chip L1 memory This process is called booting The processor features three dedicated input pins BMODE 2 0 that instruct the processor on how to behave after reset If all three pins are low whe...

Page 988: ...esses Boot Source BMODE 2 0 Execution Start Address Bypass boot ROM execute from 16 bit external memory connected to ASYNC Bank 0 000 0x2000 0000 Use boot ROM to boot from 8 bit or 16 bit mem ory PROM flash 001 0xEF00 0000 Reserved 010 0xEF00 0000 Boots from 8 16 or 24 bit addressable SPI mem ory in SPI master mode with support for Atmel AT45DB041B AT45DB081B and AT45DB161B DataFlash devices 011 0...

Page 989: ...rogramming the watchdog timer appropriately causes a watchdog timer reset Resets both the core and the peripherals excluding the RTC block and most of the DPMC The software reset register SWRST can be read to determine whether the reset source was the watchdog timer Core double fault reset If the core enters a dou ble fault state a reset can be caused by unmasking the core double fault reset mask ...

Page 990: ... bits in SYSCR configure the Boot mode that is employed after hardware reset or System Software reset See the ADSP BF53x BF56x Blackfin Processor Pro gramming Reference for further information System Reset Configuration Register SYSCR The values sensed from the BMODE 2 0 pins are latched into the system reset configuration register SYSCR when the RESET pin is deasserted The values are made availab...

Page 991: ...el 1 memory either as cache or as SRAM Figure 19 1 System Reset Configuration Register X 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMODE 2 0 Boot Mode RO 000 Bypass boot ROM execute from 16 bit external memory 001 Use Boot ROM to load from 8 bit or 16 bit flash 010 Reserved 011 Boot from serial SPI memory 100 Boot from SPI host slave mode 101 Boot from serial TWI memory 110 Boot from TWI hos...

Page 992: ...the system soft ware reset field in the software reset register SWRST Bit 3 can be read to determine whether the reset source was core double fault A core double fault reset resets both the core and the peripherals excluding the RTC block and most of the DPMC Bit 15 indicates whether a software reset has occurred since the last time SWRST was read Bit 14 and bit 13 respec tively indicate whether t...

Page 993: ...ng the reset period Figure 19 2 Software Reset Register 0 Software Reset Register SWRST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SYSTEM_RESET System Software Reset 0x0 0x6 No SW reset 0x7 Triggers SW reset RESET_SOFTWARE Software Reset Status RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0x0000 RESET_DOUBLE Core Double Fault Reset RO 0 SW reset not generated by double fault 1 SW reset generated by double fa...

Page 994: ... reset forces reboot RAISE 1 Reset Vector When reset releases in no boot mode BMODE b 000 the processor starts fetching and executing instructions from off chip memory at address 0x2000 0000 In all other boot modes the processor starts program execu tion at address 0xEF00 0000 which is populated by the on chip boot ROM On a hardware reset the boot kernel initializes the EVT1 register to 0xFFA0 000...

Page 995: ...rocessor is in supervisor mode and has full access to all system resources To enter the user mode the reset service routine must initialize the RETI register and terminate by an RTI instruc tion The code examples in Listing 19 2 and Listing 19 3 show the least instructions required to handle the reset event See the ADSP BF53x BF56x Blackfin Processor Programming Reference for details on user and s...

Page 996: ...terrupt vector EVT15 P0 L LO IMASK read modify write IMASK register R0 P0 to enable IVG15 interrupts R1 EVT_IVG15 Z R0 R0 R1 set IVG15 bit P0 R0 write back to IMASK RAISE 15 generate IVG15 interrupt request IVG 15 is not served until reset handler returns P0 L LO _usercode P0 H HI _usercode RETI P0 RETI loaded with return address RTI Return from Reset Event _reset end _usercode Wait in user mode t...

Page 997: ...ing in the on chip boot ROM starts pro cessing the boot stream The boot stream is either read from memory or received from a host processor A boot stream represents the application data and is formatted in a special manner The application data is seg mented into multiple blocks of data Each block begins with a block header The header contains control words such as the destination address and data ...

Page 998: ...Booting into scratchpad memory 0xFFB0 0000 0xFFB0 0FFF is not supported If booting to scratchpad memory is attempted the processor hangs within the on chip boot ROM Similarly booting into the upper 16 bytes of L1 data bank A 0xFF80 7FF0 0XFF80 7FFF is not supported These memory locations are used by the boot kernel for intermediate storage of block header information and cannot be initialized at b...

Page 999: ...LAG field This 10 byte header which precedes each block in the loader file contains the following information used by the on chip boot ROM during the boot process ADDRESS 4 bytes the target address to which the block boots to within memory COUNT 4 bytes the number of data bytes in the block The COUNT field can be any 32 bit value including zero FLAG 2 bytes block type and control commands Figure 1...

Page 1000: ...0 BYTE HEADER FOR BLOCK 2 BLOCK 2 10 BYTE HEADER FOR BLOCK 3 BLOCK 3 10 BYTE HEADER FOR BLOCK n 16 BIT FLAG 6 15 10 13 Flag Word 14 12 11 9 8 7 5 4 3 2 1 0 ZEROFILL 0 Non ZEROFILL block 1 ZEROFILL block FINAL INIT 0 Non INIT block 1 INIT block IGNORE 0 Non IGNORE block 1 IGNORE block RESVECT 0 Non last block 1 Last block 1 Always 1 PFLAG 3 0 GPIO number used for HWAIT signal PPORT 1 0 Port of HWAI...

Page 1001: ...ss of 0xFFA0 0000 After a hardware reset the reset vector stored in the EVT1 register is set to 0xFFA0 0000 If bit 4 no boot on software reset of the SYSCR register is set and a software reset is issued the processor vec tors to the address set in the EVT1 register This reset vector can be reconfigure to another address during runtime and hence an appli cation can vector to an address other than 0...

Page 1002: ...instructs the boot ROM to skip COUNT bytes of the boot stream In master boot modes the boot ROM can just modify its source address pointer In slave boot modes the boot ROM actively boots in the payload data to a single location in memory This essentially trashes the block The current VisualDSP tools support IGNORE blocks for global headers only currently the 4 byte DXE count see Multi Application ...

Page 1003: ...visor mode and in the lowest priority interrupt IVG15 when it jumps to L1 memory for code execution For every boot block the individual flags are processed by the algorithm shown in Figure 19 7 The IGNORE flag requires different processing for slave versus master boot modes Where master modes can simply incre ment their source address pointer slave modes actively consume and trash the payload data...

Page 1004: ...ER MODE INIT 1 DONE DEASSERT HWAIT JUMP TO EVT1 VECTOR NO ZEROFILL 1 ZERO FILL MDMA SEE NOTE 2 0 IGNORE 1 SLAVE MODE OVERWRITE DESTINATION POINTER AND SET DMA MODIFIER TO ZERO 0 FINAL 1 0 CALL TARGET ADDRESS UPDATE SOURCE POINTER NOTE 1 TEMPORARILY DEASSERT HWAIT TO REQUEST MORE DATA FROM HOST DEVICE NOTE 2 DMA AND MDMA BLOCKS SUPPORT BYTE COUNTS FROM 0 TO 232 1 BY PERFORMING MULTIPLE DMA SEQUENCE...

Page 1005: ...es the HWAIT functionality and determines whether the HWAIT strobe operates at port F G or H See Figure 19 6 on page 19 14 for the bit settings The 4 bit field PFLAG also shown in Figure 19 6 on page 19 14 then determines which GPIO pin of the chosen port is used to handshake with the host For example if PPORT b 10 and PFLAG b 0110 then HWAIT strobe is activated on PG6 For individual boot modes ce...

Page 1006: ...ignal to the inactive state encouraging the host to send data After receiving the ten bytes the boot kernel knows whether to activate the HWAIT signal and which GPIO to use If PPORT is not zero the boot kernel first senses the polarity on the respective GPIO pin Then it enables the output driver and inverts the signal polarity to immediately hold off the host The signal is not released again until...

Page 1007: ...raged to per form these steps 1 Send the first 10 bytes 2 Wait until HWAIT goes active 3 For every further byte wait until HWAIT is inactive and then send the next byte Final Initialization After the successful download of the application into the bootable mem ory and before jumping to the EVT1 vector address the boot kernel does some housekeeping work Most of the used registers are changed back t...

Page 1008: ...tates for faster boot time The INIT code is added to the beginning of the loader file stream via the elfloader Init Init_Code DXE command line switch where Init_Code DXE refers to the user provided custom initialization code executable that is by a separate VisualDSP project Figure 19 8 shows a boot stream example that per forms these steps 1 Boot INIT code into L1 memory 2 Execute INIT code 3 The...

Page 1009: ... ROM for the rest of the boot process Figure 19 8 Initialization Code Execution Boot HEADER FOR INIT BLOCK INIT BLOCK HEADER FOR L1 BLOCK L1 BLOCK HEADER FOR SDRAM BLOCK BLOCK n HEADER FOR BLOCK n SDRAM BLOCK BOOT STREAM SDRAM BLOCK ADSP BF534 BF536 BF537 PROCESSOR ON CHIP BOOT ROM INIT BLOCK L1 0xEF00 0000 HEADER FOR INIT BLOCK INIT BLOCK HEADER FOR L1 BLOCK L1 BLOCK HEADER FOR SDRAM BLOCK BLOCK ...

Page 1010: ... kernel provides sufficient stack space in scratchpad memory 0xFFB0 0000 0xFFB0 0FFF Listing 19 4 shows an example INIT code file that demonstrates the setup of the SDRAM controller Listing 19 4 Example INIT Code SDRAM Controller Setup include defBF537 h section program SP ASTAT Save registers onto Stack SP RETS SP R7 0 SP P5 0 INIT Code Section SDRAM Setup Setup_SDRAM P0 L LO EBIU_SDRRC P0 H HI E...

Page 1011: ...iple blocks represent the INIT code within the boot stream Only the last block has the INIT bit set The elfloader utility ensures that the last of these blocks vectors to the INIT code s entry address It instructs the on chip boot ROM to execute a CALL instruction to the given ADDRESS Although INIT code DXE files are built through their own VisualDSP projects they differ from standard projects INI...

Page 1012: ... file LDR structure can be used to deter mine the boundary between the individual boot streams stored in the external memory and hence provides the ability to boot in a specific DXE application Figure 19 9 Multi DXE Loader File Contents 10 BYTE HEADER FOR BLOCK 1 BLOCK 1 10 BYTE HEADER FOR BLOCK 1 BLOCK 2 10 BYTE HEADER FOR BLOCK 2 BLOCK 2 10 BYTE HEADER FOR BLOCK 3 BLOCK 3 10 BYTE HEADER FOR COUN...

Page 1013: ... 19 9 Note that each IGNORE block is headed by a 10 byte header L Currently the initial IGNORE block contains only 4 bytes of data to store the NDP In future VisualDSP versions the length of initial IGNORE blocks may increase without further notice With this NDP the boot streams are structured like a chained list The user can essentially jump through whole DXE applications within the LDR file unti...

Page 1014: ... stored in asynchronous memory bank 1 include defBF537 h provides function entry addresses P0 H HI _BOOTROM_Boot_DXE_Flash P0 L LO _BOOTROM_Boot_DXE_Flash R7 H HI 0x20100000 start of async bank 1 R7 L LO 0x20100000 JUMP P0 jump to Boot ROM This example assumes that the AMS1 strobe has already been activated The function determines whether an 8 bit or a 16 bit memory device is con nected Note that ...

Page 1015: ...hree input parameters where R7 is again the start address and R6 holds the 7 bit TWI chip select address If three address inputs of a TWI memory are named A2 A1 and A0 then R6 should provide binary b 1010 A2 A1 A0 x in its lower byte In this case R5 holds the clock divider value that is written to the TWI_CLKDIV register as shown in the example below include defBF537 h provides function entry addr...

Page 1016: ...d boot stream contained in the flash connected to AMS0 Register R7 simply requires the number of the boot stream to be loaded The parameter passed in R6 tells the function where to find the chain of boot streams include defBF537 h provides function entry addresses P0 H HI _BOOTROM_Get_DXE_Address_Flash P0 L LO _BOOTROM_Get_DXE_Address_Flash R7 2 Z DXE 3 start counting from zero R6 H HI 0x20000000 ...

Page 1017: ...e routines Programs must initialize the stack and save all required registers to the stack as the stack pointer SP is returned correctly The _BOOTROM_Get_DXE_Address_SPI function requires the same three parameters as its _BOOTROM_Boot_DXE_SPI counterpart Register R7 holds the number of the DXE whose address is to be returned by the function Enable the SPI signals in the PORTF_FER register before c...

Page 1018: ...ters as _BOOTROM_Boot_DXE_TWI Additionally pointer P2 should point to a 32 bit scratch location _main user must setup the stack pointer as well as save and restore needed resources sp h 0xFFB0 sp l 0x1000 GET DXE ADDRESS R7 holds the DXE R5 0x0811 Z TWI_CLKDIV value to produce 400 KHz SCL in a 30 duty cycle R6 0xA0 Z R6 holds the addressed memory device R7 0x3 holds the DXE to be booted in p2 h 0x...

Page 1019: ...et_DXE_Address function is used in an INIT code application care must be taken to not restore these registers before returning to the boot ROM code R0 for flash booting R3 for SPI master booting R4 for TWI master booting For example when booting from SPI do not restore R3 when booting from TWI do not restore R4 and so on When the processor returns to the on chip boot ROM after the RTS instruction ...

Page 1020: ...page 19 53 TWI Slave Boot Mode BMODE 110 on page 19 55 UART Slave Mode Boot via Master Host BMODE 111 on page 19 56 This section discusses the hardware connections required for each boot mode and explains topics specific to the individual modes Bypass No Boot Mode BMODE 000 In bypass mode BMODE 000 the processor starts code execution from address 0x2000 0000 This is the first address in the asynch...

Page 1021: ...the Blackfin processor is in any undefined state for example during powerup In bypass mode the content of the flash device is not formatted in any way Instead it holds plain application code The VisualDSP loader util ity needs to be invoked in its splitter mode to create a proper file Refer to the VisualDSP Loader Manual for more information Execution from external 16 bit memory BMODE 000 is discu...

Page 1022: ...te Because code execution from 8 bit external memory is not supported in 8 bit mode the usage of the flash PROM device is most likely restricted to booting purposes The boot kernel assumes these conditions for the flash boot mode BMODE 001 Asynchronous Memory Bank AMB 0 enabled 16 bit packing for AMB 0 enabled Bank 0 RDY is set to active high Bank 0 hold time read write deasserted to AOE deasserte...

Page 1023: ... different sections to illustrate the loader file s structure 1 Intel hex overhead 2 10 Byte header for INIT code DXE count block consisting of an ADDRESS of 10 byte seader COUNT of 10 byte header and FLAG of 10 byte header 3 INIT code DXE count block 4 10 Byte header for block 1 of INIT code DXE consisting of an ADDRESS of 10 byte header count of 10 byte header and FLAG of 10 byte header Figure 1...

Page 1024: ...INIT code DXE consisting of an ADDRESS of 10 byte header count of 10 byte header and FLAG of 10 byte header 6 DXE1 count block 7 10 Byte header for block 1 of DXE1 consisting of an ADDRESS of 10 byte header count of 10 byte header and FLAG of 10 byte header 8 Block 1 of DXE1 Figure 19 12 Example Intel Hex Loader File ...

Page 1025: ...7 0 0x20000000 xx 0x40 0x20000002 xx 0x00 0x20000004 xx 0x80 0x20000006 xx 0xFF 0x20000008 xx 0x04 0x2000000A xx 0x00 0x2000000C xx 0x00 0x2000000E xx 0x00 0x20000010 xx 0x12 0x20000012 xx 0x00 0x20000014 xx 0x5C 0x20000016 xx 0x00 0x20000018 xx 0x00 0x2000001A xx 0x00 ADDRESS COUNT FLAG DXE COUNT BLOCK ADDRESS DATA DATA 15 8 7 0 0x2000001C xx 0x00 0x2000001E xx 0x00 0x20000020 xx 0xA0 0x20000022 ...

Page 1026: ...ardware as the bypass mode This not only enables the user to support two booting methods on a given board by a single jumper on the BMODE0 pin but it also enables programming to exe cute slow subroutines directly out of the flash PROM at runtime A loader file for a 16 bit flash PROM will be exactly the same as the one shown in Figure 19 12 except that the ADDRESS of the 10 byte header for the DXE ...

Page 1027: ... into a 16 bit flash connected to asyn chronous bank 0 of the Blackfin processor the contents of memory starting at location 0x2000 0000 viewed from the Blackfin processor look like Figure 19 15 Figure 19 15 16 Bit Flash PROM Memory Contents Viewed From Blackfin Memory Window ADDRESS DATA DATA 15 8 7 0 0x20000000 0x00 0x60 0x20000002 0xFE 0x80 0x20000004 0x00 0x04 0x20000006 0x00 0x00 0x20000008 0...

Page 1028: ...kernel assumes that the SPI baud rate is SCLK 2 x 133 Kbit s SPI serial EEPROMs that are 8 bit 16 bit and 24 bit addressable are supported The SPI uses the PF10 output pin to select a single SPI EEPROM device The SPI controller submits successive read commands at addresses 0x00 0x0000 and Figure 19 16 Timing Diagram for 16 Bit Flash Boot Sequence INITIAL CORE BYTE READ OF FLASH LOCATION Ox0 DETERM...

Page 1029: ...sponding that is no data written on the MISO pin by the SPI memory This enables the boot kernel to automatically determine the type of SPI memory con nected prior to the boot procedure Although the pull up resistor on the MISO line is mandatory additional pull up resistors might also be worthwhile as well pull up the chip select signal on PF10 to ensure the SPI memory is not activated while the Bl...

Page 1030: ... ries After the correct read command and address are sent the data stored in the memory at the selected address is shifted out on the MISO pin Data is sent out sequentially from that address with continuing clock pulses Analog Devices has tested these standard SPI memory devices 8 bit addressable SPI memory 25LC040 from Microchip 16 bit addressable SPI memory 25LC640 from Microchip 24 bit addressa...

Page 1031: ...is 0xFF the on chip boot ROM sends another byte 0x00 on the MOSI pin and checks whether the incoming byte on the MISO pin is anything other than 0xFF An incoming byte other than 0xFF means that the SPI memory has responded back after two address bytes and a 16 bit addressable SPI memory device is assumed to be connected 5 If the incoming byte is 0xFF the on chip boot ROM sends another byte 0x00 on...

Page 1032: ...ines the SPI memory type con nected an 8 16 or 24 bit addressable or an Atmel DataFlash The on chip boot ROM has detected that a 16 bit addressable SPI mem ory is connected at this point Next it issues the read command and sends out address 0x0000 to read in the first 10 byte header for the INIT code DXE count block Figure 19 18 SPI Master Mode Boot Sequence SPI Memory Detection Sequence 0 SPICLK ...

Page 1033: ...Block Figure 19 20 SPI Master Mode Boot Sequence Boot 10 Byte Header for Block 1 of INIT Code DXE 0 1 1 SPICLK all PF10 all MISO all MOSI all 0 0 0x40 ADDRESS 10 BYTE HEADER FOR INIT CODE DXE COUNT BLOCK FLAG 0 DSP SENDS OUT READ COMMAND DSP SENDS OUT READ COMMAND 0x03 AND THEN TWO ADDRESS BYTES ADDR 15 8 FIRST AND THEN ADDR 7 0 0 0 0 1 0 0 0 1 0x80 0xA0 0xFF 0x04 0x00 0x00 0x00 COUNT 0x00 0x12 0 ...

Page 1034: ...al that connects to the SPISS input of the Blackfin processor on pin PF14 It can toggle with each byte transferred or remain low during the entire procedure In SPI slave boot mode the boot kernel sets the CPHA bit and clears the CPOL bit in the SPI_CTL register Therefore the MISO pin is latched on the falling edge of the MOSI pin See SPI Transfer Protocols on page 10 14 for details Eight bit data ...

Page 1035: ... an ADSP BF537 processor as the slave SPI device On the host side PF4 is used as the CS which is connected to the SPISS of the slave ADSP BF537 The SPI slave s PG0 ADSP BF537 processor functions as HWAIT and connects to PG1 of the host ADSP BF536 processor All the timing diagrams are from the SPI slave point of view The loader file used SPI_Slave_HostFile ldr is the same one as in Figure 19 12 on ...

Page 1036: ... strobe In this case PG0 is used Note the deassertion of HWAIT in Figure 19 23 after bits 8 5 of the FLAG word are processed After that the host sends out the 4 byte INIT code DXE count block the 10 byte header for block 1 of the INIT code DXE and then block 1 itself See Figure 19 24 Figure 19 23 SPI Slave Mode Boot Sequence Start of Boot Sequence 0 0 0 1 1 1 SPICLK all SPISS all MISO all MOSI all...

Page 1037: ...ave Mode Boot Sequence Boot Block 1 of INIT Code DXE Figure 19 25 SPI Slave Mode Boot Sequence Boot Block 2 of INIT Code DXE 0 0 0 1 1 SPICLK all SPISS all MISO all MOSI all PFLAG all 0 0 0x5C 0x00 0x00 0x00 INIT CODE DXE COUNT 0x00 0x00 0xA0 0xFF ADDRESS 10 BYTE HEADER FOR BLOCK 1 of INIT CODE DXE 1 0 0x46 0x00 0x00 0x00 COUNT 0xA2 0x01 FLAG 0x66 0x01 0x67 BLOCK 1 OF INIT CODE 0 1 1 SPICLK all SP...

Page 1038: ...s of the boot process 10 byte header for block 3 and block 3 itself as shown in Figure 19 27 Figure 19 26 SPI Slave Mode Boot Sequence Boot ZEROFILL Block Block 2 of DXE1 1 1 SPICLK all SPISS all MISO all MOSI all PFLAG all 0 0 ADDRESS 0xFFA00300 10 BYTE HEADER FOR BLOCK 2 OF DXE1 ZERO FILL BLOCK 0 FLAG 0x01A3 FEEDBACK STROBE 0 0 1 0 1 0 0 0 COUNT 0x00004000 NOTE THAT THE NEXT BYTE OF DATA WILL BE...

Page 1039: ... auto increment its internal address counter such that the contents of the memory device can be read sequen tially See Figure 19 28 The TWI controller is programmed so as to generate a 30 duty cycle clock in accordance with the I2 C clock specification for fast mode operation L In both TWI master and slave boot modes the upper 256 bytes starting at address 0xFF90 3F00 must not be used The boot ROM...

Page 1040: ...rt booting 0x00 Figure 19 30 shows the TWI init and zero fill blocks Figure 19 28 TWI Master Boot Mode Figure 19 29 TWI Master Booting ADSP BF537 SDA SDA SCL I2C COMPATIBLE MEMORY DEVICE SCL A0 A1 A2 VSS TWI SCL all TWI SDA all RESET all 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 THE ADSP BF534 BF536 BF537 TWI CONTROLLER OUTPUTS ON THE BUS THE ADDRESS OF THE I2C DEVIDE TO BOOT FROM 0xA0 WHERE THE LEAST SIGNIFI...

Page 1041: ... I2C Bus Specification version 2 1 The host device supplies the serial clock See Figure 19 31 and Figure 19 32 Figure 19 30 TWI Init and Zero Fill Blocks Figure 19 31 TWI Slave Booting TWI SDA all TWI SCL all RESET all 1 1 1 1 1 BUS IDLE DURING PROCESSING OF AN INIT BLOCK BUS IDLE DURING PROCESSING OF A ZERO FILL BLOCK TWI SDA all TWI SCL all RESET all 1 1 1 0 0 DURING THE PROCESSING OF INIT AND O...

Page 1042: ...ream formatted program is downloaded by the host The host agent selects a bit rate within the UART s clocking capabilities When performing the autobaud the UART expects an character 0x40 eight bits data one start bit one stop bit no parity bit on the UART0 RXD input to determine the bit rate The hardware support and the mathematical operations to perform for this autobaud detection is explained in...

Page 1043: ...the FLAG word of all block headers See Figure 19 6 on page 19 14 for details The boot kernel is not permitted to drive any of the GPIOs before the first block header has been received and evaluated completely There fore a pulling resistor on the HWAIT signal is recommended If the resistor pulls down to ground the host is always permitted to send when the HWAIT signal is low and must pause transmis...

Page 1044: ... information about UART booting Figure 19 33 UART Slave Boot Mode Figure 19 34 UART Slave Booting MASTER UART DEVICE ADSP BF537 TX UART0 RXD HOST SLAVE UART DEVICE RX UART0 TXD CTS INTERRUPT HWAIT 0 UART RX all UART TX all HWAIT all 1 0 0 0 ADSP BF537 RECEIVES THE AUTOBAUD CHARACTER 0x40 ADSP BF537 ASSERTS HWAIT AFTER RECEIVING THE FIRST HEADER 0 0 0 0 1 0 0 0 0 1 1 1 ADSP BF537 SENDS BACK FOUR BY...

Page 1045: ...into individual DXE files and displays it as individual blocks with headers ADDRESS COUNT and FLAG This handy utility can help to view a loader file s content When the file in Figure 19 12 is loaded into the LdrViewer the GUI contents look like Figure 19 36 Figure 19 35 UART Init and Zero Fill Blocks 0 UART RX all UART TX all HWAIT all 1 0 0 0 ADSP BF537 ASSERTS HWAIT DURING THE PROCESSING OF AN I...

Page 1046: ...r 19 60 ADSP BF537 Blackfin Processor Hardware Reference Note that the LdrViewer utility is a 3rd party freeware product and is not part of the standard VisualDSP software toolset Figure 19 36 Blackfin Loader File Viewer Utility ...

Page 1047: ...ty are consolidated regis ter definitions and programming examples Phase Locked Loop and Clock Control The input clock into the processor CLKIN provides the necessary clock frequency duty cycle and stability to allow accurate internal clock multi plication by means of an on chip PLL module During normal operation the user programs the PLL with a multiplication factor for CLKIN The resulting multip...

Page 1048: ...rse adjustment For a fine adjustment the PLL clock frequency can also be varied PLL Overview To provide the clock generation for the core and system the processor uses an analog PLL with programmable state machine control The PLL design serves a wide range of applications It emphasizes embed ded and portable applications and low cost general purpose processors in which performance flexibility and ...

Page 1049: ...configura tion inputs and resulting outputs In the figure the VCO is an intermediate clock from which the core clock CCLK and system clock SCLK are derived PLL Clock Multiplier Ratios The PLL control register PLL_CTL governs the operation of the PLL For details about the PLL_CTL register see PLL_CTL Register on page 20 26 The divide frequency DF bit and multiplier select MSEL 5 0 field con figure ...

Page 1050: ...ncy Under normal conditions setting DF to 1 typically results in lower power dissipation See the processor data sheet for maximum and minimum fre quencies for CLKIN CCLK and VCO The PLL control register PLL_CTL controls operation of the PLL See Figure 20 5 on page 20 26 Note that changes to the PLL_CTL register do not take effect immediately In general the PLL_CTL register is first pro grammed wit...

Page 1051: ...e reset value of CSEL 1 0 is 0x0 and the reset value of SSEL 3 0 is 0x5 These values can be reprogrammed at startup by the boot code By writing the appropriate value to PLL_DIV you can change the CSEL and SSEL value dynamically Note the divider ratio of the core clock can never be greater than the divider ratio of the system clock If the PLL_DIV register is programmed to illegal values the SCLK di...

Page 1052: ...nt register PLL_LOCKCNT defines the number of SCLK cycles that occur before the processor sets the PLL_LOCKED bit in the PLL_STAT register When execut ing the PLL programming sequence the internal PLL lock counter begins incrementing upon execution of the IDLE instruction The lock counter increments by 1 each SCLK cycle When the lock counter has incremented to the value defined in the PLL_LOCKCNT ...

Page 1053: ...e characteristics and power dissipation dynamically The DPMC provides these features that allow the user to control performance and power Multiple operating modes The processor works in four operating modes each with different performance characteristics and power dissipation profiles See Operating Modes on page 20 8 Peripheral clocks Clocks to each peripheral are disabled automat ically when the ...

Page 1054: ...n page 20 26 In these modes the core can either execute instructions or be in the Idle core state If the core is in the Idle state it can be awakened by several sources See the ADSP BF53x BF56x Blackfin Processor Programming Ref erence for details The following sections describe the DPMC PLL states in more detail as they relate to the power management controller functions Table 20 4 Operational Ch...

Page 1055: ...ock CCLK and system clock SCLK run at the input clock CLKIN frequency DMA access is available to appropri ately configured L1 and external memories In active mode it is possible not only to bypass but also to disable the PLL If disabled the PLL must be re enabled before transitioning to full on or sleep modes From active mode the processor can transition directly to full on sleep or deep sleep mod...

Page 1056: ...e reset see the ADSP BF53x BF56x Blackfin Processor Programming Reference An RTC interrupt causes the processor to transition to active mode and execution resumes from where the pro gram counter was when deep sleep mode was entered If an interrupt is also enabled in SIC_IMASK the vector is taken immediately after exiting deep sleep and the ISR is executed Note an RTC interrupt in deep sleep mode a...

Page 1057: ...ransitions In the diagram ellipses represent operating modes and rectangles represent processor states Arrows show the allowed transitions into and out of each mode or state For mode transitions the text next to each transition arrow shows the fields in the PLL control register PLL_CTL that must be changed for the transition to occur For example the transition from full on mode to sleep mode indic...

Page 1058: ...ransitions Sleep Full On Active Deep Sleep Reset Wakeup BYPASS 0 STOPCK 1 PDWN 0 PDWN 1 RTC_WAKEUP PDWN 1 STOPCK 1 PDWN 0 HARDWARE RESET BYPASS 0 PLL_OFF 0 STOPCK 0 PDWN 0 BYPASS 1 STOPCK 0 PDWN 0 Wakeup BYPASS 1 Hibernate RTC_WAKEUP WAKE 1 HARDWARE RESET WAKE 1 FREQ 00 FREQ 00 CAN Activity CANWE 1 PHY Activity PHYWE 1 ...

Page 1059: ..._OFF bit in the PLL_CTL register and then execute the PLL pro gramming sequence PLL enabled When the PLL is disabled it can be re enabled later when additional performance is required The PLL must be re enabled before transitioning to full on or sleep operating modes To re enable the PLL clear the PLL_OFF bit in the PLL_CTL register and then execute the PLL programming sequence New multiplier rati...

Page 1060: ...s other than those shown in Table 20 6 causes unpredictable behavior Programming Operating Mode Transitions The operating mode is defined by the state of the PLL_OFF BYPASS STOPCK and PDWN bits of the PLL control register PLL_CTL Merely modi fying the bits of the PLL_CTL register does not change the operating mode or the behavior of the PLL Changes to the PLL_CTL register are realized only after e...

Page 1061: ... bits CSEL and SSEL can be made dynamically they do not require execution of the PLL program ming sequence Listing 20 1 PLL Programming Sequence ASM CLI R0 disable interrupts IDLE drain pipeline and send core into IDLE state STI R0 re enable interrupts after wakeup The first two instructions in the sequence take the core to an idled state with interrupts disabled the interrupt mask IMASK is saved ...

Page 1062: ...mmed the processor proceeds in one of the following four ways If the PLL_CTL register is programmed to enter either active or full on operating mode the PLL generates a wakeup signal and then the processor continues with the STI instruction in the sequence as described in PLL Programming Sequence on page 20 15 When the state change enters full on mode from active mode or active from full on the PL...

Page 1063: ...ocessor to enter active operating mode and continue with the STI instruction in the sequence as described below A hardware reset causes the processor to execute the reset sequence For more information about hardware reset see the ADSP BF53x BF56x Blackfin Processor Programming Reference If no operating mode transition is programmed the PLL generates a wakeup signal and the processor continues with...

Page 1064: ...ote that the internal logic of the processor and much of the processor I O can be run over a range of voltages See the product data sheet for details on the allowed voltage ranges for each power domain and power dissipation data Power Supply Management The processor provides an on chip switching regulator controller which with some external hardware can generate internal voltage levels from the ex...

Page 1065: ... The state of the VR_CTL register is maintained during power down modes and hibernate It is only set to its reset value by a powerup reset sequence Writing to VR_CTL initiates a PLL relock sequence thus the PLL repro gramming sequence must be followed after modifying VR_CTL The on chip switching regulator can be modified in terms of its transient behavior in the GAIN and FREQ fields of the VR_CTL ...

Page 1066: ...allows for smaller switching capacitor and inductor values while potentially generating more EMI electromagnetic interference Table 20 9 lists the switching frequency values configured by FREQ 1 0 L To bypass onboard regulation program a value of b 00 in the FREQ field and leave the VROUT pins floating Table 20 8 GAIN Encodings GAIN Value 00 5 01 10 10 20 11 50 Table 20 9 FREQ Encodings FREQ Value...

Page 1067: ...e operating voltage level To ensure predictable behavior when varying the operating voltage the processor should be brought to a known and stable state before the operating voltage is modified The recommended procedure is to follow the PLL programming sequence when varying the voltage The four bit voltage level VLEV field identifies the nominal internal voltage level Please refer to the processor ...

Page 1068: ...e within the limits specified in the processor data sheet for the new operating voltage level Powering Down the Core Hibernate State The internal supply regulator for the processor can be shut off by writing b 00 to the FREQ bits of the VR_CTL register This disables both CCLK and SCLK Furthermore it sets the internal power supply voltage VDDINT to 0 V eliminating any leakage currents from the proc...

Page 1069: ...remove the external VDDINT voltage source a When the core is powered down VDDINT is set to 0 V and thus the internal state of the processor is not maintained with the exception of the VR_CTL register Therefore any critical informa tion stored internally memory contents register contents and so on must be written to a non volatile storage device prior to remov ing power Be sure to set the drive CKE...

Page 1070: ...ng sequence 4 When the idle state is reached VDDINT will transition to 0 V 5 When the processor is woken up whether by RTC CAN or PHY on the ADSP BF536 or ADSP BF537 or by RTC or CAN on the ADSP BF534 or by a reset interrupt the PLL relocks and the boot sequence defined by the BMODE 1 0 pin settings takes effect a Failure to allow VDDINT to complete the transition to 0 V before waking up the proce...

Page 1071: ...es reprogramming sequence when writ ten PLL_DIV PLL divisor register Can be written freely PLL_STAT PLL status register Monitors active modes of operation PLL_LOCKCNT PLL lock count register Number of SCLKs allowed for PLL to relock VR_CTL Voltage regulator control register Requires PLL reprogramming sequence when written Figure 20 4 PLL Divide Register PLL Divide Register PLL_DIV 15 14 13 12 11 1...

Page 1072: ...le power to PLL STOPCK Stop Clock 0 CCLK on 1 CCLK off PDWN Power Down 0 All internal clocks on 1 All internal clocks off Reset 0x1400 0xFFC0 0000 Output Delay 0 Do not add output delay 1 Add approximately 200 ps of delay to external memory output signals Input Delay 0 Do not add input delay 1 Add approximately 200 ps of delay to the time when inputs are latched on the external memory interface 0 ...

Page 1073: ...e Level See Table 20 10 for encodings FREQ 1 0 Switching Frequency Controls the switching oscillator frequency for the voltage regulator see Table 20 8 for encodings GAIN 1 0 Voltage Level Gain Controls how quickly the voltage output settles on its final value see Table 20 9 for encodings 0 1 1 WAKE RTC Reset Wakeup Enable 0 RTC and Reset wakeups disabled 1 RTC and Reset wakeups enabled 0xFFC0 000...

Page 1074: ...ns Some setup code has been removed for clarity and the following assumptions are made For operating mode transition examples In the ASM examples P0 points to the PLL control register PLL_CTL P1 points to the PLL divide register PLL_DIV In the C examples the appropriate headers are included and one data element is declared as follows include cdefBF537 h sets up MMR access via pREGISTER_NAME labels...

Page 1075: ...embler commands int IMASK_reg 32 bit data element to tempo rarily store IMASK short VR_CTL_reg 16 bit data element to tem porarily store VR_CTL short VLEV_field 16 bit data element for VLEV field The CAN RTC RESET and PHY GP wakeup interrupts are enabled as wakeup signals Active Mode to Full On Mode Listing 20 3 and Listing 20 4 provide code for transitioning from active operating mode to full on ...

Page 1076: ...t and write to PLL_CTL idle drain pipeline enter idled state wait for PLL wakeup sti IMASK_reg after PLL wakeup occurs restore interrupts and IMASK processor is now in Full On mode Full On Mode to Active Mode Listing 20 5 and Listing 20 6 provide code for transitioning from full on operating mode to active mode in Blackfin assembly and C code respectively Listing 20 5 Transitioning From Full On Mo...

Page 1077: ...eup occurs restore interrupts and IMASK processor is now in Active mode In the Full On Mode Change CLKIN to VCO Multiplier From 31x to 2x Listing 20 7 and Listing 20 7 provide code for changing the CLKIN to VCO multiplier from 31x to 2x in full on operating mode in Blackfin assembly and C code respectively Listing 20 7 Changing CLKIN to VCO Multiplier ASM CLI R2 disable interrupts copy IMASK to R2...

Page 1078: ...ernate State Listing 20 9 and Listing 20 10 provide code for configuring the regulator wakeups and placing the regulator in the hibernate state in Blackfin assembly and C code respectively Listing 20 9 Configuring Regulator Wakeups and Entering Hibernate State ASM R1 W P0 Z read VR_CTL register BITSET R1 8 enable wakeup from RTC reset BITSET R1 15 protect SDRAM contents during reset after wakeup B...

Page 1079: ... Changing Internal Voltage Levels Listing 20 11 and Listing 20 12 provide code for dynamically changing the internal voltage level in Blackfin assembly and C code respectively Additional code may be required to alter the core clock frequency when voltage level is being decreased Please refer to the processor data sheet for the applicable VLEV voltage range and associated supported core clock speed...

Page 1080: ...5V 5 10 Listing 20 12 Changing Core Voltage via the On Chip Regulator C VLEV_field 0xC 0xC 1 15V 5 10 in VLEV VR_reg pVR_CTL read VR_CTL into temporary data VR_reg 0xFF0F clear out current VLEV field data VLEV_field 4 shift VLEV field into proper position VR_reg VLEV_field deposit new VLEV field into VR_CTL word pVR_CTL VR_reg write new value to VR_CTL IMASK_reg cli disable interrupts copy IMASK t...

Page 1081: ...g section of the text instead of repeating the discussion in this chapter Pin Descriptions Refer to the processor data sheet for pin information including pin num bers for the 208 ball Pb free sparse MBGA and 182 ball MBGA Managing Clocks Systems can drive the clock inputs with a crystal oscillator or a buffered shaped clock derived from an external clock oscillator The external clock connects to ...

Page 1082: ...lable They include both core and periph eral interrupts The processor assigns default core priorities to system level interrupts However these system interrupts can be remapped via the sys tem interrupt assignment registers SIC_IARx For more information see Chapter 4 System Interrupts The processor core supports nested and non nested interrupts as well as self nested interrupts For explanations of...

Page 1083: ...until the store operation completes In multithreaded systems the TESTSET instruction is required to maintain semaphore consistency To ensure that the store operation is flushed through any store or write buffers issue an SSYNC instruction immediately after semaphore release The TESTSET instruction can be used to implement binary semaphores or any other type of mutual exclusion method The TESTSET i...

Page 1084: ...0 is nonzero Current thread could write thread_id to semaphore location to indicate current owner of resource R0 L THREAD_ID B P0 R0 When done using shared resource write a zero byte to P0 R0 0 B P0 R0 SSYNC NOTE Instead of busy idling in the QUERY loop one can use an operating system call to reschedule the current thread Data Delays Latencies and Throughput For detailed information on latencies a...

Page 1085: ...AM Note this interface does not require external assertion of ARDY since the internal wait state counter is sufficient for deterministic access times of memories Figure 21 1 shows the interface to 8 bit SRAM or flash Figure 21 2 shows the interface to 16 bit SRAM or flash Figure 21 1 Interface to 8 Bit SRAM or Flash ADSP BF537 ADSP BF536 ADSP BF534 8 BIT SRAM OR FLASH X DATA 7 0 ARDY BE 1 0 D 7 0 ...

Page 1086: ... 16 bit packing mode be enabled for this bank of memory Otherwise the programming model must ensure that every other 16 bit memory location is accessed starting on an even byte address 1 0 00 16 bit address Figure 21 2 Interface to 16 Bit SRAM or Flash ADSP BF537 ADSP BF536 ADSP BF534 DATA 15 0 ARDY R W OR 16 BIT SRAM OR FLASH BE 1 0 D 15 0 ADDR N 1 1 A N 0 ARE AWE AOE OE X AMS X AMS 1 0 ABE WR ...

Page 1087: ... quick to drive the devices contend There are two cases where contention can occur The first case is a read followed by a write to the same memory space In this case the data bus drivers can potentially contend with those of the memory device addressed by the read The second case is back to back reads from two different memory spaces In this case the two memory devices addressed by the two reads c...

Page 1088: ...Integrity In addition to reducing signal length and capacitive loading critical sig nals should be treated like transmission lines Capacitive loading and signal length of buses can be reduced by using a buffer for devices that operate with wait states for example SDRAMs This reduces the capacitance on signals tied to the zero wait state devices allowing these signals to switch faster and reducing ...

Page 1089: ... critical signals IBIS models are available from Analog Devices Inc that will assist signal simulation software Some signals can be cor rected with a small zero or 22 ohm resistor located near the driver The resistor value can be adjusted after measuring the signal at all endpoints For details see the reference sources in Recommended Reading on page 21 13 for suggestions on transmission line termi...

Page 1090: ... must travel through vias The ground planes must not be densely perforated with vias or traces as their effectiveness is reduced VDDINT is the highest frequency and requires special attention Two things help power filtering above 100 MHz First capacitors should be physically small to reduce the inductance Surface mount capacitors of size 0402 give better results than larger sizes Secondly lower va...

Page 1091: ...re not 5 V tolerant There are a few exceptions such as the TWI pins Level shifters are required on all other Blackfin pins to keep the pin voltage at or below absolute maximum ratings Figure 21 4 Bypass Capacitor Placement CASE 1 BYPASS CAPACITORS ON NON COMPONENT BOTTOM SIDE OF BOARD BENEATH PACKAGE a B ADSP BF537 CASE 2 BYPASS CAPACITORS ON COMPONENT TOP SIDE OF BOARD AROUND PACKAGE ...

Page 1092: ...DSP BF53x BF56x Blackfin Processor Programming Ref erence Manual Recommendations for Unused Pins Most often there is no need to terminate unused pins but the handful that do require termination are listed at the end of the pin list description section of the product data sheet If the real time clock is not used RTXI should be pulled low Programmable Outputs Programmable pins used as output pins sh...

Page 1093: ...ar to have excessive overshoot and undershoot To see the signals accurately a 1 GHz or better sampling oscilloscope is needed Recommended Reading For more information refer to High Speed Digital Design A Handbook of Black Magic Johnson Graham Prentice Hall Inc ISBN 0 13 395724 1 This book is a technical reference that covers the problems encountered in state of the art high frequency digital circu...

Page 1094: ...tors Consult your CAD software tools vendor Some companies offer demon stration versions of signal integrity software Simply by using their free software you can learn Transmission lines are real Unterminated printed circuit board traces will ring and have over shoot and undershoot Simple termination will control signal integrity problems ...

Page 1095: ...of this document click a reference in the See Page column to jump to additional information about the MMR These notes provide general information about the system mem ory mapped registers MMRs The system MMR address range is 0xFFC0 0000 0xFFDF FFFF All system MMRs are either 16 bits or 32 bits wide MMRs that are 16 bits wide must be accessed with 16 bit read or write operations MMRs that are 32 bi...

Page 1096: ...ter Name See Page 0xFFC0 0000 PLL_CTL PLL Control Register on page 20 26 0xFFC0 0004 PLL_DIV PLL Divide Register on page 20 25 0xFFC0 0008 VR_CTL Voltage Regulator Control Register on page 20 27 0xFFC0 000C PLL_STAT PLL Status Register on page 20 26 0xFFC0 0010 PLL_LOCKCNT PLL Lock Count Register on page 20 27 Table A 2 System Reset and Interrupt Control Registers Memory mapped Address Register Na...

Page 1097: ... Interrupt Assignment Register 3 on page 4 19 0xFFC0 0120 SIC_ISR System Interrupt Status Register on page 4 21 0xFFC0 0124 SIC_IWR System Interrupt Wakeup enable Register on page 4 22 Table A 3 Watchdog Timer Registers Memory mapped Address Register Name See Page 0xFFC0 0200 WDOG_CTL Watchdog Control Register on page 17 8 0xFFC0 0204 WDOG_CNT Watchdog Count Register on page 17 6 0xFFC0 0208 WDOG_...

Page 1098: ...Name See Page 0xFFC0 0300 RTC_STAT RTC Status Register on page 18 20 0xFFC0 0304 RTC_ICTL RTC Interrupt Control Register on page 18 20 0xFFC0 0308 RTC_ISTAT RTC Interrupt Status Register on page 18 21 0xFFC0 030C RTC_SWCNT RTC Stopwatch Count Register on page 18 21 0xFFC0 0310 RTC_ALARM RTC Alarm Register on page 18 22 0xFFC0 0314 RTC_PREN Prescaler Enable Register on page 18 22 Table A 5 UART0 Co...

Page 1099: ... 0xFFC0 040C UART0_LCR UART Line Control Registers on page 13 21 0xFFC0 0410 UART0_MCR UART Modem Control Registers on page 13 23 0xFFC0 0414 UART0_LSR UART Line Status Registers on page 13 24 0xFFC0 041C UART0_SCR UART Scratch Registers on page 13 31 0xFFC0 0424 UART0_GCTL UART Global Control Registers on page 13 31 Table A 6 SPI Controller Registers Memory mapped Address Register Name See Page 0...

Page 1100: ...e 0xFFC0 0600 TIMER0_CONFIG Timer Configuration Registers on page 15 44 0xFFC0 0604 TIMER0_COUNTER Timer Counter Registers on page 15 46 0xFFC0 0608 TIMER0_PERIOD Timer Period Registers on page 15 48 0xFFC0 060C TIMER0_WIDTH Timer Width Registers on page 15 49 0xFFC0 0610 TIMER1_CONFIG Timer Configuration Registers on page 15 44 0xFFC0 0614 TIMER1_COUNTER Timer Counter Registers on page 15 46 0xFF...

Page 1101: ...46 0xFFC0 0648 TIMER4_PERIOD Timer Period Registers on page 15 48 0xFFC0 064C TIMER4_WIDTH Timer Width Registers on page 15 49 0xFFC0 0650 TIMER5_CONFIG Timer Configuration Registers on page 15 44 0xFFC0 0654 TIMER5_COUNTER Timer Counter Registers on page 15 46 0xFFC0 0658 TIMER5_PERIOD Timer Period Registers on page 15 48 0xFFC0 065C TIMER5_WIDTH Timer Width Registers on page 15 49 0xFFC0 0660 TI...

Page 1102: ...atus Register on page 15 42 Table A 8 Ports Registers Memory mapped Address Register Name See Page 0xFFC0 0700 PORTFIO GPIO Data Registers on page 14 24 0xFFC0 0704 PORTFIO_CLEAR GPIO Clear Registers on page 14 25 0xFFC0 0708 PORTFIO_SET GPIO Set Registers on page 14 25 0xFFC0 070C PORTFIO_TOGGLE GPIO Toggle Registers on page 14 26 0xFFC0 0710 PORTFIO_MASKA GPIO Mask Interrupt A Registers on page ...

Page 1103: ... GPIO Set on Both Edges Registers on page 14 27 0xFFC0 0740 PORTFIO_INEN GPIO Input Enable Registers on page 14 24 0xFFC0 1500 PORTGIO GPIO Data Registers on page 14 24 0xFFC0 1504 PORTGIO_CLEAR GPIO Clear Registers on page 14 25 0xFFC0 1508 PORTGIO_SET GPIO Set Registers on page 14 25 0xFFC0 150C PORTGIO_TOGGLE GPIO Toggle Registers on page 14 26 0xFFC0 1510 PORTGIO_MASKA GPIO Mask Interrupt A Re...

Page 1104: ...ut Enable Registers on page 14 24 0xFFC0 1700 PORTHIO GPIO Data Registers on page 14 24 0xFFC0 1704 PORTHIO_CLEAR GPIO Clear Registers on page 14 25 0xFFC0 1708 PORTHIO_SET GPIO Set Registers on page 14 25 0xFFC0 170C PORTHIO_TOGGLE GPIO Toggle Registers on page 14 26 0xFFC0 1710 PORTHIO_MASKA GPIO Mask Interrupt A Registers on page 14 28 0xFFC0 1714 PORTHIO_MASKA_ CLEAR GPIO Mask Interrupt A Clea...

Page 1105: ...s on page 14 26 0xFFC0 1738 PORTHIO_EDGE Interrupt Sensitivity Registers on page 14 27 0xFFC0 173C PORTHIO_BOTH GPIO Set on Both Edges Registers on page 14 27 0xFFC0 1740 PORTHIO_INEN GPIO Input Enable Registers on page 14 24 0xFFC0 3200 PORTF_FER Function Enable Registers on page 14 23 0xFFC0 3204 PORTG_FER Function Enable Registers on page 14 23 0xFFC0 3208 PORTH_FER Function Enable Registers on...

Page 1106: ...g ister on page 12 64 0xFFC0 080C SPORT0_TFSDIV SPORTx Transmit Frame Sync Divider Reg ister on page 12 65 0xFFC0 0810 SPORT0_TX SPORTx Transmit Data Register on page 12 60 0xFFC0 0818 SPORT0_RX SPORTx Receive Data Register on page 12 62 0xFFC0 0820 SPORT0_RCR1 SPORTx Receive Configuration 1 Register on page 12 54 0xFFC0 0824 SPORT0_RCR2 SPORTx Receive Configuration 2 Register on page 12 55 0xFFC0...

Page 1107: ...age 12 71 0xFFC0 0848 SPORT0_MTCS2 SPORTx Multichannel Transmit Select Reg isters on page 12 71 0xFFC0 084C SPORT0_MTCS3 SPORTx Multichannel Transmit Select Reg isters on page 12 71 0xFFC0 0850 SPORT0_MRCS0 SPORTx Multichannel Receive Select Regis ters on page 12 69 0xFFC0 0854 SPORT0_MRCS1 SPORTx Multichannel Receive Select Regis ters on page 12 69 0xFFC0 0858 SPORT0_MRCS2 SPORTx Multichannel Rec...

Page 1108: ...eg ister on page 12 64 0xFFC0 090C SPORT1_TFSDIV SPORTx Transmit Frame Sync Divider Reg ister on page 12 65 0xFFC0 0910 SPORT1_TX SPORTx Transmit Data Register on page 12 60 0xFFC0 0918 SPORT1_RX SPORTx Receive Data Register on page 12 62 0xFFC0 0920 SPORT1_RCR1 SPORTx Receive Configuration 1 Register on page 12 54 0xFFC0 0924 SPORT1_RCR2 SPORTx Receive Configuration 2 Register on page 12 55 0xFFC...

Page 1109: ...ge 12 71 0xFFC0 0948 SPORT1_MTCS2 SPORTx Multichannel Transmit Select Reg isters on page 12 71 0xFFC0 094C SPORT1_MTCS3 SPORTx Multichannel Transmit Select Reg isters on page 12 71 0xFFC0 0950 SPORT1_MRCS0 SPORTx Multichannel Receive Select Regis ters on page 12 69 0xFFC0 0954 SPORT1_MRCS1 SPORTx Multichannel Receive Select Regis ters on page 12 69 0xFFC0 0958 SPORT1_MRCS2 SPORTx Multichannel Rece...

Page 1110: ...0 EBIU_AMGCTL Asynchronous Memory Global Control Regis ter on page 6 21 0xFFC0 0A04 EBIU_AMBCTL0 Asynchronous Memory Bank Control 0 Reg ister on page 6 22 0xFFC0 0A08 EBIU_AMBCTL1 Asynchronous Memory Bank Control 1 Reg ister on page 6 23 0xFFC0 0A10 EBIU_SDGCTL SDRAM Memory Global Control Register on page 6 68 0xFFC0 0A14 EBIU_SDBCTL SDRAM Memory Bank Control Register on page 6 63 0xFFC0 0A18 EBIU...

Page 1111: ...hen lists the register suffix and provides its offset from the Base Address As an example the DMA channel 0 Y_MODIFY register is called DMA0_Y_MODIFY and its address is 0xFFC0 0C1C Likewise the memory DMA stream 0 source current address register is called MDMA_S0_CURR_ADDR and its address is 0xFFC0 0E64 Table A 12 DMA Traffic Control Registers Memory mapped Address Register Name See Page 0xFFC0 0B...

Page 1112: ...F80 MDMA_D1_ MemDMA stream 1 source 0xFFC0 0FC0 MDMA_S1_ Table A 14 DMA Register Suffix and Offset Register Suffix Offset From Base See Page NEXT_DESC_PTR 0x00 Next Descriptor Pointer Registers on page 5 95 START_ADDR 0x04 Start Address Registers on page 5 82 CONFIG 0x08 Configuration Registers on page 5 74 X_COUNT 0x10 Inner Loop Count Registers on page 5 85 X_MODIFY 0x14 Inner Loop Address Incre...

Page 1113: ... Peripheral Map Registers on page 5 71 CURR_X_COUNT 0x30 Current Inner Loop Count Registers on page 5 87 CURR_Y_COUNT 0x38 Current Outer Loop Count Registers on page 5 92 Table A 15 PPI Registers Memory mapped Address Register Name See Page 0xFFC0 1000 PPI_CONTROL PPI Control Register on page 7 27 0xFFC0 1004 PPI_STATUS PPI Status Register on page 7 33 0xFFC0 1008 PPI_COUNT Transfer Count Register...

Page 1114: ...ffer Registers on page 13 26 0xFFC0 2000 UART1_DLL UART Divisor Latch Registers on page 13 30 0xFFC0 2004 UART1_DLH UART Divisor Latch Registers on page 13 30 0xFFC0 2004 UART1_IER UART Interrupt Enable Registers on page 13 28 0xFFC0 2008 UART1_IIR UART Interrupt Identification Registers on page 13 29 0xFFC0 200C UART1_LCR UART Line Control Registers on page 13 21 0xFFC0 2010 UART1_MCR UART Modem ...

Page 1115: ...ission Request Reset Register 1 on page 9 75 0xFFC0 2A10 CAN_TA1 Transmission Acknowledge Register 1 on page 9 77 0xFFC0 2A14 CAN_AA1 Abort Acknowledge Register 1 on page 9 76 0xFFC0 2A18 CAN_RMP1 Receive Message Pending Register 1 on page 9 71 0xFFC0 2A1C CAN_RML1 Receive Message Lost Register 1 on page 9 72 0xFFC0 2A20 CAN_MBTIF1 Mailbox Transmit Interrupt Flag Register 1 on page 9 80 0xFFC0 2A2...

Page 1116: ...eceive Message Lost Register 2 on page 9 72 0xFFC0 2A60 CAN_MBTIF2 Mailbox Transmit Interrupt Flag Register 2 on page 9 81 0xFFC0 2A64 CAN_MBRIF2 Mailbox Receive Interrupt Flag Register 2 on page 9 82 0xFFC0 2A68 CAN_MBIM2 Mailbox Interrupt Mask Register 2 on page 9 80 0xFFC0 2A6C CAN_RFH2 Remote Frame Handling Register 2 on page 9 79 0xFFC0 2A70 CAN_OPSS2 Overwrite Protection Single Shot Transmis...

Page 1117: ...xFFC0 2AC4 CAN_UCCNT Universal Counter Register on page 9 84 0xFFC0 2AC8 CAN_UCRC Universal Counter Reload Capture Register on page 9 84 0xFFC0 2ACC CAN_UCCNF Universal Counter Configuration Mode Reg ister on page 9 83 Table A 18 CAN Mailbox Acceptance Mask Registers Memory mapped Address Register Name See Section 0xFFC0 2B00 CAN_AM00L Acceptance Mask Register L on page 9 51 0xFFC0 2B04 CAN_AM00H ...

Page 1118: ...ister L on page 9 51 0xFFC0 2B44 CAN_AM08H Acceptance Mask Register H on page 9 49 0xFFC0 2B48 CAN_AM09L Acceptance Mask Register L on page 9 51 0xFFC0 2B4C CAN_AM09H Acceptance Mask Register H on page 9 49 0xFFC0 2B50 CAN_AM10L Acceptance Mask Register L on page 9 51 0xFFC0 2B54 CAN_AM10H Acceptance Mask Register H on page 9 49 0xFFC0 2B58 CAN_AM11L Acceptance Mask Register L on page 9 51 0xFFC0 ...

Page 1119: ...k Register L on page 9 51 0xFFC0 2BA4 CAN_AM20H Acceptance Mask Register H on page 9 49 0xFFC0 2BA8 CAN_AM21L Acceptance Mask Register L on page 9 51 0xFFC0 2BAC CAN_AM21H Acceptance Mask Register H on page 9 49 0xFFC0 2BB0 CAN_AM22L Acceptance Mask Register L on page 9 51 0xFFC0 2BB4 CAN_AM22H Acceptance Mask Register H on page 9 49 0xFFC0 2BB8 CAN_AM23L Acceptance Mask Register L on page 9 51 0x...

Page 1120: ... 0xFFC0 2E34 0xFFC0 2BD8 CAN_AM27L Acceptance Mask Register L on page 9 51 0xFFC0 2BDC CAN_AM27H Acceptance Mask Register H on page 9 49 0xFFC0 2BE0 CAN_AM28L Acceptance Mask Register L on page 9 51 0xFFC0 2BE4 CAN_AM28H Acceptance Mask Register H on page 9 49 0xFFC0 2BE8 CAN_AM29L Acceptance Mask Register L on page 9 51 0xFFC0 2BEC CAN_AM29H Acceptance Mask Register H on page 9 49 0xFFC0 2BF0 CAN...

Page 1121: ...0 CAN_MB10_ 11 0xFFC0 2D60 CAN_MB11_ 12 0xFFC0 2D80 CAN_MB12_ 13 0xFFC0 2DA0 CAN_MB13_ 14 0xFFC0 2DC0 CAN_MB14_ 15 0xFFC0 2DE0 CAN_MB15_ 16 0xFFC0 2E00 CAN_MB16_ 17 0xFFC0 2E20 CAN_MB17_ 18 0xFFC0 2E40 CAN_MB18_ 19 0xFFC0 2E60 CAN_MB19_ 20 0xFFC0 2E80 CAN_MB20_ 21 0xFFC0 2EA0 CAN_MB21_ 22 0xFFC0 2EC0 CAN_MB22_ 23 0xFFC0 2EE0 CAN_MB23_ 24 0xFFC0 2F00 CAN_MB24_ 25 0xFFC0 2F20 CAN_MB25_ Table A 19 CA...

Page 1122: ... Base See Page DATA0 0x00 Mailbox Word 0 Register on page 9 67 DATA1 0x04 Mailbox Word 1 Register on page 9 65 DATA2 0x08 Mailbox Word 2 Register on page 9 63 DATA3 0x0C Mailbox Word 3 Register on page 9 61 LENGTH 0x10 Mailbox Word 4 Register on page 9 59 TIMESTAMP 0x14 Mailbox Word 5 Register on page 9 57 ID0 0x18 Mailbox Word 6 Register on page 9 55 ID1 0x1C Mailbox Word 7 Register on page 9 53 ...

Page 1123: ...0 3010 EMAC_HASHHI MAC Multicast Hash Table High Register on page 8 75 0xFFC0 3014 EMAC_STAADD MAC Station Management Address Register on page 8 76 0xFFC0 3018 EMAC_STADAT MAC Station Management Data Register on page 8 78 0xFFC0 301C EMAC_FLC MAC Flow Control Register on page 8 79 0xFFC0 3020 EMAC_VLAN1 MAC VLAN1 Tag Register on page 8 81 0xFFC0 3024 EMAC_VLAN2 MAC VLAN2 Tag Register on page 8 81 ...

Page 1124: ...tatus Register on page 8 95 0xFFC0 3068 EMAC_RX_STAT Ethernet MAC RX Current Frame Status Register on page 8 98 0xFFC0 306C EMAC_RX_STKY Ethernet MAC RX Sticky Frame Status Regis ter on page 8 103 0xFFC0 3070 EMAC_RX_IRQE Ethernet MAC RX Frame Status Interrupt Enable Register on page 8 107 0xFFC0 3074 EMAC_TX_STAT Ethernet MAC TX Current Frame Status Register on page 8 108 0xFFC0 3078 EMAC_TX_STKY...

Page 1125: ...54 0xFFC0 310C EMAC_RXC_OCTET MAC Management Counter Registers on page 8 54 0xFFC0 3110 EMAC_RXC_ DMAOVF MAC Management Counter Registers on page 8 54 0xFFC0 3114 EMAC_RXC_UNICST MAC Management Counter Registers on page 8 54 0xFFC0 3118 EMAC_RXC_MULTI MAC Management Counter Registers on page 8 54 0xFFC0 311C EMAC_RXC_BROAD MAC Management Counter Registers on page 8 54 0xFFC0 3120 EMAC_RXC_LNERRI M...

Page 1126: ...8 EMAC_RXC_EQ64 MAC Management Counter Registers on page 8 54 0xFFC0 314C EMAC_RXC_LT128 MAC Management Counter Registers on page 8 54 0xFFC0 3150 EMAC_RXC_LT256 MAC Management Counter Registers on page 8 54 0xFFC0 3154 EMAC_RXC_LT512 MAC Management Counter Registers on page 8 54 0xFFC0 3158 EMAC_RXC_LT1024 MAC Management Counter Registers on page 8 54 0xFFC0 315C EMAC_RXC_GE1024 MAC Management Co...

Page 1127: ...EMAC_TXC_UNICST MAC Management Counter Registers on page 8 54 0xFFC0 31A8 EMAC_TXC_MULTI MAC Management Counter Registers on page 8 54 0xFFC0 31AC EMAC_TXC_BROAD MAC Management Counter Registers on page 8 54 0xFFC0 31B0 EMAC_TXC_ES_DFR MAC Management Counter Registers on page 8 54 0xFFC0 31B4 EMAC_TXC_MACCTL MAC Management Counter Registers on page 8 54 0xFFC0 31B8 EMAC_TXC_ALLFRM MAC Management C...

Page 1128: ...age 8 54 0xFFC0 31D8 EMAC_TXC_ABORT MAC Management Counter Registers on page 8 54 Table A 22 HMDMA Registers Memory mapped Address Register Name See Page 0xFFC0 3300 HMDMA0_CONTROL Handshake MDMA Control Registers on page 5 100 0xFFC0 3304 HMDMA0_ECINIT Handshake MDMA Initial Edge Count Regis ters on page 5 103 0xFFC0 3308 HMDMA0_BCINIT Handshake MDMA Initial Block Count Reg isters on page 5 101 0...

Page 1129: ...nitial Edge Count Regis ters on page 5 103 0xFFC0 3348 HMDMA1_BCINIT Handshake MDMA Initial Block Count Reg isters on page 5 101 0xFFC0 334C HMDMA1_ ECURGENT Handshake MDMA Edge Count Urgent Reg isters on page 5 104 0xFFC0 3350 HMDMA1_ ECOVERFLOW Handshake MDMA Edge Count Overflow Interrupt Registers on page 5 104 0xFFC0 3354 HMDMA1_ECOUNT Handshake MDMA Current Edge Count Registers on page 5 103 ...

Page 1130: ...isters Memory mapped Address Register Name See Page 0xFFE0 3000 TCNTL Core Timer Control Register on page 16 4 0xFFE0 3004 TPERIOD Core Timer Period Register on page 16 6 0xFFE0 3008 TSCALE Core Timer Scale Register on page 16 7 0xFFE0 300C TCOUNT Core Timer Count Register on page 16 5 Table A 24 Processor Specific Memory Registers Memory mapped Address Register Name See Page 0xFFE0 0004 DMEM_CONT...

Page 1131: ...a are communicated A set of test features is defined including a boundary scan register such that the component can respond to a mini mum set of instructions designed to help test printed circuit boards The standard defines test logic that can be included in an integrated cir cuit to provide standardized approaches to Testing the interconnections between integrated circuits once they have been ass...

Page 1132: ... 5 bit instruction codes to select the test mode that performs the desired test operation Several data registers defined by the JTAG standard The TAP controller is a synchronous 16 state finite state machine con trolled by the TCK and TMS pins Transitions to the various states in the diagram occur on the rising edge of TCK and are defined by the state of the TMS pin here denoted by either a logic ...

Page 1133: ... for the TAP controller Figure B 1 TAP Controller State Diagram Test Logic_Reset Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 1134: ...wide and accommodates up to 32 boundary scan instructions The instruction register holds both public and private instructions The JTAG standard requires some of the public instructions other public instructions are optional Private instructions are reserved for the manu facturer s use The binary decode column of Table B 2 lists the decode for the public instructions The register column lists the s...

Page 1135: ...ions EXTEST Binary Code 00000 The EXTEST instruction selects the boundary scan register to be connected between the TDI and TDO pins This instruction allows testing of on board circuitry external to the device Figure B 2 Serial Scan Paths TDO TDI N N 1 N 2 2 1 0 0 1 30 31 4 3 2 1 0 1 Bypass Register Boundary Scan Register JTAG Instruction Register ...

Page 1136: ...fect on internal logic The SAMPLE part of the instruction allows a snapshot of the inputs and outputs captured on the boundary scan cells Data is sampled on the ris ing edge of TCK The PRELOAD part of the instruction allows data to be loaded on the device pins and driven out on the board with the EXTEST instruction Data is pre loaded on the pins on the falling edge of TCK BYPASS Binary Code 11111 ...

Page 1137: ...nit ALU A processor component that performs arithmetic comparative and logical functions bank activate command The bank activate command causes the SDRAM to open an internal bank specified by the bank address in a row specified by the row address When the bank activate command is issued it opens a new row address in the dedicated bank The memory in the open internal bank and row is referred to as ...

Page 1138: ...th determines the number of words that the SDRAM device stores or delivers after detecting a single write or read command followed by a NOP no operation command respectively Number of NOPs burst length 1 Burst lengths of full page 8 4 2 and 1 no burst are available The burst length is selected by writing the BL bits in the SDRAM s mode register during the SDRAM powerup sequence Burst Stop command ...

Page 1139: ... tag Upper address bits stored along with the cached data line to identify the specific address source in memory that the cached line represents Cacheability Protection Lookaside Buffer CPLB Storage area that describes the access characteristics of the core memory map CAM Content Addressable Memory Also called associative memory A memory device that includes compari son logic with each bit of stor...

Page 1140: ...ess By activating Column Address Strobe CAS before activating Row Address Strobe RAS this counter is selected to supply the row address instead of the address inputs CEC See Core Event Controller circular addressing The process by which the Data Address Generator DAG wraps around or repeatedly steps through a range of registers companding Compressing expanding The process of logarithmically encodi...

Page 1141: ...AB See DMA Access Bus DAG See Data Address Generator Data Address Generator DAG Processing component that provides memory addresses when data is trans ferred between memory and registers Data Register File A set of data registers that is used to transfer data between computation units and memory while providing local storage for operands data registers Dreg Registers located in the data arithmetic...

Page 1142: ...at those systems will be testable Digital Signal Processor DSP An integrated circuit designated for high speed manipulation of analog information that has been converted into digital form direct branches Jump or call return instructions that use absolute addresses that do not change at runtime such as a program label or they use a PC relative address direct mapped Cache architecture where each lin...

Page 1143: ...ssed by the peripherals DMA chaining The linking or chaining of multiple direct memory access DMA sequences In chained DMA the I O processor loads the next DMA descriptor into the DMA parameter registers when the current DMA fin ishes and autoinitializes the next DMA sequence DMA Core Bus DCB A bus that provides a means for DMA channels to gain access to on chip memory DMA descriptor registers Reg...

Page 1144: ...a is stored as electrical charges in an array of cells each consisting of a capacitor and a transistor The cells are arranged on a chip in a grid of rows and columns Since the capacitors discharge gradually and the cells lose their information the array of cells has to be refreshed periodically DSP See Digital Signal Processor EAB See External Access Bus EBC See External Bus Controller EBIU See Ex...

Page 1145: ...ied to the chip s surface through a quartz window in the package dis charges the floating gates allowing the chip to be reprogrammed EVT Event Vector Table A table stored in memory that contains sixteen 32 bit entries each entry contains a vector address for an interrupt service routine ISR When an event occurs instruction fetch starts at the address location in the corre sponding EVT entry See IS...

Page 1146: ...o off chip memory and peripherals External Port Bus EPB A bus that connects the output of the EBIU to external devices FFT Fast Fourier Transform An algorithm for computing the Fourier transform of a set of discrete data values The FFT expresses a finite set of data points for example a peri odic sampling of a real world signal in terms of its component frequencies Or conversely the FFT reconstruc...

Page 1147: ...des some level of abstraction above assembly language often using English like statements where each com mand or statement corresponds to several machine instructions I2 C A bus standard specified in the Philips I2 C Bus Specification version 2 1 dated January 2000 IDLE An instruction that causes the processor to cease operations holding its current state until an interrupt occurs Then the process...

Page 1148: ...n a given SDRAM Each of these banks can be accessed with the bank select lines BA 1 0 The bank address can be thought of as part of the row address interrupt An event that suspends normal processing and temporarily diverts the flow of control through an interrupt service routine ISR See ISR invalid Describes the state of a cache line When a cache line is invalid a cache line match cannot occur IrD...

Page 1149: ...nel or port that supports the IEEE standard 1149 1 JTAG standard for system test This standard defines a method for serially scanning the I O status of each component in a system jump A permanent transfer of the program flow to another part of program memory latency The overhead time used to find the correct place for memory access and preparing to access it Least Recently Used algorithm Replaceme...

Page 1150: ...nal latency to access level sensitive interrupts A signal or interrupt that the processor detects if the input signal is low active when sampled on the rising edge of CLKIN LIFO Last In First Out A data structure from which the next item taken out is the most recent item put in little endian The native data store format of the processor Words and half words are stored in memory and registers with ...

Page 1151: ...ulator Memory Management Unit MMU A component of the processor that supports protection and selective cach ing of memory by using Cacheability Protection Lookaside Buffers CPLBs Mode register Internal configuration registers within SDRAM devices which allow speci fication of the SDRAM device s functionality modified addressing The process whereby the Data Address Generator DAG produces an address ...

Page 1152: ...gle cycle and they combine parallel opera tion of the computational units and memory accesses The multiple operations perform the same as if they were in corresponding single func tion computations multiplier A computational unit that performs fixed point multiplication and exe cutes fixed point multiply add and multiply subtract operations NMI Nonmaskable Interrupt A high priority interrupt that ...

Page 1153: ...egister PAB See Peripheral Access Bus page size The amount of memory which has the same row address and can be accessed with successive read or write commands without needing to acti vate another row Parallel Peripheral Interface PPI The PPI is a half duplex bidirectional port accommodating up to 16 bits of data It has a dedicated clock pin and three multiplexed frame sync pins PC Program Counter ...

Page 1154: ...e Parallel Peripheral Interface precision The number of bits after the binary point in the storage format for the number post modify addressing The process in which the Data Address Generator DAG provides an address during a data move and auto increments after the instruction is executed precharge command The precharge command closes a specific active page in an internal bank and the precharge all...

Page 1155: ... the digital watch features of the processor including time of day alarm and stopwatch countdown features ROM Read Only Memory A data storage device manufactured with fixed contents This term is most often used to refer to non volatile semiconductor memory RTC See Real Time Clock RZ Return to Zero modulation A binary encoding scheme in which two signal pulses are used for every bit A 0 is represen...

Page 1156: ...ing a bank of synchronous memory consisting of SDRAM SDRAM Synchronous Dynamic Random Access Memory A form of DRAM that includes a clock signal with its other control sig nals This clock signal allows SDRAM devices to support burst access modes that clock out a series of successive bits SDRAM bank Region of external memory that can be configured to be 16M bytes 32M bytes 64M bytes or 128M bytes an...

Page 1157: ...l peripheral devices set A group of N line storage locations in the ways of an N way cache selected by the index field of the address set associative Cache architecture that limits line placement to a number of sets or ways shifter A computational unit that completes logical and arithmetic shifts SIC System Interrupt Controller Part of the processor s two level event control mechanism The SIC work...

Page 1158: ...write memory that does not require periodic refreshing system The system includes the peripheral set timers real time clock program mable flags UART SPORTs PPI and SPIs the external memory controller EBIU the memory DMA controller as well as the interfaces between these peripherals and the optional external off chip resources System clock SCLK A component that delivers clock pulses at a frequency ...

Page 1159: ...ns one word for each of the 24 channels TWI See Two Wire Interface Two Wire Interface TWI The TWI controller allows a device to interface to an Inter IC bus as spec ified by the Philips I2 C Bus Specification version 2 1 dated January 2000 The interface is essentially a shift register that serially transmits and receives data bits one bit at a time at the SCL rate to and from other TWI devices UAR...

Page 1160: ...ee space for a cache line allocation Von Neumann architecture The architecture used by most non DSP microprocessors This architec ture uses a single address and data bus for memory access Way An array of line storage elements in an N Way cache W1C See Write 1 to Clear W1S See Write 1 to Set Write 1 to Clear W1C bit A control or status bit that can be cleared 0 by being written to with 1 Write 1 to...

Page 1161: ...data is written only to the cache line The modified cache line is written to source mem ory only when it is replaced write through A cache write policy also known as store through The write data is writ ten to both the cache line and to source memory The modified cache line is not written to the source memory when it is replaced ...

Page 1162: ...G 26 ADSP BF537 Blackfin Processor Hardware Reference ...

Page 1163: ...ster CAN_AMxxH 9 49 acceptance mask register CAN_AMxxL 9 51 access denied interrupt CAN 9 24 accesses off core 2 5 to internal memory 3 2 access to unimplemented address interrupt CAN 9 25 access way instruction address bit 11 bit 3 10 ACKE bit 9 85 active descriptor queue and DMA synchronization 5 64 active low high frame syncs serial port 12 33 active mode 1 23 20 9 active mode to full on mode e...

Page 1164: ...ous memory bank control registers EBIU_AMBCTLx 6 21 asynchronous memory controller See AMC asynchronous memory global control register EBIU_AMGCTL 6 18 asynchronous read 6 13 asynchronous serial communications 13 4 asynchronous write 6 14 ASYNC memory banks 6 3 autobaud and general purpose timers 15 34 autobaud detection 13 4 13 13 15 34 autobuffer mode 5 14 5 31 5 76 auto refresh command 6 35 6 5...

Page 1165: ... O memory space 1 7 memory architecture 1 4 block DMA 5 11 block count DMA 5 40 block diagrams bus hierarchy 2 3 CAN 9 3 core 2 5 block diagrams continued core timer 16 2 DMA controller 5 5 EBIU 6 4 general purpose timers 15 3 interrupt processing 4 16 MAC 8 3 PLL 20 3 PPI 7 2 processor 1 3 1 4 RTC 18 3 SDRAM 6 58 6 59 SPI 10 3 SPORT 12 6 TWI 11 2 UART 13 3 watchdog timer 17 2 block done interrupt...

Page 1166: ...K register 8 56 BroadcastFramesXmittedOK register 8 62 broadcast mode 10 10 10 17 10 18 BRP 9 0 field 9 10 9 45 BR signal 6 8 buffer registers timers 15 47 BUFRDERR bit 11 13 11 38 BUFWRERR bit 11 13 11 38 burst length 6 33 G 2 burst type 6 34 G 2 bus agents DAB 2 9 PAB 2 6 BUSBUSY bit 11 12 11 38 bus contention avoiding 6 11 21 7 bus cycles asynchronous read 6 13 asynchronous write 6 14 bus error...

Page 1167: ...itration 9 27 and low power designs 9 38 low power features 9 37 mailbox area registers 9 5 mailbox control 9 6 CAN continued mailboxes 9 4 mailbox interrupts 9 23 mailbox RAM 9 4 message buffers 9 4 message received 9 27 message stored 9 27 multiplexing of signals 9 2 nominal bit rate 9 11 nominal bit time 9 10 overload frame 9 26 pins 14 3 port J 14 8 propagation segment 9 11 protocol basics 9 7...

Page 1168: ...40 9 47 CAN_GIS global interrupt status register 9 40 9 47 CAN interrupt register CAN_INTR 9 46 CAN_INTR CAN interrupt register 9 40 9 46 CAN_MBIM1 mailbox interrupt mask register 1 9 79 CAN_MBIM2 mailbox interrupt mask register 2 9 80 CAN_MBIMx registers 9 41 CAN_MBRIF1 mailbox receive interrupt flag register 1 9 81 CAN_MBRIF2 mailbox receive interrupt flag register 2 9 82 CAN_MBRIFx registers 9 ...

Page 1169: ...ATUS global status register 9 39 9 44 CAN_TA1 transmission acknowledge register 1 9 77 CAN_TA2 transmission acknowledge register 2 9 77 CAN_TAx registers 9 41 CAN_TIMING CAN timing register 9 10 9 40 9 46 CAN timing register CAN_TIMING 9 46 CAN_TRR1 transmission request reset register 1 9 75 CAN_TRR2 transmission request reset register 2 9 75 CAN_TRRx registers 9 41 CAN_TRS1 transmission request s...

Page 1170: ... 22 EBIU 6 2 frequency for SPORT 12 64 internal 2 4 MAC 8 4 managing 21 1 RTC 18 4 source for general purpose timers 15 5 SPI clock signal 10 4 types 21 1 clock divide modulus register 12 64 clock domain synchronization PPI 7 16 clock input CLKIN pin 21 1 clock phase SPI 10 14 10 15 clock polarity SPI 10 14 clock rate core timer 16 1 SPORT 12 2 clock ratio changing 20 6 codecs connecting to 12 1 c...

Page 1171: ...6 1 to 16 8 block diagram 16 2 clock rate 16 1 features 16 1 initialization 16 2 internal interfaces 16 2 interrupts 16 3 core timer continued low power mode 16 3 operation 16 2 registers 16 4 scaling 16 7 core timer control register TCNTL 16 3 16 4 core timer count register TCOUNT 16 5 core timer period register TPERIOD 16 6 core timer scale register TSCALE 16 7 core voltage changing 20 33 counte...

Page 1172: ...eld filtering CAN 9 18 data formats SPORT 12 28 data input modes for PPI 7 15 to 7 17 data instruction access bit 3 10 data I O mask function 6 34 data masks 6 41 data memory control register DMEM_CONTROL 3 9 data move serial port operations 12 38 data output modes for PPI 7 18 to 7 19 data sampling serial 12 33 data test command register DTEST_COMMAND 3 10 data transfers DMA 2 10 5 1 SPI 10 17 da...

Page 1173: ...FO 5 60 2D polled 5 59 2D array example 5 108 2D interrupt driven 5 59 autobuffer mode 5 14 5 31 5 76 DMA continued bandwidth 5 50 block count 5 40 block diagram 5 5 block done interrupt 5 44 block transfers 5 11 5 41 buffer size multichannel SPORT 12 25 buses 2 8 channel registers 5 70 channels 5 45 channels and control schemes 5 55 channel specific register names 5 69 congestion 5 50 connecting ...

Page 1174: ...iderations 5 46 peripheral 5 7 peripheral channels 5 2 peripheral channels priority 5 8 peripheral interrupts 4 9 DMA continued peripheral priority and default mapping 5 49 pipelining requests 5 41 polling DMA status example 5 110 polling registers 5 56 and PPI 7 37 prioritization and traffic control 5 48 to 5 55 programming examples 5 107 to 5 118 receive 5 30 receive restart or finish 5 39 refre...

Page 1175: ...DONE interrupt 5 78 DMAEN bit 5 21 5 66 5 74 5 78 DMA_ERR bit 5 79 DMA_ERROR interrupt 5 32 DMA error interrupts 5 80 DMA external bus See DEB DMA performance optimization 5 44 DMA queue completion interrupt 5 64 DMAR0 pin 5 6 DMAR1 pin 5 6 DMA registers 5 67 5 68 DMA_RUN bit 5 24 5 63 5 66 5 79 DMARx pin 5 41 DMA start address field 5 82 DMA_TC_CNT DMA traffic control counter register 5 106 DMA_T...

Page 1176: ...xPRI signal 12 5 DTxPRI SPORT output 12 6 DTxSEC signal 12 5 DTxSEC SPORT output 12 6 dynamic power management 1 23 20 1 to 20 34 dynamic power management controller 20 2 E EAB arbitration 2 11 clocking 20 2 and EBIU 6 5 frequency 2 11 performance 2 11 early frame sync 12 35 EAV signal 7 7 EBC 6 5 EBCAW 1 0 field 6 63 EBE bit 6 56 6 62 6 63 EBIU 1 9 6 1 to 6 83 as slave 6 5 asynchronous interfaces...

Page 1177: ...e register EMAC_MMC_RIRQE 8 117 EMAC MMC RX interrupt status register EMAC_MMC_RIRQS 8 115 EMAC_MMC_TIRQE EMAC MMC TX interrupt enable register 8 54 8 121 EMAC_MMC_TIRQS EMAC MMC TX interrupt status register 8 54 8 119 EMAC MMC TX interrupt enable register EMAC_MMC_TIRQE 8 121 EMAC MMC TX interrupt status register EMAC_MMC_TIRQS 8 119 EMAC multicast hash table high register EMAC_HASHHI 8 72 EMAC m...

Page 1178: ... 8 63 EMAC_TXC_MACCTL register 8 63 EMAC_TXC_MULTI register 8 62 EMAC_TXC_OCTET register 8 61 EMAC_TXC_OK register 8 60 EMAC_TXC_UNICST register 8 62 EMAC TX current frame status register EMAC_TX_STAT 8 108 EMAC_TXC_XS_COL register 8 61 EMAC_TXC_XS_DFR register 8 62 EMAC TX frame status interrupt enable register EMAC_TX_IRQE 8 114 EMAC_TX_IRQE EMAC TX frame status interrupt enable register 8 53 8 ...

Page 1179: ...mers 15 11 error signals SPI 10 20 to 10 23 error status register CAN_ESR 9 85 error warning receive interrupt CAN 9 26 error warning transmit interrupt CAN 9 26 ERR_TYP 1 0 field 15 10 15 43 15 44 15 51 ETBEI bit 13 6 13 11 13 18 13 27 13 28 Ethernet frame header 8 50 Ethernet MAC See MAC event counter CAN 9 26 event handling 4 2 events default mapping 4 11 definition 4 3 types of 4 2 event vecto...

Page 1180: ... operation 9 14 DMA 5 21 5 22 flow charts continued general purpose timers interrupt structure 15 9 GPIO 14 20 GPIO interrupt generation 14 17 PPI 7 25 SPI core driven 10 36 SPI DMA 10 37 timer EXT_CLK mode 15 35 timer PWM_OUT mode 15 14 timer WDTH_CAP mode 15 27 TWI master mode 11 29 TWI slave mode 11 28 FLOW mode DMA 5 19 FLOW value DMA 5 23 FLSx bit 10 10 10 42 FMD bit 9 49 FPE bit 13 31 13 32 ...

Page 1181: ...nc signal control of 12 51 12 56 FrameTooLongErrors register 8 57 frame track error 7 31 7 35 FREQ 1 0 field 20 20 20 27 frequencies clock and frame sync 12 26 frequency DEB 2 11 frequency EAB 2 11 FSDR bit 12 22 12 67 F signal 7 31 FT_ERR bit 7 31 7 33 7 35 full duplex 12 4 12 6 SPI 10 1 FULL_ON bit 20 26 full on mode 1 23 20 9 full on mode to active mode example 20 30 function enable register PO...

Page 1182: ... PPI 15 5 15 23 preventing errors in PWM_OUT mode 15 48 programming model 15 36 PULSE_HI toggle mode 15 18 PWM mode 15 7 PWM_OUT mode 15 13 to 15 25 15 47 registers 15 37 signal generation 15 53 single pulse generation 15 15 size of register accesses 15 38 stopping in PWM_OUT mode 15 23 three timers with same period 15 19 timer outputs 15 4 two timers with non overlapping clocks 15 20 waveform gen...

Page 1183: ...14 11 writes to registers 14 13 GPIO clear registers PORTxIO_CLEAR 14 25 GPIO data registers PORTxIO 14 24 GPIO direction registers PORTxIO_DIR 14 23 GPIO input enable registers PORTxIO_INEN 14 24 GPIO mask interrupt A clear registers PORTxIO_MASKA_CLEAR 14 31 GPIO mask interrupt A registers PORTxIO_MASKA 14 28 GPIO mask interrupt A set registers PORTxIO_MASKA_SET 14 29 GPIO mask interrupt A toggl...

Page 1184: ...2 high current option 14 5 high frequency design considerations 21 8 HM bit 8 64 8 69 HMDMA 5 11 pins 14 2 HMDMAEN bit 5 40 5 41 5 100 HMDMAx_BCINIT handshake MDMA configuration registers 5 40 5 101 HMDMAx_BCOUNT handshake MDMA current block count registers 5 41 5 101 5 102 HMDMAx_CONTROL handshake MDMA control registers 5 6 5 99 5 100 HMDMAx_ECINIT handshake MDMA initial edge count registers 5 41...

Page 1185: ... Inter IC bus 11 1 interlaced video 7 7 interleaving of data in SPORT FIFO 12 58 SPORT data 12 7 internal address mapping table 6 64 internal bank 6 33 G 12 internal boot ROM 19 1 internal clocks 2 4 internal external frame syncs See frame sync internal memory 1 6 accesses 3 2 interfaces 6 5 internal SDRAM banks 6 29 internal supply regulator shutting off 20 22 internal voltage levels changing 20 ...

Page 1186: ...4 9 UART 13 10 use in managing a descriptor queue 5 62 interrupt sensitivity registers PORTxIO_EDGE 14 27 interrupt service routine determining source of interrupt 4 8 interrupt status registers DMAx_IRQ_STATUS 5 78 5 79 MDMA_yy_IRQ_STATUS 5 78 5 79 I O interface to peripheral serial device 12 3 I O memory space 1 7 I O pins general purpose 14 10 IP checksum MAC 8 19 IRCLK bit 12 54 12 56 IrDA 13 ...

Page 1187: ... 11 loopback mode UART 13 23 LOOP bit 13 23 LOSTARB bit 11 14 11 38 LRFS bit 12 31 12 33 12 54 12 57 LSBF bit 10 41 LT_ERR_OVR bit 7 31 7 33 LT_ERR_OVR flag 7 32 LT_ERR_UNDR bit 7 31 7 33 LT_ERR_UNDR flag 7 32 LTFS bit 12 20 12 31 12 33 12 48 12 52 M MAA bit 9 45 MAC 1 14 8 1 to 8 132 aborted frames 8 16 address filter evaluation 8 14 address setup 8 129 alternative descriptor structure 8 26 block...

Page 1188: ... RX IP frame checksum calculation 8 21 RX receive status priority 8 20 speculative read 8 44 station management read 8 9 MAC continued station management read transfer 8 49 station management transfer done 8 41 station management write 8 9 station management write transfer 8 49 transfer frame protocol 8 8 transmit DMA operation 8 24 transmitting data 8 51 TX DMA data alignment 8 27 TX DMA directio...

Page 1189: ..._MBIM1 9 79 mailbox interrupt mask register 2 CAN_MBIM2 9 80 mailbox interrupts CAN 9 23 mailbox receive interrupt flag register 1 CAN_MBRIF1 9 81 mailbox receive interrupt flag register 2 CAN_MBRIF2 9 82 mailbox transmit interrupt flag register 1 CAN_MBTIF1 9 80 mailbox transmit interrupt flag register 2 CAN_MBTIF2 9 81 mailbox word 0 register CAN_MBxx_DATA0 9 67 mailbox word 1 register CAN_MBxx_...

Page 1190: ...DDR start address registers 5 82 MDMA_yy_X_COUNT inner loop count registers 5 85 MDMA_yy_X_MODIFY inner loop address increment registers 5 88 MDMA_yy_Y_COUNT outer loop count registers 5 90 MDMA_yy_Y_MODIFY outer loop address increment registers 5 93 MDn bit 9 70 measurement report general purpose timers 15 28 15 29 15 30 memory 3 1 to 3 10 accesses to internal 3 2 ADSP BF534 3 3 ADSP BF536 3 4 AD...

Page 1191: ...8 97 MMC interrupt 8 40 8 45 MMRs 1 7 address range A 1 width A 1 mode fault error 10 21 10 23 modes boot 1 25 19 34 broadcast 10 10 10 17 10 18 multichannel 12 15 serial port 12 11 SPI master 10 17 10 24 SPI slave 10 18 10 26 UART DMA 13 17 UART non DMA 13 15 MODF bit 10 21 10 43 MOSI pin 10 4 10 5 10 15 10 17 10 18 10 19 10 27 moving data serial port 12 38 MPEG compression PPI 7 39 MPKE bit 8 34...

Page 1192: ...ore accesses 2 5 offsets DMA descriptor elements 5 19 OI bit 5 100 OIE bit 5 100 onboard regulation bypassing 20 20 on chip memory 1 6 on chip switching regulator controller 20 18 open drain drivers 10 1 open drain outputs 10 17 open page 6 35 G 1 operating modes 20 8 active 1 23 20 9 deep sleep 1 24 20 10 full on 1 23 20 9 hibernate state 1 24 20 11 PPI 7 5 sleep 1 23 20 9 transition 20 11 20 12 ...

Page 1193: ... PAB 2 7 SDRAM 6 31 PERIOD_CNT bit 15 13 15 22 15 28 15 44 15 50 period value 15 0 field 16 6 period value 31 16 field 16 6 peripheral access bus See PAB peripheral DMA 5 7 peripheral DMA channels 5 45 peripheral DMA start address registers 5 82 peripheral DMA transfers 5 2 peripheral error interrupts 5 80 peripheral interrupt request lines 4 2 peripheral interrupts 4 2 4 4 4 7 to 4 13 peripheral ...

Page 1194: ...5 41 SDC supported 6 75 PJCE 1 0 field 14 22 PJSE bit 14 22 PJx pin 10 8 PLL 20 1 to 20 34 active mode 20 9 active mode effect of programming for 20 16 applying power to the PLL 20 13 block diagram 20 3 BYPASS bit 20 9 20 17 bypassing onboard regulation 20 20 CCLK derivation 20 3 changing CLKIN to VCO multiplier 20 13 changing clock ratio 20 6 clock dividers 20 3 clocking to SDRAM 20 10 clock mult...

Page 1195: ...20 2 20 3 sleep mode 20 9 20 16 STOPCK bit 20 11 voltage control 20 7 20 21 wakeup signal 20 16 PLL control register PLL_CTL 20 25 20 26 PLL_CTL PLL control register 20 4 20 25 20 26 PLL divide register PLL_DIV 20 25 PLL_DIV PLL divide register 20 5 20 25 PLL_LOCKCNT PLL lock count register 20 25 20 27 PLL lock count register PLL_LOCKCNT 20 27 PLL_LOCKED bit 20 26 PLL_OFF bit 20 26 PLL_STAT PLL st...

Page 1196: ...s 1 10 See also ports by name port width PPI 7 28 PORTx_FER function enable registers 14 14 14 23 PORTxIO_BOTH GPIO set on both edges registers 14 27 PORTxIO_CLEAR GPIO clear registers 14 25 PORTxIO_DIR GPIO direction register 14 23 PORTxIO_EDGE interrupt sensitivity registers 14 27 PORTxIO GPIO data registers 14 24 PORTxIO_INEN GPIO input enable registers 14 14 14 24 PORTxIO_MASKA_CLEAR GPIO mask...

Page 1197: ...itive inputs 7 21 enabling 7 3 7 30 7 38 enabling DMA 7 38 entire field mode 7 10 external frame syncs 7 16 7 17 7 18 features 7 1 FIFO 7 31 flow diagram 7 25 PPI continued frame start detect 7 36 frame synchronization with ITU R 656 7 12 frame sync polarity with timer peripherals 7 21 frame sync signals 7 3 frame track error 7 31 7 35 and general purpose timers 15 23 general flow for GP modes 7 1...

Page 1198: ...18 22 prescale 6 0 field 11 30 prescaler RTC 18 1 prescaler enable register RTC_PREN 18 22 priorities memory DMA operations 5 51 peripheral DMA operations 5 51 prioritization DMA 5 48 to 5 55 interrupts 4 7 private instructions B 4 probes oscilloscope 21 13 processor block diagram 1 3 1 4 programmable outputs 21 12 programmable timing characteristics EBIU 6 12 program Pxn bit 14 24 progressive vid...

Page 1199: ...t 9 44 receive buffer 7 0 field 13 26 receive configuration registers SPORTx_RCR1 SPORTx_RCR2 12 52 receive data 15 0 field 12 62 receive data 31 16 field 12 62 receive data buffer 15 0 field 10 44 receive FIFO SPORT 12 60 receive message lost interrupt CAN 9 25 receive message lost register 1 CAN_RML1 9 72 receive message lost register 2 CAN_RML2 9 72 receive message pending register 1 CAN_RMP1 9...

Page 1200: ...10 bit 8 64 8 65 RMII bit 8 64 8 66 RMLIF bit 9 25 9 48 RMLIM bit 9 25 9 47 RMLIS bit 9 25 9 47 RMLn bit 9 72 RMPn bit 9 71 ROM 1 6 6 1 round robin operation MDMA 5 52 routing of interrupts 4 3 ROVF bit 12 62 12 63 12 64 row activation SDRAM 6 32 row address 6 64 row precharge SDRAM 6 33 RPOLC bit 13 31 13 32 RRFST bit 12 55 12 57 RSCLKx pins 12 30 RSCLKx signal 12 5 RSFSE bit 12 12 12 55 12 57 RS...

Page 1201: ...18 RXCKS bit 8 93 8 94 RX_COMP bit 8 98 8 102 8 103 8 106 8 107 RX_CRC bit 8 98 8 101 8 103 8 106 8 107 RX_CTL bit 8 98 8 100 8 103 8 104 8 107 RX DMA direction error detected 8 41 RXDMAERR bit 8 95 8 96 RX_DMAO bit 8 98 8 101 8 103 8 105 8 107 RXDWA bit 8 18 8 51 8 93 8 94 RXECNT 7 0 field 9 85 RX_EQ64_CNT bit 8 116 8 118 RX_FCS_CNT bit 8 116 8 118 RX_FRAG bit 8 98 8 101 8 103 8 105 8 107 RX fram...

Page 1202: ...f core timer 16 7 scan paths B 4 SCCB bit 11 30 scheduling memory DMA 5 51 SCKE pin 6 53 SCK signal 10 4 10 15 10 17 10 19 SCLK 2 4 20 5 changing frequency 6 45 derivation 20 2 disabling 20 22 EBIU 6 2 status by operating mode table 20 8 SCLOVR bit 11 34 SCL pin 11 4 SCLSEN bit 11 12 11 38 SCOMP bit 11 19 11 43 SCOMPM bit 11 41 11 43 scratch 7 0 field 13 31 scratchpad memory and booting 19 12 SCTL...

Page 1203: ...ormance 6 31 power up sequence 6 45 powerup sequence 6 73 precharge all command 6 35 SDRAM continued precharge command 6 35 read command 6 35 read transfers 6 52 read write command 6 51 refresh 6 32 reserved 6 2 row activation 6 32 row precharge 6 33 self refresh mode 6 35 6 36 6 53 shared 6 46 sharing external 6 72 size configuration 6 62 sizes supported 3 8 6 25 smaller than 16M byte 6 65 specif...

Page 1204: ...interrupt mask register 4 7 4 20 SIC_ISR system interrupt status register 4 8 4 21 SIC_IWR systeminterruptwakeup enable register 4 9 4 22 signal integrity 21 8 sine wave input 1 22 SingleCollisionFrames register 8 60 single precharge command 6 52 single pulse generation timer 15 15 single shot transmission CAN 9 15 SINIT bit 11 19 11 43 SINITM bit 11 41 11 43 SIZE bit 10 18 10 41 size of accesses ...

Page 1205: ...4 port J 14 8 reception error 10 22 registers table 10 40 SCK signal 10 4 slave boot mode 19 48 slave device 10 6 SPI continued slave mode 10 18 10 26 slave mode DMA operation 10 32 slave select enable setup 10 8 slave select function 10 42 slave transfer preparation 10 27 SPI_FLG mapping to port pins 10 43 starting DMA transfer 10 51 starting transfer 10 46 stopping 10 48 stopping DMA transfers 1...

Page 1206: ... 10 enabling functionality 12 4 enabling multichannel mode 12 18 framed serial transfers 12 31 framed vs unframed 12 31 SPORT continued frame sync 12 32 12 35 frame sync frequencies 12 26 framing signals 12 30 general operation 12 10 H 100 standard protocol 12 25 initialization code 12 56 internal memory access 12 38 internal vs external frame syncs 12 32 late frame sync 12 18 modes 12 11 moving d...

Page 1207: ...ers SPORTx_MRCSn 12 23 12 24 12 68 SPORTx multichannel transmit select registers SPORTx_MTCSn 12 23 12 70 SPORTx_RCLKDIV SPORTx receive serial clock divider registers 12 64 SPORTx_RCR1 SPORTx receive configuration registers 12 52 SPORTx_RCR2 SPORTx receive configuration register 12 55 SPORTx_RCR2 SPORTx receive configuration registers 12 52 SPORTx receive configuration 2 registers SPORTx_RCR2 12 5...

Page 1208: ... STOPCK bit 20 26 stop mode DMA 5 13 5 75 stopping DMA transfers 5 31 stopwatch count 15 0 field 18 21 stopwatch event flag bit 18 21 stopwatch function RTC 18 2 stopwatch interrupt enable bit 18 20 STP bit 13 21 streams memory DMA 5 10 subbank access 1 0 field 3 10 subbanks L1 data memory 3 7 L1 instruction memory 3 6 supervisor mode 19 9 support technical or customer xlvii suspend mode CAN 9 37 ...

Page 1209: ...rt B 1 B 2 controller B 2 TAUTORLD bit 16 3 16 4 TCKFE bit 12 33 12 48 12 52 TCNTL core timer control register 16 3 16 4 TCOUNT core timer count register 16 2 16 5 TCP IP style checksums MAC 8 21 TCSR bit 6 68 6 77 TDA bit 9 21 9 78 TDM interfaces 12 3 TDPTR 4 0 field 9 78 TDR bit 9 21 9 78 TDTYPE 1 0 field 12 28 12 48 12 50 TE bit 8 43 8 51 8 64 8 68 technical support xlvii temporary mailbox disa...

Page 1210: ... register 15 40 15 42 timer width 15 0 field 15 49 timer width 31 16 field 15 49 timer width registers TIMERx_WIDTH 15 47 15 49 TIMERx_CONFIG timer configuration registers 15 43 15 44 TIMERx_COUNTER timer counter registers 15 6 15 45 15 46 TIMERx_PERIOD timer period registers 15 47 15 48 TIMERx_WIDTH timer width registers 15 47 15 49 time stamps CAN 9 20 TIMILx bits 15 6 15 42 timing auto refresh ...

Page 1211: ... error SPI 10 22 transmit configuration registers SPORTx_TCR1 and SPORTx_TCR2 12 47 transmit data 15 0 field 12 60 transmit data 31 16 field 12 60 transmit data buffer 15 0 field 10 44 transmit hold 7 0 field 13 26 tRAS 6 36 TRAS 3 0 field 6 68 6 70 tRC 6 38 tRCD 6 37 TRCD 2 0 field 6 68 6 71 tREF 6 39 tREFI 6 39 tRFC 6 38 TRFST bit 12 49 12 52 triggering DMA transfers 5 65 TRM bit 9 44 tRP 6 38 T...

Page 1212: ...17 TWI_MASTER_ADDR TWI master mode address register 11 37 TWI_MASTER_CTL TWI master mode control register 11 34 TWI master mode address register TWI_MASTER_ADDR 11 37 TWI master mode control register TWI_MASTER_CTL 11 34 TWI master mode status register TWI_MASTER_STAT 11 12 TWI_MASTER_STAT TWI master mode status register 11 12 TWI pins 14 3 TWI_RCV_DATA16 TWI FIFO receive data double byte register...

Page 1213: ...LATE bit 8 108 8 111 8 112 8 113 8 114 TX_LATE_CNT bit 8 120 8 122 TX_LOSS bit 8 108 8 109 8 112 8 114 TX_LOST_CNT bit 8 120 8 122 TX_LT1024_CNT bit 8 120 8 122 TX_LT128_CNT bit 8 120 8 122 TX_LT256_CNT bit 8 120 8 122 TX_LT512_CNT bit 8 120 8 122 TX_MACCTL_CNT bit 8 120 8 122 TX_MACE bit 8 112 8 113 8 114 TX_MCOLL_CNT bit 8 120 8 122 TX_MULTI bit 8 110 8 112 8 113 8 114 TX Multicast TX Broadcast ...

Page 1214: ...ission 13 36 switching from DMA to non DMA 13 18 UART continued switching from non DMA to DMA 13 19 and system DMA 13 27 timers 13 4 transmission 13 5 transmission SYNC bit use 13 39 UART divisor latch high byte registers UARTx_DLH 13 30 UART divisor latch low byte registers UARTx_DLL 13 30 UART global control registers UARTx_GCTL 13 31 UART interrupt enable registers UARTx_IER 13 27 13 28 UART in...

Page 1215: ...ee UART universal counter CAN 9 26 universal counter configuration mode register CAN_UCCNF 9 83 universal counter exceeded interrupt CAN 9 24 universal counter register CAN_UCCNT 9 84 universal counter reload capture register CAN_UCRC 9 84 unpopulated memory 6 10 UnsupportedOpcodesReceived register 8 58 unused pins 21 12 urgent DMA transfers 5 50 user mode 19 9 UTE bit 5 43 5 100 UTHE 15 0 field 5...

Page 1216: ...ount 15 0 field 17 6 watchdog count 31 16 field 17 6 watchdog count register WDOG_CNT 17 5 17 6 watchdog mode CAN 9 19 watchdog status 15 0 field 17 7 watchdog status 31 16 field 17 7 watchdog status register WDOG_STAT 17 6 17 7 watchdog timer 1 21 17 1 to 17 10 block diagram 17 2 disabling 17 5 and emulation mode 17 2 features 17 1 registers 17 5 and reset 17 4 reset 19 5 starting 17 4 zero value...

Page 1217: ... 21 write with data mask command 6 51 WSIZE 3 0 field 12 21 12 66 WT bit 9 44 WUIF bit 9 25 9 48 WUIM bit 9 25 9 47 WUIS bit 9 25 9 47 X X_COUNT 15 0 field 5 85 XFR_TYPE 1 0 field 7 5 7 27 7 30 X_MODIFY 15 0 field 5 89 XMTDATA16 15 0 field 11 45 XMTDATA8 7 0 field 11 44 XMTFLUSH bit 11 38 11 40 XMTINTLEN bit 11 38 11 39 XMTSERV bit 11 18 11 43 XMTSERVM bit 11 41 XMTSTAT 1 0 field 11 17 11 40 Y YCb...

Page 1218: ...Index I 56 ADSP BF537 Blackfin Processor Hardware Reference ...

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