Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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SDC Description of Operation
6-36 ADSP-BF537 Blackfin Processor Hardware Reference
Exit Self-Refresh Mode
When the SDRAM exits self-refresh mode, the SDRAM’s internal timer
stops refresh cycles and relinquishes control to external SDC.
SDC Timing Specs
The following SDRAM timing specs are discussed because they are used
by the SDC and SDRAM. To program the SDRAM interface, you need
the SDRAM’s specific datasheet information
L
Any absolute timing parameter must be normalized to the system
clock which allows the SDC to adapt to the timing parameter of
the device.
t
MRD
This is the required delay between issuing a mode register set and an acti-
vate command during powerup.
Dependency: system clock frequency
SDC setting: 3 system clock cycles
SDC usage:
MRS command
t
RAS
This is the required delay between issuing a bank A activate command and
issuing a bank A precharge command.
Dependency: system clock frequency
SDC setting: 1–15 normalized system clock cycles
SDC usage:
single column read/write, auto-refresh, self-refresh
command