Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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AMC Functional Description
6-16 ADSP-BF537 Blackfin Processor Hardware Reference
Asynchronous read bus cycles proceed as follows.
1. At the start of the setup period,
AMS[x]
and
AOE
assert. The address
bus becomes valid. The
ABE[1:0]
signals are low during the read.
2. At the beginning of the read access period,
ARE
asserts.
3. At the beginning of the hold period, read data is sampled on the
rising edge of the EBIU clock. The
ARE
signal deasserts after this
rising edge.
4. At the end of the hold period,
AOE
deasserts unless this bus cycle is
followed by another asynchronous read to the same memory space.
Also,
AMS[x]
deasserts unless the next cycle is to the same memory
bank.
5. Unless another read of the same memory bank is queued internally,
the AMC appends the programmed number of memory transition
time cycles.
Adding External Access Extension
The
ARDY
pin is used to insert extra wait states. The EBIU starts sampling
ARDY
on the clock cycle before the end of the programmed strobe period.
If
ARDY
is sampled as deasserted, the access period is extended. The
ARDY
pin is then sampled on each subsequent clock edge. Read data is latched
on the clock edge after
ARDY
is sampled as asserted. The read- or
write-enable remains asserted for one clock cycle after
ARDY
is sampled as
asserted. An example of this behavior is shown in Figure 6-5 , where
setup = 2 cycles, read access = 4 cycles, and hold = 1 cycle. Note the read
access period must be programmed to a minimum of two cycles to make
use of the
ARDY
input.
L
The read access period must be programmed to a minimum of two
cycles to make use of the
ARDY
input.