Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 6-13
External Bus Interface Unit
Asynchronous Reads
Figure 6-3 shows an asynchronous read bus cycle with timing pro-
grammed as setup = 2 cycles, read access = 2 cycles, hold = 1 cycle, and
transition time = 1 cycle.
Asynchronous read bus cycles proceed as follows.
1. At the start of the setup period,
AMS[x]
and
AOE
assert. The address
bus becomes valid. The
ABE[1:0]
signals are low during the read.
2. At the beginning of the read access period and after the 2 setup
cycles,
ARE
asserts.
3. At the beginning of the hold period, read data is sampled on the
rising edge of the EBIU clock. The
ARE
pin deasserts after this ris-
ing edge.
4. At the end of the hold period,
AOE
deasserts unless this bus cycle is
followed by another asynchronous read to the same memory space.
Also,
AMS[x]
deasserts unless the next cycle is to the same memory
bank.
5. Unless another read of the same memory bank is queued internally,
the AMC appends the programmed number of memory transition
time cycles.