Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

Page: 1074 / 1218

Programming Examples
20-28 ADSP-BF537 Blackfin Processor Hardware Reference
The CLKIN buffer output enable (
CLKBUFOE
) control bit allows another
device, most likely the Ethernet PHY, and the Blackfin processor to run
from a single crystal oscillator. Clearing this bit prevents the
CLKBUF
pin
from driving a buffered version of the input clock
CLKIN
.
Programming Examples
The following code examples illustrate how to use the on-chip voltage reg-
ulator and how to effect various operating mode transitions. Some setup
code has been removed for clarity, and the following assumptions are
made:
• For operating mode transition examples:
• In the ASM examples, P0 points to the PLL control register
(
PLL_CTL
). P1 points to the PLL divide register (
PLL_DIV
).
• In the C examples, the appropriate headers are included and
one data element is declared, as follows:
#include <cdefBF537.h> /* sets up MMR access via
*pREGISTER_NAME labels */
#include <ccblkfn.h> /* contains intrinsics for
Blackfin assembler commands */
int IMASK_reg; /* 32-bit data element to tempo-
rarily store IMASK */
• The PLL wakeup interrupt is enabled as a wakeup signal.
•
MSEL[5:0]
and
DF
in
PLL_CTL
are set to (b#011111) and
(b#0) respectively, signifying a
CLKIN
to
VCO
multiplier of
31x.