Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Phase Locked Loop and Clock Control
20-2 ADSP-BF537 Blackfin Processor Hardware Reference
A user-programmable value divides the
VCO
signal to generate the system
clock (
SCLK
). The
SCLK
signal clocks the Peripheral Access Bus (PAB),
DMA Access Bus (DAB), External Access Bus (EAB), and the External
Bus Interface Unit (EBIU).
L
These buses run at the PLL frequency divided by 1–15 (
SCLK
domain). Using the
SSEL
parameter of the PLL divide register,
select a divider value that allows these buses to run at or below the
maximum
SCLK
rate specified in the processor data sheet.
To optimize performance and power dissipation, the processor allows the
core and system clock frequencies to be changed dynamically in a “coarse
adjustment.” For a “fine adjustment,” the PLL clock frequency can also be
varied.
PLL Overview
To provide the clock generation for the core and system, the processor
uses an analog PLL with programmable state machine control.
The PLL design serves a wide range of applications. It emphasizes embed-
ded and portable applications and low cost, general-purpose processors, in
which performance, flexibility, and control of power dissipation are key
features. This broad range of applications requires a wide range of fre-
quencies for the clock generation circuitry. The input clock may be a
crystal, a crystal oscillator, or a buffered, shaped clock derived from an
external system clock oscillator.
The PLL interacts with the Dynamic Power Management Controller
(DPMC) block to provide power management functions for the processor.
For information about the DPMC, see
“Dynamic Power Management
Controller” on page 20-7 .