ADV8005 Hardware Reference Manual
UG-707
1.1.5.
External DDR2 Memory
Figure 5: External DDR2 Memory Interface
External DDR2 memory is required for motion adaptive de-interlacing, Frame Rate Conversion (FRC), and OSD bitmap overlay.
supports various memory options using one or two DDR2 memories of various sizes (1 Gb maximum). For full processing capabilities, two
DDR2 memories are required which use data transfers up to 250 MHz. Refer to
Section
3 for more details on the operations using the external
DDR2 memory.
1.1.6.
HDMI Transmitter
features two HDMI v1.4b transmitters. The transmitters feature an audio return channel (ARC), which allows a Sony/Philips
Digital Interface (SPDIF) audio connection between the source and sink. Each transmitter features an on-chip MPU with an I
2
C master to
perform HDCP operations and EDID operations.
Note
: The dual transmitter variants of the
are ADV8005KBCZ-8A, ADV8005KBCZ-8N and ADV8005KBCZ-8C. The single
is the ADV8005KBCZ-8B.
1.1.7.
Video Encoder
The
features a high speed digital to analog video encoder. Six high speed, NSV, 3.3 V, 12-bit video DACs provide support for worldwide
composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high
definition (HD) video formats. It is also possible to enable the
video encoder to work in simultaneous mode where both an SD and
ED/HD format are being output.
Note
: The video encoder variants of the
are the ADV8005KBCZ-8A and the ADV8005KBCZ-8N. The variants of
with no
encoder are the ADV8005KBCZ-8B and the ADV8005KBCZ-8B.
1.1.8.
Digital Video Output
Video can be output from the
via the flexible TTL port. Reusing up to 36 of the flexible TTL port pins means that video can be routed
without using HDMI, a useful cost reduction in systems which utilize FPGA interconnects (e.g. 30-bit TTL input
and 30-bit TTL output allowing 1080p 10-bit input and output). The possible configurations of the TTL output port are captured in
and
. The video TTL output port has a manually programmable CSC.
DDR2 Interface
Motion
Adaptive
De-interlacer
Frame Rate
Conversion
Bitmap OSD
Data
DDR2 Interface
Motion
Adaptive
De-interlacer
Frame Rate
Conversion
Bitmap OSD
Data
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