UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 98 of 192
DIGITAL INPUTS/OUTPUTS
DIGITAL INPUTS/OUTPUTS FEATURES
The
features a number of bidirectional general-purpose input/output (GPIO) pins. Most of the GPIO pins have multiple
functions, configurable by user code. At power up, all but one of these pins are configured as GPIOs; one pin reflects the state of the POR.
This pin can also be configured by user code to be used as a GPIO.
DIGITAL INPUTS/OUTPUTS BLOCK DIAGRAM
OUTPUT ENABLE
GPxOE
INPUT ENABLE
GPxIE
INPUT DATA
GPxIN
IOV
DD
PULL UP
ENABLE
GPxPUL
OUTPUT DATA
GPxOUT, GPxSET,
GPxCLR, GPxTGL
GPIO
1
1461-
016
Figure 18. GPIO Structure
DIGITAL INPUTS/OUTPUTS OVERVIEW
The GPIOs are grouped into four ports: Port 0, Port 1, and Port 2 contains eight GPIOs, and Port 3 contains four GPIOs. Each GPIO can
be configured as input, output, or fully open circuit and has an internal pull-up programmable resistor with a drive capability of 1 mA. All
input/output pins are functional over the full supply range (IOV
DD
= 2.9 V to 3.6 V (maximum)), and the logic input voltages are specified
as percentages of the supply as follows:
V
INL
= 0.2 ×
IOV
DD
max
V
INH
= 0.7 ×
IOV
DD
min
The absolute maximum input voltage is IOV
DD
+ 0.3 V. The typical leakage current of the GPIOs configured as input or open circuit is
50 nA per GPIO. When the
enters a power saving mode, the GPIO pins retain their states. Note that a driving peripheral
cannot drive the pin. That is, if the UART is driving the pin upon entry to deep sleep, it is isolated from the pin and power is gated. Its
state and control are restored upon wake up.
