ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 59 of 192
Address
Analog Devices
Header File Name Description
Access
0xE000ED2C HFSR
Hard fault status.
RW
0xE000ED34 MMAR
Memory manage fault address register.
RW
0xE000ED38 BFAR
Bus fault address.
RW
0xE000EF00
STIR
Software trigger interrupt register.
W
EXTERNAL INTERRUPT CONFIGURATION
Nine external interrupts are implemented. These nine external interrupts can be separately configured to detect any combination of the
following type of events:
•
Edge: rising edge, falling edge, or both rising and falling edges. An interrupt signal (pulse) is sent to the NVIC upon detecting a
transition from low to high, high to low, or on either high to low or low to high.
•
Level: high or low. An interrupt signal is generated and remains asserted in the NVIC until the conditions generating the interrupt
deassert. The level must be maintained for a minimum of one core clock cycle to be detected.
The external interrupt detection unit block is in the always on section and allows external interrupt to wake up the device when in
hibernate mode.
Ensure that the associated GPxIE register bit is enabled for the required external interrupt input. The GPxIE register enables the input path
circuit for the external interrupt. It may also be required to enable the internal pull-up resistor if no external pull-up resistor is provided.
For example, for External Interrupt 0, the following code configures P0.3 as an input, enables the pull-up resistor on P0.3, and enables the
input path. The appended code also enables external interrupt 0 NVIC interrupt source:
pADI_GP0->GPIE = 0x8; // Enable Input path for P0.3 input
pADI_GP0->GPPUL = 0x08; // enable P0.3 pull-up resistor
pADI_INTERRUPT->EI0CFG |= 0x8; // External IRQ0 enabled
NVIC_EnableIRQ(EINT0_IRQn); // Enable External interrupt 0 source
REGISTER SUMMARY: EXTERNAL INTERRUPTS
Table 65. External Interrupts Register Summary
Address
Name
Description
Reset
Access
0x40002420
EI0CFG
External Interrupt Configuration 0
0x0000
RW
0x40002424
EI1CFG
External Interrupt Configuration 1
0x0000
RW
0x40002428
EI2CFG
External Interrupt Configuration 2
0x0000
RW
0x40002430
EICLR
External interrupt clear
0x0000
RW
