UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 10 of 192
CLOCKING ARCHITECTURE OVERVIEW
The system clock, UCLK can be selected from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes.
Internally, the system clock is divided into separate clocks:
•
UCLK system clock
•
System bus clock (HCLK) for the flash, SRAM, and DMA
•
ACLK for the analog section of the chip; this is based on the 20 MHz peripheral bus clock (PCLK) output and goes to the low voltage
analog die
•
PCLK for most peripherals
All ADC performance details are based on a 20 MHz ACLK (CLKCON1[10:8] = 010b). Performance at other clock speeds is not
guaranteed; therefore, do not change CLKCON1[10:8] when the ADC is being used.
CLOCKING ARCHITECTURE OPERATION
At power-up, the processor executes at 80 MHz, sourced from the 80 MHz PLL output. The clock source for the 80 MHz PLL is the
internal 16 MHz oscillator by default. User code can select the clock source for the system clock and can divide the clock by a factor of 1
to 128, where the clock divider bits are controlled by CLKCON1[2:0]. This allows slower code execution and reduced power consumption.
Note that P1.0 must be configured first as a clock input before the clock source is switched in the clock control register.
If the clock source for the 80 MHz SPLL is required to change from the internal 16 MHz oscillator to the external HFXTAL, observe the
following procedure:
1.
Check that HFXTAL is stable by reading CLKSTAT0[14:12].
2.
Change the system clock to the internal 16 MHz oscillator using CLKCON0[1:0].
3.
Switch the input to the SPLL using CLKCON0[11].
4.
Wait until the SPLL has locked by monitoring CLKSTAT0[2:0].
5.
Change the system clock back to the SPLL clock.
REGISTER SUMMARY: CLOCK ARCHITECTURE
Table 4. Clocking Register Summary
Address
Name
Description
Reset
Access
0x40028000
CLKCON0
Miscellaneous clock settings register
0x0041
RW
0x40028004
CLKCON1
Clock dividers register
0x0200
RW
0x40028014
CLKCON5
User clock gating control register
0x0040
RW
0x40028018
CLKSTAT0
Clocking status register
0x0003
RW
REGISTER DETAILS: CLOCK ARCHITECTURE
Miscellaneous Clock Settings Register
Address: 0x40028000, Reset: 0x0041, Name: CLKCON0
Table 5. Bit Descriptions for CLKCON0
Bits
Bit Name
Description
Reset
Access
15
HFXTALIE
High frequency crystal interrupt enable.
0x0
RW
0: an interrupt to the core is not generated on a HFXTAL OK or HFXTAL not OK.
1: an interrupt to the core is generated on a HFXTAL OK or HFXTAL not OK.
14
UPLLIE
UPLL interrupt enable.
0x0
RW
0: UPLL interrupt is not generated.
1: UPLL interrupt is generated.
13
SPLLIE
SPLL interrupt enable.
0x0
RW
0: system PLL interrupt is not generated.
1: system PLL interrupt is generated.
12
RESERVED
Reserved.
0x0
R
11
PLLMUX
PLL source selection.
0x0
RW
0: internal oscillator is selected (HFOSC).
1: external oscillator is selected (HFXTAL).
