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8.

  17000043 - ADC Reference Voltages Do Not Match Specification:

DESCRIPTION:

The ADC reference voltages (VREF0, VREF1, and VREF2) are not calibrated to the specified 2.5 V.

WORKAROUND:

Use the actual ADC reference voltage values in ADC calculations, not the specified value.

APPLIES TO REVISION(S):

0.0

9.

  17000044 - DAC Output Current Limit Is Less Than Specified:

DESCRIPTION:

The maximum DAC output current load specification is 5 mA. The actual DAC output current load is limited to 1 mA.

WORKAROUND:

None.

APPLIES TO REVISION(S):

0.0

10.

  17000046 - ADC Auxiliary Bypass Mode Cannot Be Cleared By Register Write:

DESCRIPTION:

The auxiliary bypass bit cannot be cleared by a register write. If the ADC is set to enter auxiliary buffer bypass mode during operation, it
cannot subsequently be reverted to non-bypass mode.

WORKAROUND:

If the auxiliary bypass bit is set, a soft reset is required to take the AFE out of auxiliary buffer bypass mode. The ADCC drivers include the

adi_adcc_SetRegister()

 function to communicate with the AFE through the ADCC module. The ADCC drivers are furnished in the

EVAL-CM41X-EZBRD/EZLITE evaluation platform Board Support Package (BSP).

The following is an example to issue the soft reset to the Analog Front End:

 #include <drivers/adcc/adi_adcc.h>
 ADI_ADCC_HANDLE handle;
 ADI_ADCC_RESULT result;
 static char space[ADI_ADCC_MEMORY];
 
 result = adi_adcc_Open(0, space, &handle, false);
 result = adi_adcc_SetRegister(handle, REG_USER_CONFIG_REG0_USERCFG, 0x00400000);
 if (result == ADI_ADCC_SUCCESS) 
 {
    /* Success! */
 } 
 else 
 {
    /* Failure! */
 }
 

For more information about the APIs, refer to Device Driver documentation and example codes in the Board Support Package (BSP).

APPLIES TO REVISION(S):

0.0

ADSP-CM411F/412F/413F/416F/417F/418F/419F

NR004483C   |   Page 5 of 12   |   July 2017

 

 

Silicon Anomaly List

Summary of Contents for ADSP-CM411F

Page 1: ...ons and Changes 07 24 2017 C PrB Added Silicon Revision C Added Anomalies 17000067 17000080 17000082 17000083 06 27 2016 B PrB Added Anomalies 17000063 17000064 17000066 17000075 17000076 17000077 Rev...

Page 2: ...t x 14 17000055 Flash Security Features Are Not Fully Operational x 15 17000057 PLL Malfunctions at Higher Frequencies x 16 17000059 Security Keys for Devices Connected in a JTAG Chain Require Leading...

Page 3: ...s the SMC0_AOE signal is high during write operations APPLIES TO REVISION S 0 0 2 17000035 Timer0 Status Interrupt Is Not Functional DESCRIPTION SYSBLK_SISTAT15 TIMER0_STAT bit is always read as 0 The...

Page 4: ...bit of the voltage trim values for the VDD_EXT and VDD_INT power supply trip levels are not programmed at power on reset As a result of this 1 The VMU may detect a fault when the VDD_EXT and VDD_INT...

Page 5: ...erted to non bypass mode WORKAROUND If the auxiliary bypass bit is set a soft reset is required to take the AFE out of auxiliary buffer bypass mode The ADCC drivers include the adi_adcc_SetRegister fu...

Page 6: ...s are available in the EVAL CM41X EZBRD EZLITE evaluation platform Board Support Package BSP The following is an example to read from the FOCP_LATCH_0 FOCP_LATCH_1 FOCP_LATCH_2 registers include drive...

Page 7: ...er debug security bits For all other parts zeroes are appended with respect to the position of the part in the scan chain This issue occurs when security keys are provided through the TAPC security sc...

Page 8: ...T2_TX 00000X011 DMA7 SPI1_RX UART2_RX 00000X100 DMA8 HAE_IN0 UART3_TX 00000X101 DMA9 HAE_OUT UART3_RX 00000X110 DMA10 HAE_IN1 UART4_TX SPORT0A 00000X111 DMA11 SPORT0B UART4_RX 01000X000 DMA12 MDMA0_RD...

Page 9: ...t less than 16 KB for DMA writes the workaround is to place the segregated write buffers either at the top or bottom half of the 32 KB bank Ensure that the writable DMA data regions and read only DMA...

Page 10: ...sed accesses a high DMA latency value M4P_SRAM_CFG_DMAMAXLAT decreases the probability of writes getting lost when back to back writes are performed to SRAM APPLIES TO REVISION S 0 0 20 17000066 Manua...

Page 11: ...ADCC_NUMFRAMx register to a value that is less than the value read For example perform this check and adjustment in the ADCC timer event handler triggered by assertion of the ADCC_FISTAT FINTx bit Whe...

Page 12: ...ROUND None APPLIES TO REVISION S 0 0 26 17000082 Primary ADC Gain Error Correction Is Not Functional DESCRIPTION Primary ADC ADC1 and ADC2 gain error correction is not functional This feature is disab...

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