3. If DMA requires more than 32 KB for writes, ensure that the writes are linear. This issue does not exist in case of a linear addressed
DMA.
4. If Read-only DMA buffer has to be initialized, the code and variables of the function performing the initialization must reside in a
separate 32 KB bank.
For DMA-based accesses, a high DMA latency value (
M4P_SRAM_CFG_DMAMAXLAT
) decreases the probability of writes getting lost
when back-to-back writes are performed to SRAM.
APPLIES TO REVISION(S):
0.0
17000066 - Manual ECC Error Diagnostic Testing of Flash Memory Is Not Functional:
DESCRIPTION:
The
FLC_CTL.MECC
bit is intended to induce a Flash ECC error. This bit is not functional.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.0
ADSP-CM411F/412F/413F/416F/417F/418F/419F
NR004483C | Page 10 of 12 | July 2017
Silicon Anomaly List
