Analog Devices ADSP-219 Series, Hardware Reference Manual

Page: 59 / 106

ADSP-219x/2192 DSP Hardware Reference B-59
ADSP-2192 DSP Peripheral Registers
PCI Configuration Register Space, Function 2
PCI Configuration Spaces should be accessed only by the DSP, and only
during the boot process. After the PCI interface has been configured, bit 2
of the
PCI_CFGCTL register ( ConfRdy ) should be set by the DSP. This allows
the PCI interface access to these registers while at the same time denying
the DSP access.
L
Access to these registers is controlled by the PCI RDY bit in the PCI
Interrupt Control Register (Page 0x08, Address 0xA2). See
“General Purpose I/O (GPIO) Control Registers” on page B-24 .
PCI_CFG1_PWRMT Config1 Power
Mgt Capabilities
Bit 15 set, if
Vaux is sensed
valid. 0x45-0x44 n/a 0x0A 0x44
Table B-27. Function 2 Registers
Register Name Description PCI
Address USB
Address DSP
I/O
Page DSP I/O
Address
PCI_CFG2_VID Config2 Vendor
ID 0x01-0x00 n/a 0x0B 0x00
PCI_CFG2_DID Config2 Device
ID 0x03-0x02 n/a 0x0B 0x02
PCI_CFG2_CCODEL Config2 Class
Code[7:0],Rev
ID 0x08 n/a 0x0B 0x08
Table B-26. Function 1 Registers (Continued)
Register Name Description PCI
Address USB
Address DSP
I/O
Page DSP
I/O
Address