Analog Devices ADSP-21261 SHARC, Hardware Reference Manual

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I/O Processor Registers
A-150 ADSP-2126x SHARC Processor Hardware Reference
Input Data Port FIFO Register
(IDP_FIFO)
The
IDP_FIFO
register provides information about the output of the IDP
FIFO. Normally, the
IDP_FIFO
register is used only to read and remove
the top sample from the FIFO. However, the core may also write to this
register. When it does so, the audio data word is pushed into the input
side of the FIFO, as if it had come from the SRU on the channel encoded
in the three LSBs. This can be useful for verifying the operation of the
5 IDP_DMA_EN DMA Enable. Enables DMA on all IDP channels.
6 IDP_CLROVR FIFO Overflow Clear Bit. Writes of 1 to this bit will
clear the overflow condition in the DAI_STAT register.
Because this is a write-only bit; it always returns LOW
when read.
7 IDP_ENABLE Enable IDP. 1 to 0 transition on this bit clears the
IDP_FIFO.
1 = IDP is enabled
0 = IDP is disabled and data does not come to
IDP_FIFO from IDP channels
10–8 IDP_SMODE0 Serial Input Mode Select. These eight inputs (0-7), each
of which is 3-bits, indicate the mode of the serial input
for each of the eight IDP channels.
Input format:
000 = Left-justified Sample Pair mode
001 = I
2
S mode
010 = RESERVED
011 = RESERVED
100 = Right-justified 24-bits
101 = Right-justified 20-bits
110 = Right-justified 18-bits
111 = Right-justified 16-bits
13–11 IDP_SMODE1
16–14 IDP_SMODE2
19–17 IDP_SMODE3
22–20 IDP_SMODE4
25–23 IDP_SMODE5
28–26 IDP_SMODE6
31–29 IDP_SMODE7
Table A-46. IDP_CTL Register (Cont’d)
Bits Name Description