Analog Devices ADSP-21261 SHARC, Hardware Reference Manual

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ADSP-2126x SHARC Processor Hardware Reference A-111
Registers Reference
Parallel Port DMA Transmit Register (TXPP)
This register’s address is 0x1808. This Transmit Data register is a 32-bit
register that is part of the IOP register set and can be accessed by the core
or the DMA controller. Data is loaded into this register before being
transmitted. Prior to the beginning of a data transfer, data in the
TXPP
reg-
ister is automatically loaded into the Transmit Shift register. During a
DMA transmit operation, the data in
TXPP
is automatically loaded from
internal memory.
11-10 PPS Parallel Port FIFO Status. These read-only bits indicate
the status of the parallel port FIFO as follows: 00 =
RXPP/TXPP is empty
01 = RXPP/TXPP is partially full
11 = RXPP/TXPP is full
0
12 PPBHD Parallel Port Buffer Hang Disable. When cleared (= 0),
core stalls occur normally when the core attempts to write
to a full transmit buffer or read from an empty receive buf-
fer. Prevents a core hang when set (= 1). The old data pres-
ent in the receive buffer is read again if the core tries to
read it. If a write to the transmit buffer is performed, the
core will overwrite the current data in the buffer.
0
13 PPALEPL Parallel Port ALE Polarity Level. Asserts ALE active low if
set, (= 1) or active high if cleared, (= 0).
0
15–14 Reserved 0
16 PPDS DMA Status. Indicates that the internal DMA interface is
active if set, (= 1) or not active if cleared, (= 0).
0
17 PPBS Parallel Port Bus Status. Indicates that the external bus
interface is busy if set, (= 1) or available if cleared, (= 0).
The bus will be “busy” until one ALE cycle,
RD
cycle or
WR
cycle has taken place.
0
31–18 Reserved 0
Table A-33. Parallel Port Register (PPCTL) Bit Definitions (Cont’d)
Bit Name Definition Default