
ADSP-2126x SHARC Processor Hardware Reference
2-9
Processing Elements
During the
FPACK
operation, an overflow sets the
SV
condition and
non-overflow clears it. During the
FUNPACK
operation, the
SV
condition is
cleared. The
SZ
and
SS
conditions are cleared by both instructions.
Fixed-Point Formats
The DSP supports two 32-bit fixed-point formats—fractional and integer.
In both formats, numbers can be signed (twos-complement) or unsigned.
The four possible combinations are shown in
. In the fractional
format, there is an implied binary point to the left of the most significant
magnitude bit. In integer format, the binary point is understood to be to
the right of the LSB. Note that the sign bit is negatively weighted in a
twos-complement format.
ALU outputs always have the same width and data format as the inputs.
The multiplier, however, produces a 64-bit product from two 32-bit
inputs. If both operands are unsigned integers, the result is a 64-bit
unsigned integer. If both operands are unsigned fractions, the result is a
64-bit unsigned fraction. These formats are shown in
.
If one operand is signed and the other unsigned, the result is signed. If
both inputs are signed, the result is signed and automatically shifted left
one bit. The LSB becomes zero and bit 62 moves into the sign bit posi-
tion. Normally bit 63 and bit 62 are identical when both operands are
signed. (The only exception is full-scale negative multiplied by itself.)
Thus, the left-shift normally removes a redundant sign bit, increasing the
precision of the most significant product. Also, if the data format is frac-
tional, a single bit left-shift renormalizes the MSP to a fractional format.
The signed formats with and without left-shifting are shown in
The multiplier has an 80-bit accumulator to allow the accumulation of
64-bit products. For more information on the multiplier and accumula-
tor, see
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...