Core Registers
A-28
ADSP-2126x SHARC Processor Hardware Reference
Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions
Bit
Name
Definition
0
EMUI
Emulator Interrupt.
An EMUI occurs when the external emulator
triggers an interrupt or the core hits a emulator breakpoint.
Note this interrupt has highest priority, it is read-only and non-mas-
kable
1
RSTI
Reset Interrupt.
An RSTI occurs as an external device asserts the
RESET pin or after a software reset (SYSCTL register). Note this
interrupt is read-only and non-maskable.
2
IICDI
Illegal Input Condition Detected Interrupt.
An IICDI occurs when a
TRUE results from the logical OR’ing of the illegal I/O processor reg-
ister access (IIRA) and unaligned 64-bit memory access bits in the
STKYx registers.
3
SOVFI
Stack Overflow/Full Interrupt.
A SOVFI occurs when a stack in the
program sequencer overflows or is full.
4
TMZHI
Core Timer Expired High Priority.
A TMZHI occurs when the timer
decrements to zero. Note that this event also triggers a TMZLI. Since
the timer expired event (TCOUNT decrements to zero) generates two
interrupts, TMZHI and TMZLI, programs should unmask the timer
interrupt with the desired priority and leave the other one masked.
5
SPERRI
1
Sport Error Interrupt.
A SPERRI occurs on a FIFO underflow/over-
flow or a frame sync error.
6
BKPI
Hardware Breakpoint Interrupt.
When the processor is servicing
another interrupt, indicates if the BKPI interrupt is unmasked (if set,
= 1), or masked (if cleared, = 0).
7
Reserved
8
IRQ2
I
Hardware Interrupt.
An
IRQ2
I occurs when an external device asserts
the FLAG2 pin configured as
IRQ2
. The
IRQ2
E bit (MODE2) defines
if interrupt latched on edge or level.
9
IRQ1
I
Hardware Interrupt.
An
IRQ1
I occurs when an external device asserts
the FLAG2 pin configured as
IRQ1
. The
IRQ1
E bit (MODE2) defines
if interrupt latched on edge or level.
10
IRQ0
I
Hardware Interrupt.
An
IRQ0
I occurs when an external device asserts
the FLAG2 pin configured as
IRQ0
. The
IRQ0
E bit (MODE2) defines
if interrupt latched on edge or level.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...