
ADSP-2126x SHARC Processor Hardware Reference
11-7
Input Data Port
efficiency. The frame sync input is used to hold off latching of the next
sample (that is, ignore the clock edges). The data then flows through the
FIFO and is transferred by a dedicated DMA channel into the core’s
memory as with any IDP channel. As shown in
, the PDAP
can accept input words up to 20 bits wide, or can accept input words that
are packed as densely as four input words up to eight bits wide.
The
IDP_PDAP_CTL
register also provides a reset bit that zeros any data that
is waiting in the packing unit to be latched into the FIFO. When asserted,
the
IDP_PDAP_RESET
bit (bit 30 in the
IDP_PDAP_CTL
register) causes the
reset circuit to strobe, then automatically clear itself. Therefore, this bit
always returns a value of zero when read. The
IDP_PORT_SELECT
bit (bit 26
in the
IDP_PDAP_CTL
register) selects between the two sets of pins that may
be used as the parallel input port. When
IDP_PORT_SELECT
is set (= 1), the
upper 16 bits are read from the
AD[15:0]
. When
IDP_PORT_SELECT
is
cleared (= 0), the upper 16 bits are read from
DAI_P[20:5]
. Note that the
four least significant bits (LSBs) of the parallel port input are not multi-
plexed. These input bits are always read from Digital Audio Interface
(DAI) pins 4–1, as shown in
. The
DAI_P[4:1]
pins are always
connected as bits 3 through 0. A sample PDAP program is located at the
end of this chapter. See
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...