
SPI Data Transfer Operations
10-12
ADSP-2126x SHARC Processor Hardware Reference
SPI Data Transfer Operations
The following sections provide information on the two methods the
ADSP-2126x uses to transfer data; through the core or through DMA.
Core Transmit and Receive Operations
For core-driven SPI transfers, the software has to read from or write to the
RXSPI
and
TXSPI
registers to control the transfer. It is important to check
the buffer status before reading from or writing to these registers because
the core
does not
hang when it attempts to read from an empty buffer or
write to a full buffer. When the core writes to a full buffer, the data that is
in that buffer is overwritten and the SPI begins transmitting the new data.
Invalid data is obtained when the core reads from an empty buffer.
For a master, when the transmit buffer becomes empty, or the
receive buffer becomes full, the SPI device stalls the SPI clock until
it reads all the data from the receive buffer or it detects that the
transmit buffer contains a piece of data.
• For a master configured with
TIMOD
= 01: When the transmit buffer
becomes empty, the SPI device stalls the SPI clock until a piece of
data is written to the transmit buffer.
• For a master configured with
TIMOD
= 00: When the receive buffer
becomes full the SPI device stalls the SPI clock until all of the data
is read from the receive buffer.
SPI DMA
The SPI has a single DMA channel associated with it that can be config-
ured to support either an SPI transmit or a receive channel, but not both
simultaneously. In addition to the
TXSPI
and
RXSPI
data buffers, there is a
four-word deep DMA FIFO the SPI port uses to improve throughput.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...