
ADSP-2126x SHARC Processor Hardware Reference
1-3
Introduction
• Extended precision and dynamic range in the computation units
• Dual address generators with circular buffering support
• Efficient program sequencing
Fast, Flexible Arithmetic.
The ADSP-21000 family processors execute all
instructions in a single cycle. They provide fast cycle times and a complete
set of arithmetic operations. The processor is IEEE floating-point compat-
ible and allows either interrupt on arithmetic exception or latched status
exception handling.
Unconstrained Data Flow.
The ADSP-2126x processor has a Super Har-
vard Architecture combined with a ten-port data register file. In every
cycle, the processor can write or read two operands to or from the register
file, supply two operands to the ALU, supply two operands to the
multiplier, and receive three results from the ALU and multiplier. The
processor’s 48-bit orthogonal instruction word supports parallel data
transfers and arithmetic operations in the same instruction.
40-Bit Extended-Precision.
The processor handles 32-bit IEEE float-
ing-point format, 32-bit integer and fractional formats (twos-complement
and unsigned), and extended-precision 40-bit floating-point format. The
processors carry extended precision throughout their computation units,
limiting intermediate data truncation errors (up to 80 bits of precision are
maintained during multiply-accumulate operations).
Dual Address Generators.
The processor has two Data Address Genera-
tors (DAGs) that provide immediate or indirect (pre- and post-modify)
addressing. Modulus, bit-reverse, and broadcast operations are supported
with no constraints on data buffer placement.
Efficient Program Sequencing.
In addition to zero-overhead loops, the
processor supports single-cycle setup and exit for loops. Loops are both
nestable (six levels in hardware) and interruptible. The processors support
both delayed and non-delayed branches.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...