
Frame Sync Options
9-36
ADSP-2126x SHARC Processor Hardware Reference
Active Low Versus Active High Frame Syncs
Frame sync signals may be active high or active low (for example,
inverted). The
LFS
bit of the
SPCTLx
Control register determines the frame
sync’s logic level.
• When
LFS
is cleared (=0), the corresponding frame sync signal is
active high.
• When
LFS
is set (=1), the corresponding frame sync signal is active
low.
Active high frame syncs are the default. The
LFS
bit is initialized to zero
after a processor reset.
Active low or active high frame syncs are selected using the
LTDV
and
LRFS
bits. These bits are located in the
SPCTLx
Control registers.
Sampling Edge for Data and Frame Syncs
Data and frame syncs can be sampled on the rising or falling edges of the
serial port clock signals. The
CKRE
bit of the
SPCTLx
Control registers
selects the sampling edge.
For sampling receive data and frame syncs, setting
CKRE
to 1 in the
SPCTLx
register selects the rising edge of
SPORTx_CLK
. When
CKRE
is cleared (=0),
the processor selects the falling edge of
SPORTx_CLK
for sampling receive
data and frame syncs. Note that transmit data and frame sync signals
change their state on the clock edge that is not selected.
For example, the transmit and receive functions of any two serial ports
connected together should always select the same value for
CKRE
so inter-
nally-generated signals are driven on one edge and received signals are
sampled on the opposite edge.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...