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Setting Up DMA Parameter Registers
7-26
ADSP-2126x SHARC Processor Hardware Reference
Addressing
shows a block diagram of the I/O processor’s address generator
(DMA controller).
lists the parameter registers for each DMA
channel. The parameter registers are uninitialized following a processor
reset.
The I/O processor generates addresses for DMA channels much the same
way that the Data Address Generators (DAGs) generate addresses for data
memory accesses. Each channel has a set of parameter registers including
an index register and modify register that the I/O processor uses to address
a data buffer in internal memory. The index register must be initialized
with a starting address for the data buffer. As part of the DMA operation,
the I/O processor outputs the address in the index register onto the pro-
cessor’s I/O address bus and applies the address to internal memory
during each DMA cycle—a clock cycle in which a DMA transfer is taking
place.
All addresses in the index registers are offset by a value matching the pro-
cessor’s first internal normal word addressed RAM location, before the
I/O processor uses the addresses. For the ADSP-2126x processor, this off-
set value is 0x0008 0000.
DMA addresses must always be normal word (32-bit) memory, and inter-
nal memory data transfer sizes are 32 bits. External data transfer sizes may
be 16 or 8 bits. The I/O processor can transfer short word data (16-bit)
using the packing capability of the serial port and SPI port DMA
channels.
After transferring each data word to or from internal memory, the I/O
processor adds the modify value to the index register to generate the
address for the next DMA transfer and writes the modified index value to
the index register. The modify value in the modify register is a signed inte-
ger, which allows both increment and decrement modifies. The modify
value can have any positive or negative integer value.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...