
IOP/Core Interaction Options
7-18
ADSP-2126x SHARC Processor Hardware Reference
Managing DMA Channel Priority
The default channel priority is: DMA channel 0 as highest priority and
DMA channel 22 as lowest priority.
DMA channels in priority order. When a channel becomes the highest
priority requester, the I/O processor services the channel’s request. In the
next clock cycle, the I/O processor starts the DMA transfer.
The I/O data (IOD) bus is 32 bits wide and is the only path that the IOP
uses to transfer data between internal memory and the peripherals. When
there are two or more peripherals with active DMAs in progress, they may
all require data to be moved to or from memory in the same cycle. For
example, the parallel port may fill its
RXPP
buffer just as a SPORT shifts a
word into its
RXn
buffer. To determine which word is transferred first, the
DMA channels for each of the processor’s I/O ports negotiate channel pri-
ority with the I/O processor using an internal DMA request/grant
handshake.
Each I/O port has one or more DMA channels, and each channel has a
single request and a single grant. When a particular channel needs to read
or write data to internal memory, the channel asserts an internal DMA
request. The I/O processor prioritizes the request with all other valid
DMA requests. When a channel becomes the highest priority requester,
the I/O processor asserts the channel’s internal DMA grant. In the next
clock cycle, the DMA transfer starts.
paths for internal DMA requests within the I/O processor.
If a DMA channel is disabled (
PPDEN
,
SPIDEN
,
SDEN
, or
IDP_DMA_EN
bits =0), the I/O processor does not issue internal DMA grants to
that channel (whether or not the channel has data to transfer).
The default DMA channel priority is
fixed prioritization
by DMA channel
group (serial ports, parallel port, IDP, or SPI port).
lists the DMA channels in descending order of priority.
For information on programming serial port priority modes, see
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...