
Accessing Memory
5-24
ADSP-2126x SHARC Processor Hardware Reference
When data is accessed using long word addressing, the data is always long
word aligned on 64-bit boundaries in internal memory space. When data
is accessed using normal word addressing and the
LW
mnemonic, the pro-
gram should maintain this alignment by using an even normal word
address (least significant bit of address = 0). This register selection aligns
the normal word address with a 64-bit boundary (long word address).
All long word accesses load or store two consecutive 32-bit data values.
The register file source or destination of a long word access is a set of two
neighboring data registers in a processing element. In a forced long word
access (uses the
LW
mnemonic), the even (normal word address) location
moves to or from the explicit register in the neighbor-pair, and the odd
(normal word address) location moves to or from the implicit register in
the neighbor-pair. For example, the following long word moves could
occur:
DM(0x80000) = R0 (LW);
/* The data in R0 moves to location DM(0x80000), and the data in
R1 moves to location DM(0x80001) */
R0 = DM(0x80003)(LW);
/* The data at location DM(0x80002) moves to R0, and the data at
location DM(0x80003) moves to R1 */
The example shows that
R0
and
R1
are neighbor registers in the same pro-
cessing element.
lists the other neighbor register assignments
that apply to long word accesses.
In unforced long word accesses (accesses to
LW
memory space), the DSP
places the lower 32 bits of the long word in the named (explicit) register
and places the upper 32 bits of the long word in the neighbor (implicit)
register.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...