
Interrupts and Sequencing
3-58
ADSP-2126x SHARC Processor Hardware Reference
Nesting Interrupts
The sequencer supports interrupt nesting—responding to another inter-
rupt while a previous interrupt is being serviced. Bits in the
MODE1
,
IMASKP
,
and
LIRPTL
registers control interrupt nesting as described below.
•
Interrupt Nesting enable.
MODE1
Bit 11 (
NESTM
). This bit directs
the DSP to enable (if 1) or disable (if 0) interrupt nesting.
•
Interrupt Mask Pointer.
IMASKP
bits. These bits list the interrupts
in priority order and provide a temporary interrupt mask for each
nesting level.
•
SPI Port DMA Transmit or Receive Interrupt Mask Pointer.
LIRPTL
Bit 29 (
SPILIMSKP
). This bit is for the SPI port transmit or
receive DMA interrupt. It provides a temporary interrupt mask.
•
General-Purpose IOP Timer Interrupt Mask Pointer.
LIRPTL
Bits
24 and 28 (
GPTMR1MSKP
and
GPTMR2MSKP
). These bits are for the
general purpose IOP timer 1 and timer 2 interrupts, respectively.
They provide a temporary interrupt mask.
•
Serial Port Interrupt Mask Pointer.
LIRPTL
Bits 22-20
(
SPxMSKP
). These bits are for the serial port interrupts (
SP0
,
SP2
,
and
SP4
). They provide a temporary interrupt mask.
•
DAI Low Priority Interrupt Mask Pointer.
LIRPTL
Bit 26
(
DAILIMSKP
). This bit is for the DAI low priority interrupt. It pro-
vides a temporary interrupt mask.
When interrupt nesting is enabled, a higher priority interrupt can inter-
rupt a lower priority interrupt’s service routine. Lower priority interrupts
are latched as they occur, but the DSP processes them according to their
priority after the nested routines finish.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...