
Instruction Pipeline
3-4
ADSP-2126x SHARC Processor Hardware Reference
Instruction Pipeline
The program sequencer determines the next instruction address by exam-
ining both the current instruction being executed and the current state of
the processor. If no conditions require otherwise, the DSP fetches and exe-
cutes instructions from memory in sequential order.
To achieve a high execution rate while maintaining a simple programming
mode, the DSP employs a three stage pipeline to process instructions:
1.
Fetch cycle.
The DSP reads the instruction from either the on-chip
memory or the instruction cache.
2.
Decode cycle.
The DSP decodes the instruction, generating condi-
tions that control instruction execution and program flow.
3.
Execute cycle.
The DSP executes the instruction; the operations
specified by the instruction complete in a single cycle.
In a sequential program flow, when one instruction is being executed, the
next instruction is being decoded, and the instruction following that is
being fetched. Sequential program flow usually has a throughput of one
instruction per cycle. In the event of cache misses, instructions may take
more than one cycle.
illustrates how the instructions starting at address 0x08 are
processed by the pipeline. While the instruction at address 0x08 is being
executed, the instruction 0x09 is being decoded and the instruction at
address 0xA is being fetched.
While sequential execution takes one core clock cycle per instruction,
branching (nonsequential executions) can temporarily reduce this rate.
Nonsequential program operations include:
• Program memory data accesses that conflict with instruction
fetches
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...