3.3.2 Using the AD1819A SoundPort Codec as the Analog Front End
There are two ways you can use the AD1819 SoundPort codec on the 21065L EZ-KIT Lite
with the Vi+ debugger.
Method 1
— Use the codec DMA buffers and the codec interrupt handler within the
EPROM monitor that are installed by the AD1819/SPORT1 initialization
routine in the EPROM Monitor Program. This method is useful if you want
to quickly test your DSP algorithm.
This method may be preferable for early DSP evaluation, and the user does not need to be
concerned with many of the details of the AD1819 theory of operation. The following
section provides coding guidelines for the programmer to link in the required codec and
SPORT DMA buffers. All of the audio demos provided with the ADSP-21065L EZ-KIT
Lite use this method for communicating with the codec for RS-232 host codec control.
Method 2
— Disabling and Overwriting the SPORT1 DMA codec buffers, and down-
loading a custom AD1819/SPORT1 initialization routine with the RS-232
monitor.
The custom user routine includes instructions necessary to reset the codec, program
SPORT1, activates serial port 1 transmit and receive DMA transfers, and programs any
AD1819a register to a desired configuration. This method may be preferable if you want to
test AD1819 code that may be downloaded via the SHARC JTAG, burnt into a new
EPROM, or to test AD1819 functionality in a new custom-based 21065L design.
For detailed AD1819 and SHARC interface information and example source that demon-
strates this second method, contact Analog Devices DSP hotline or search our web site for
the following document:
Interfacing The ADSP-21065L SHARC DSP to the AD1819a 'AC-
97' SoundPort codec.
Further information on the AC-97 serial protocol may be found in the
AD1819A Datasheet.
3.3.3 Method 1: Using the Monitor’s Codec DMA Buffers and
Interrupt Handler
This section provides more detail on Method 1 from the previous section. The ADSP-
21065L uses DMA transfers to automatically send and receive data from the codec. After
codec reset, the codec begins transmitting the clock used to synchronously transfer data
across SPORT1. The ADSP-21065L, in turn, initiates all transmissions with the codec by
sending a frame synchronization pulse. Even though the codec transmits the data clock, it
may not be ready for normal operation. While the codec is not ready it holds the first bit
(codec Ready bit) of SLOT 0 low. When ready, this bit is driven high. Once this bit goes
high, the codec is ready for standard communication with the ADSP-21065L.
The AD1819 initially expects all data transfers to be in packets according the AC'97 spec-
ification, where there is 1 x 16-bit time slot and 12 x 20 bit slots in the TDM audio frame.
This packet scheme does not work well in DMA transfer schemes, nor to standard Multi-
channel Mode data transfers with the ADSP-21065L, which expects all slots to be the same
number of bits. To realign your data, set the SLOT16 bit in the AD1819’s Serial
Configuration register as soon the serial port is enabled. To do this, the program must per-
form a single transfer using the initial packing style.
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