Preliminary Technical Data
UG-1828
Rev. PrC | Page 9 of 338
The ADC in the receive chain possesses a high dynamic range. Assuming a mixer gain of 0 dB, the ADC’s noise and maximum input
power referred to the RF input are -142 dBm/Hz and 8.6 dBm, respectively. These levels translate into a dynamic range in excess of 150 dB on a
per Hertz basis. Taking into account the digital filtering and AGC loops, an even greater dynamic range can be achieved.
Given the high dynamic range of the receiver ADC, very little channelization or blocker filtering occurs in the analog signal chain since
the ADC can simultaneously absorb weak signals and large blockers. Blocker suppression and channelization are then achieved in the
digital signal path.
If reciprocal mixing of the RX LO phase noise by a large blocker close to the desired channel significantly degrades blocking performance,
a lower phase noise external LO source can be used in place of the on-board RFPLLs.
The receive path also contains two types of ADCs connected to the chip’s RF front end, that allow for the trade-off between power
consumption and dynamic range: a high performance ADC, and low power ADC that possess degraded dynamic range. Users can trade-
off receive channel dynamic range and power consumption by selecting between either set of ADCs.
Power Consumption Modes
The
provides users with various levels of power control. Power scaling on individual analog signal path blocks can be
performed to trade-off power and performance. In addition, enabling and disabling various blocks in TDD RX and TX frames to reduce
power can be customized, at the expense of RX/TX or TX/RX turnaround time.
A specialized “RX Monitor mode” exists that allows the
to autonomously poll a region of the spectrum for the presence of a
signal, while in a low power state. In this mode, the chip continuously cycles through sleep-detect-sleep states controlled by an internal
state machine. Power savings are achieved by ensuring that the sleep duty cycle is greater than the “detect” duty cycle.
In the “sleep” state, the chip is in a minimal power consumption configuration where few functions are enabled. After a pre-determined
period, the chip enters the “detect” state. In this state, the chip enables a receiver and performs a power measurement over a bandwidth
and at a RX LO frequency determined by the user. If the measured power level in the bandwidth is greater than a user-determined
threshold, the “Monitor Mode” state machine exits its cycle. Following the loop exit, an interrupt is provided via a GPIO pin to the user’s
baseband processor, and the entire receiver analog and digital chains within the
are powered up, assuming that normal signal
reception resumes due to the detection of a channel.
If the power measured over the bandwidth is less than the user-determined threshold, the chip resumes its sleep-detect-sleep cycle. The
sleep-detect duty cycle and durations, power measurement threshold, and RX LO are user-programmable, and are set before enabling
monitor mode.
Note that frequency hopping can be combined with monitor mode, allowing the
to dynamically change the RX LO while
performing the power measurement function.
The ADRV9003 delivers all features offered by
transceiver. Differences between
•
RF IOs. The ADRV9003 offers two receivers and one transmitter.
•
Digital predistortion functionality is not supported by the ADRV9003.
The ADRV9004 delivers all features offered by
transceiver. Differences between
•
Digital predistortion functionality is not supported by the ADRV9004.
