Analog Devices AD9574, Schematic

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PPR1=0,2,4, C2=1NF, R2=0OHM
PPR1=1,3,5, C2=2NF, R2=0OHM
PPR1=6,7, C2=2NF, R2=4.75KOHM
PLEASE PLACE CLOSE TO THE PART
EXTERNAL LPF CIRCUITS
CURRENT ESTIMATION:180 MA
DEFAULT: CONNECT PIN2 AND PIN3
REF1
RESETB
REF0
PPR WITH MONITOR
DEFAULT: CONNECT PIN2 AND PIN3
AND ENABLE OR DISABLE XO OF REF_IN
THIS CONNECTOR IS USED FOR DEBUGGING
PPR W/O MONITOR
REF IN SELECT
REF MONITOR SELECT
IT'S BETTER TO PLACE THE POWER SUPPLY VIA BEFORE BYPASS CAP AND PART
CAN SUPPRESS THE SPUR OF CMOS OUPTUTS MORE THAN 10DB
REPLACING R103 AND R108 WITH 600OHM OR LARGER FERRIT BEAD
DEFAULT DISABLE: CONNECT XO0_EN AND XO1_EN WITH GND
XO IS DISABLED WHEN CONNECTED WITH GND
AD9574
1 4
<DESIGN_VIEW>
: N/A
Product(s): AD9574 Customer Board
HW TYPE : Customer Evaluation
1:1
A
02_036355
Liang Xu
0.47UF
2000PF
0
0
DNI
0
0
0
0
0
0
74LVC541APW
0
0.1UF
300
300
300
300
0.1UF
3.9K
SAMTECTSW10608GS3PIN
3.9K
300
3.9K
TLMS1100-GS08 (RED)
TLMS1100-GS08 (RED)
TLMS1100-GS08 (RED)
TLMS1100-GS08 (RED)
0.1UF
600OHM
0.1UF
TLMS1100-GS08 (RED)
TSW-106-08-G-D TSW-106-08-G-D
SAMTECTSW10608GS3PIN
3.9K
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
600OHM
7914J-1-000E
3.9K
AD9574BCPZ
C122
R115
P102
P103 P103
DS102
C116
R108
C106
DS106
R125
P101
R112
C128
C129
R124
U301
U101
R116
S100
R103
C102
C104
C108
C110
C112
C114
C118
C120
R130
DS103
DS104
DS105
R114 R113
R127
R126
R129
R128
R118
R120
R119
R121
R122
R123
R2
C2
C123
LD REF_FREQ_L
REF0P
VDD_REF0
REF0N
VDD_REF1
REF1P
REF1N
PPR2
VDD_OUT0/1
OUT0N
OUT0P
OUT1P
OUT1N
GND
LDO_BYPASS
LF
VDD_PLL LD LF LDO_BYPASS VDD_VCO VDD_RFDIV PPR6 RESETB OUT6P OUT6N VDD_OUT6 PPR5
OUT4N
VDD_OUT5
REF_FREQ_L
REF_FREQ_H
VDD_OUT2/3
OUT5N
OUT5P
OUT4P
VDD_OUT4
REFMON
PPR4
PPR3
PPR0 REF_SEL
GND
OUT2N OUT2P OUT3P OUT3N PPR1 VDD_MCLK_DIG REF_SWITCH REF_ACTIVE MCLKP MCLKN
3V3_9574
REF_ACTIVE
REF_FREQ_H
REF_FREQ_L
LD
REF_SWITCH
3V3_9574
GND
GND
GND
RESETB
GND
3V3_9574
3V3_9574
REF_SEL
GND
GND
3V3_9574
REF_ACTIVE
REF_SWITCH
XO0_EN
XO1_EN
REF_FREQ_H
GND
GND
GND
GND
VDD_OUT0/1
VDD_OUT6
GND
GND
GND
GND
REFMON
RESETB
REF_SEL
GND
REFMON
GND
VDD_OUT5
VDD_OUT4
VDD_OUT2/3
VDD_RFDIV
VDD_VCO
VDD_MCLK_DIG
VDD_PLL
VDD_REF0
VDD_REF1
GND
GND
GND
GND
GND
GND
GND
GND
GND
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3V3_9574
3 2 1
12
10
8
6
4
2
11
9
7
5
3
1
A C
2 1
A C
3 2 1
20
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
10
19 1
17 18
4
3
13
36
23
31
30
8
42
20
25
43 48
34
35
44
6
5
1
2
19 24
26
27
7
41 47 PAD
22 21
32
33
29
28
39 40 38 37
11
12
10
9
45 46
15 16 14
2B
2A
1B
1A
2 1
A C
A C
A C
PAD
REF_SEL
PPR0
MCLK_N
MCLK_P
REF_ACT
REF_SW
VDD_MCLK
PPR1
OUT3_N
OUT3_P OUT2_P
OUT2_N
VDD_OUT23
REF_FHI
REF_FLO
OUT5_N
OUT5_P
VDD_OUT5
VDD_OUT4
OUT4_P
OUT4_N
PPR3
PPR4
REFMON
PPR5 VDD_OUT6 OUT6_N OUT6_P RESET_N PPR6 VDD_RFDIV VDD_VCO LDO_BYP LF LD VDD_PLL
OUT1_N
OUT1_P
OUT0_P
OUT0_N
VDD_OUT01
PPR2
REF1_N/XTAL1_B
REF1_P/XTAL1_A
VDD_REF1
REF0_N/XTAL0_B
VDD_REF0
REF0_P/XTAL0_A
EN2_N EN1_N
O7
O6
O5
O4
O3
O2
O1
O0
I7
I6
I5
I4
I3
I2
I1
I0
GND VCC
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
A
C
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
6 7
8
A
B
C
C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
O L G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
A N
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
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DATE