UG-386
AD9642/AD9634/AD6672 User Guide
When connecting the analog input source, use of a multipole,
narrow-band, band-pass filter with 50 Ω terminations is recom-
mended. Analog Devices, Inc., uses TTE and K&L Microwave,
Inc., band-pass filters. The filters should be connected directly
to the evaluation board.
If an external clock source is used, it should also be supplied
with a clean signal generator as previously specified. Typically,
most Analog Devices evaluation boards can accept ~2.8 V p-p or
13 dBm sine wave input for the clock.
OUTPUT SIGNALS
The default setup uses the Analog Devices high speed converter
evaluation platform (
) for data capture. The
output signals from Channel A and Channel B for the
are routed through P601 and P602,
respectively, to the FPGA on the data capture board.
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
This section explains the default and optional settings or modes
allowed on the
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P201.
Analog Input
The A and B channel inputs on the evaluation board are set up for a
double balun-coupled analog input with a 50 Ω impedance. This
input network is optimized to support a wide frequency band. See
the
data sheets for additional
information on the recommended networks for different input
frequency ranges. The nominal input drive level is 10 dBm to
achieve 2 V p-p full scale into 50 Ω. At higher input frequencies,
slightly higher input drive levels are required due to losses in the
front-end network.
Optionally, Channel A and Channel B inputs on the board can
be configured to use the
digitally controlled, variable
gain wide bandwidth amplifier. The
component is
included on the evaluation board at U401. However, the path into
and out of the
can be configured in many different
ways depending on the application; therefore, the parts in the
input and output path are left unpopulated. See the
data sheet for additional information on this part and for
configuring the inputs and outputs. The
, by default,
is held in power-down mode but can be enabled by adding 1 kΩ
resistors at R427 and R428 to enable Channel A and Channel B,
respectively.
Clock Circuitry
The default clock input circuit that is populated on the
evaluation board uses a simple transformer-
coupled circuit with a high bandwidth 1:1 impedance ratio
transformer (T503) that adds a very low amount of jitter to the
clock path. The clock input is 50 Ω terminated and ac-coupled
to handle single-ended sine wave types of inputs. The trans-
former converts the single-ended input to a differential signal
that is clipped by CR503 before entering the ADC clock inputs.
The board is set by default to use an external clock generator. An
external clock source capable of driving a 50 Ω terminated input
should be connected to J506.
A differential LVPECL clock driver output can also be used to
clock the ADC input using the
into the clock path, populate R541 and R542 with 0 Ω
resistors and remove C532 and C533 to disconnect the default
clock path inputs. In addition, populate R533 and R534 with
0 Ω resistors, remove R522 and R523 to disconnect the default
clock path outputs, and insert
LVPECL Output 2. The
must be configured through the SPI controller software
to set up the PLL and other operation modes. Consult the
data sheet for more information about these and other
options.
PDWN
To enable the power-down feature, Bits[1:0] of Register 0x08 must
be written for the desired power-down mode.
OEB
To disable the digital output pins and place them in a high imped-
ance state, Bit 4 of Register 0x14 must be written.
AD9642/AD9634/
AD6672
15Ω
0.1µF
2V p-p
VIN+
VIN–
VCM
3.9pF
3.9pF
15Ω
0.1µF
S
0.1µF
3.9pF
36Ω
36Ω
S
P
A
P
49.9Ω
49.9Ω
10593-
003
Figure 3. Default Analog Input Configuration of the
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