AS7030B/AS7038GB/AS7038RB
AS7030B/AS7038GB/AS7038RB Overview
Eval Kit Manual
• PUBLIC
UG001014
• v1-00 • 2021-May-06
53
│ 17
4.4
Light-to-Frequency Converter (LTF)
The LTF module can use any of the photodiodes. Photodiodes connected to the LTF cannot be used
at the same time with TIA. Integration time (itime) is configured in unit steps, one unit step is 3.702 ms.
The unit step can be reduced by 2, 4 or 8, this also reduces the resolution of the conversion. The LTF
modulator can be set to run continuously and write the result of each integration to the FIFO.
Figure 15:
Light-to-Frequency Converter
4.5
ADC and FIFO
4.5.1
ADC
The ADC is a 14-bit successive approximation register type with input clock of 1 MHz. A configurable
clock divider can reduce the input clock. One conversion takes 25 clock cycles plus configurable
number of ADC settling clock cycles (64 the default for ADC settling cycles).The ADC can be manually
triggered by register or automatically triggered by the built-in sampling sequencer. Two channel
selection registers ADC_CHANNEL_MASK_L and ADC_CHANNEL_MASK_H define the channels the
ADC will convert. The ADC will start with the channels in ADC_CHANNEL_MASK_L from the LS
asserted bit to the MS asserted bit, then continue with the channels in ADC_CHANNEL_MASK_H
register again from LS asserted bit to MS asserted bit. Then wraps back to the LS bit of
ADC_CHANNEL_MASK_L. Thus, the ADC will go through each channel in the order as shown in
Figure 16 with TIA being the first (smallest index), OFE1 second, SD1 third and so on to the GPIO2
being the last.
