Appendix A
Specifications
System Synchronization Clocks
(PXI_CLK10, PXIe_CLK100, PXIe_SYNC100)
10 MHz System Reference Clock: PXI_CLK10
Maximum slot-to-slot skew ....................250 ps
Accuracy .................................................±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter .......................................5 ps RMS phase-jitter
(10 Hz–1 MHz range)
Duty-factor..............................................45%–55%
Unloaded signal swing............................3.3 V ±0.3 V
Note
For other specifications refer to the
PXI-1 Hardware Specification
.
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe-SYNC100
Maximum slot-to-slot skew ....................100 ps
Accuracy .................................................±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter .......................................3 ps RMS phase-jitter
(10 Hz–12 kHz range)
2 ps RMS phase-jitter
(12 kHz–20 MHz range)
Duty-factor for PXIe_CLK100...............45%–55%
Absolute differential voltage
(When terminated with a 50
Ω
load
to 1.30 V or Thévenin equivalent)..........400–1000 mV
Single-ended V
OH
...................................2.0–2.5 V
Note
For other specifications, refer to the
PXI-5 PXI Express Hardware Specification
.
Manual
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